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18#ifndef _ATH5K_H
19#define _ATH5K_H
20
21
22
23
24#define CHAN_DEBUG 0
25
26#include <linux/io.h>
27#include <linux/interrupt.h>
28#include <linux/types.h>
29#include <linux/average.h>
30#include <linux/leds.h>
31#include <net/mac80211.h>
32
33
34
35#include "desc.h"
36
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38
39
40#include "eeprom.h"
41#include "debug.h"
42#include "../ath.h"
43#include "ani.h"
44
45
46#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007
47#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011
48#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012
49#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013
50#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013
51#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013
52#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207
53#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014
54#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107
55#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113
56#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112
57#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013
58#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12
59#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b
60#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052
61#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057
62#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058
63#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014
64#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015
65#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016
66#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017
67#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018
68#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019
69#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a
70#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b
71#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c
72#define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023
73#define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024
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78
79#define ATH5K_PRINTF(fmt, ...) \
80 pr_warn("%s: " fmt, __func__, ##__VA_ARGS__)
81
82void __printf(3, 4)
83_ath5k_printk(const struct ath5k_hw *ah, const char *level,
84 const char *fmt, ...);
85
86#define ATH5K_PRINTK(_sc, _level, _fmt, ...) \
87 _ath5k_printk(_sc, _level, _fmt, ##__VA_ARGS__)
88
89#define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) \
90do { \
91 if (net_ratelimit()) \
92 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \
93} while (0)
94
95#define ATH5K_INFO(_sc, _fmt, ...) \
96 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)
97
98#define ATH5K_WARN(_sc, _fmt, ...) \
99 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)
100
101#define ATH5K_ERR(_sc, _fmt, ...) \
102 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)
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110
111#define AR5K_REG_SM(_val, _flags) \
112 (((_val) << _flags##_S) & (_flags))
113
114
115#define AR5K_REG_MS(_val, _flags) \
116 (((_val) & (_flags)) >> _flags##_S)
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122
123#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \
124 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
125 (((_val) << _flags##_S) & (_flags)), _reg)
126
127#define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \
128 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
129 (_mask)) | (_flags), _reg)
130
131#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \
132 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
133
134#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \
135 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
136
137
138#define AR5K_REG_READ_Q(ah, _reg, _queue) \
139 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
140
141#define AR5K_REG_WRITE_Q(ah, _reg, _queue) \
142 ath5k_hw_reg_write(ah, (1 << _queue), _reg)
143
144#define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \
145 _reg |= 1 << _queue; \
146} while (0)
147
148#define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \
149 _reg &= ~(1 << _queue); \
150} while (0)
151
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153#define AR5K_REG_WAIT(_i) do { \
154 if (_i % 64) \
155 udelay(1); \
156} while (0)
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161
162#define AR5K_TUNE_DMA_BEACON_RESP 2
163#define AR5K_TUNE_SW_BEACON_RESP 10
164#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
165#define AR5K_TUNE_MIN_TX_FIFO_THRES 1
166#define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_FRAME_LEN / 64) + 1)
167#define AR5K_TUNE_REGISTER_TIMEOUT 20000
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170#define AR5K_TUNE_RSSI_THRES 129
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176#define AR5K_TUNE_BMISS_THRES 7
177#define AR5K_TUNE_REGISTER_DWELL_TIME 20000
178#define AR5K_TUNE_BEACON_INTERVAL 100
179#define AR5K_TUNE_AIFS 2
180#define AR5K_TUNE_AIFS_11B 2
181#define AR5K_TUNE_AIFS_XR 0
182#define AR5K_TUNE_CWMIN 15
183#define AR5K_TUNE_CWMIN_11B 31
184#define AR5K_TUNE_CWMIN_XR 3
185#define AR5K_TUNE_CWMAX 1023
186#define AR5K_TUNE_CWMAX_11B 1023
187#define AR5K_TUNE_CWMAX_XR 7
188#define AR5K_TUNE_NOISE_FLOOR -72
189#define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95
190#define AR5K_TUNE_MAX_TXPOWER 63
191#define AR5K_TUNE_DEFAULT_TXPOWER 25
192#define AR5K_TUNE_TPC_TXPOWER false
193#define ATH5K_TUNE_CALIBRATION_INTERVAL_FULL 60000
194#define ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT 10000
195#define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI 1000
196#define ATH5K_TX_COMPLETE_POLL_INT 3000
197
198#define AR5K_INIT_CARR_SENSE_EN 1
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200
201#if defined(__BIG_ENDIAN)
202#define AR5K_INIT_CFG ( \
203 AR5K_CFG_SWTD | AR5K_CFG_SWRD \
204)
205#else
206#define AR5K_INIT_CFG 0x00000000
207#endif
208
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210#define AR5K_INIT_CYCRSSI_THR1 2
211
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213#define AR5K_INIT_RETRY_SHORT 7
214#define AR5K_INIT_RETRY_LONG 4
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217#define AR5K_INIT_SLOT_TIME_TURBO 6
218#define AR5K_INIT_SLOT_TIME_DEFAULT 9
219#define AR5K_INIT_SLOT_TIME_HALF_RATE 13
220#define AR5K_INIT_SLOT_TIME_QUARTER_RATE 21
221#define AR5K_INIT_SLOT_TIME_B 20
222#define AR5K_SLOT_TIME_MAX 0xffff
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225#define AR5K_INIT_SIFS_TURBO 6
226#define AR5K_INIT_SIFS_DEFAULT_BG 10
227#define AR5K_INIT_SIFS_DEFAULT_A 16
228#define AR5K_INIT_SIFS_HALF_RATE 32
229#define AR5K_INIT_SIFS_QUARTER_RATE 64
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234#define AR5K_INIT_OFDM_PREAMPLE_TIME 20
235
236#define AR5K_INIT_OFDM_PREAMBLE_TIME_MIN 14
237#define AR5K_INIT_OFDM_SYMBOL_TIME 4
238#define AR5K_INIT_OFDM_PLCP_BITS 22
239
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241#define AR5K_INIT_RX_LAT_MAX 63
242
243
244#define AR5K_INIT_TX_LAT_A 54
245#define AR5K_INIT_TX_LAT_BG 384
246
247#define AR5K_INIT_TX_LAT_MIN 32
248
249#define AR5K_INIT_TX_LATENCY_5210 54
250#define AR5K_INIT_RX_LATENCY_5210 29
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253#define AR5K_INIT_TXF2TXD_START_DEFAULT 14
254#define AR5K_INIT_TXF2TXD_START_DELAY_10MHZ 12
255#define AR5K_INIT_TXF2TXD_START_DELAY_5MHZ 13
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259#define AR5K_SWITCH_SETTLING 5760
260#define AR5K_SWITCH_SETTLING_TURBO 7168
261
262#define AR5K_AGC_SETTLING 28
263
264#define AR5K_AGC_SETTLING_TURBO 37
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278enum ath5k_version {
279 AR5K_AR5210 = 0,
280 AR5K_AR5211 = 1,
281 AR5K_AR5212 = 2,
282};
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295enum ath5k_radio {
296 AR5K_RF5110 = 0,
297 AR5K_RF5111 = 1,
298 AR5K_RF5112 = 2,
299 AR5K_RF2413 = 3,
300 AR5K_RF5413 = 4,
301 AR5K_RF2316 = 5,
302 AR5K_RF2317 = 6,
303 AR5K_RF2425 = 7,
304};
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310#define AR5K_SREV_UNKNOWN 0xffff
311
312#define AR5K_SREV_AR5210 0x00
313#define AR5K_SREV_AR5311 0x10
314#define AR5K_SREV_AR5311A 0x20
315#define AR5K_SREV_AR5311B 0x30
316#define AR5K_SREV_AR5211 0x40
317#define AR5K_SREV_AR5212 0x50
318#define AR5K_SREV_AR5312_R2 0x52
319#define AR5K_SREV_AR5212_V4 0x54
320#define AR5K_SREV_AR5213 0x55
321#define AR5K_SREV_AR5312_R7 0x57
322#define AR5K_SREV_AR2313_R8 0x58
323#define AR5K_SREV_AR5213A 0x59
324#define AR5K_SREV_AR2413 0x78
325#define AR5K_SREV_AR2414 0x70
326#define AR5K_SREV_AR2315_R6 0x86
327#define AR5K_SREV_AR2315_R7 0x87
328#define AR5K_SREV_AR5424 0x90
329#define AR5K_SREV_AR2317_R1 0x90
330#define AR5K_SREV_AR2317_R2 0x91
331#define AR5K_SREV_AR5413 0xa4
332#define AR5K_SREV_AR5414 0xa0
333#define AR5K_SREV_AR2415 0xb0
334#define AR5K_SREV_AR5416 0xc0
335#define AR5K_SREV_AR5418 0xca
336#define AR5K_SREV_AR2425 0xe0
337#define AR5K_SREV_AR2417 0xf0
338
339#define AR5K_SREV_RAD_5110 0x00
340#define AR5K_SREV_RAD_5111 0x10
341#define AR5K_SREV_RAD_5111A 0x15
342#define AR5K_SREV_RAD_2111 0x20
343#define AR5K_SREV_RAD_5112 0x30
344#define AR5K_SREV_RAD_5112A 0x35
345#define AR5K_SREV_RAD_5112B 0x36
346#define AR5K_SREV_RAD_2112 0x40
347#define AR5K_SREV_RAD_2112A 0x45
348#define AR5K_SREV_RAD_2112B 0x46
349#define AR5K_SREV_RAD_2413 0x50
350#define AR5K_SREV_RAD_5413 0x60
351#define AR5K_SREV_RAD_2316 0x70
352#define AR5K_SREV_RAD_2317 0x80
353#define AR5K_SREV_RAD_5424 0xa0
354#define AR5K_SREV_RAD_2425 0xa2
355#define AR5K_SREV_RAD_5133 0xc0
356
357#define AR5K_SREV_PHY_5211 0x30
358#define AR5K_SREV_PHY_5212 0x41
359#define AR5K_SREV_PHY_5212A 0x42
360#define AR5K_SREV_PHY_5212B 0x43
361#define AR5K_SREV_PHY_2413 0x45
362#define AR5K_SREV_PHY_5413 0x61
363#define AR5K_SREV_PHY_2425 0x70
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447enum ath5k_driver_mode {
448 AR5K_MODE_11A = 0,
449 AR5K_MODE_11B = 1,
450 AR5K_MODE_11G = 2,
451 AR5K_MODE_MAX = 3
452};
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467enum ath5k_ant_mode {
468 AR5K_ANTMODE_DEFAULT = 0,
469 AR5K_ANTMODE_FIXED_A = 1,
470 AR5K_ANTMODE_FIXED_B = 2,
471 AR5K_ANTMODE_SINGLE_AP = 3,
472 AR5K_ANTMODE_SECTOR_AP = 4,
473 AR5K_ANTMODE_SECTOR_STA = 5,
474 AR5K_ANTMODE_DEBUG = 6,
475 AR5K_ANTMODE_MAX,
476};
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485enum ath5k_bw_mode {
486 AR5K_BWMODE_DEFAULT = 0,
487 AR5K_BWMODE_5MHZ = 1,
488 AR5K_BWMODE_10MHZ = 2,
489 AR5K_BWMODE_40MHZ = 3
490};
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513struct ath5k_tx_status {
514 u16 ts_seqnum;
515 u16 ts_tstamp;
516 u8 ts_status;
517 u8 ts_final_idx;
518 u8 ts_final_retry;
519 s8 ts_rssi;
520 u8 ts_shortretry;
521 u8 ts_virtcol;
522 u8 ts_antenna;
523};
524
525#define AR5K_TXSTAT_ALTRATE 0x80
526#define AR5K_TXERR_XRETRY 0x01
527#define AR5K_TXERR_FILT 0x02
528#define AR5K_TXERR_FIFO 0x04
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538enum ath5k_tx_queue {
539 AR5K_TX_QUEUE_INACTIVE = 0,
540 AR5K_TX_QUEUE_DATA,
541 AR5K_TX_QUEUE_BEACON,
542 AR5K_TX_QUEUE_CAB,
543 AR5K_TX_QUEUE_UAPSD,
544};
545
546#define AR5K_NUM_TX_QUEUES 10
547#define AR5K_NUM_TX_QUEUES_NOQCU 2
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561enum ath5k_tx_queue_subtype {
562 AR5K_WME_AC_BK = 0,
563 AR5K_WME_AC_BE,
564 AR5K_WME_AC_VI,
565 AR5K_WME_AC_VO,
566};
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581enum ath5k_tx_queue_id {
582 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0,
583 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1,
584 AR5K_TX_QUEUE_ID_DATA_MIN = 0,
585 AR5K_TX_QUEUE_ID_DATA_MAX = 3,
586 AR5K_TX_QUEUE_ID_UAPSD = 7,
587 AR5K_TX_QUEUE_ID_CAB = 8,
588 AR5K_TX_QUEUE_ID_BEACON = 9,
589};
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594#define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001
595#define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002
596#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004
597#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008
598#define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010
599#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020
600#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040
601#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080
602#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100
603#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200
604#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300
605#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800
606#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000
607#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000
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628struct ath5k_txq {
629 unsigned int qnum;
630 u32 *link;
631 struct list_head q;
632 spinlock_t lock;
633 bool setup;
634 int txq_len;
635 int txq_max;
636 bool txq_poll_mark;
637 unsigned int txq_stuck;
638};
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651struct ath5k_txq_info {
652 enum ath5k_tx_queue tqi_type;
653 enum ath5k_tx_queue_subtype tqi_subtype;
654 u16 tqi_flags;
655 u8 tqi_aifs;
656 u16 tqi_cw_min;
657 u16 tqi_cw_max;
658 u32 tqi_cbr_period;
659 u32 tqi_cbr_overflow_limit;
660 u32 tqi_burst_time;
661 u32 tqi_ready_time;
662};
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674enum ath5k_pkt_type {
675 AR5K_PKT_TYPE_NORMAL = 0,
676 AR5K_PKT_TYPE_ATIM = 1,
677 AR5K_PKT_TYPE_PSPOLL = 2,
678 AR5K_PKT_TYPE_BEACON = 3,
679 AR5K_PKT_TYPE_PROBE_RESP = 4,
680 AR5K_PKT_TYPE_PIFS = 5,
681};
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686#define AR5K_TXPOWER_OFDM(_r, _v) ( \
687 ((0 & 1) << ((_v) + 6)) | \
688 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
689)
690
691#define AR5K_TXPOWER_CCK(_r, _v) ( \
692 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \
693)
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713struct ath5k_rx_status {
714 u16 rs_datalen;
715 u16 rs_tstamp;
716 u8 rs_status;
717 u8 rs_phyerr;
718 s8 rs_rssi;
719 u8 rs_keyix;
720 u8 rs_rate;
721 u8 rs_antenna;
722 u8 rs_more;
723};
724
725#define AR5K_RXERR_CRC 0x01
726#define AR5K_RXERR_PHY 0x02
727#define AR5K_RXERR_FIFO 0x04
728#define AR5K_RXERR_DECRYPT 0x08
729#define AR5K_RXERR_MIC 0x10
730#define AR5K_RXKEYIX_INVALID ((u8) -1)
731#define AR5K_TXKEYIX_INVALID ((u32) -1)
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738#define AR5K_BEACON_PERIOD 0x0000ffff
739#define AR5K_BEACON_ENA 0x00800000
740#define AR5K_BEACON_RESET_TSF 0x01000000
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750#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
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765enum ath5k_rfgain {
766 AR5K_RFGAIN_INACTIVE = 0,
767 AR5K_RFGAIN_ACTIVE,
768 AR5K_RFGAIN_READ_REQUESTED,
769 AR5K_RFGAIN_NEED_CHANGE,
770};
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782struct ath5k_gain {
783 u8 g_step_idx;
784 u8 g_current;
785 u8 g_target;
786 u8 g_low;
787 u8 g_high;
788 u8 g_f_corr;
789 u8 g_state;
790};
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798#define AR5K_SLOT_TIME_9 396
799#define AR5K_SLOT_TIME_20 880
800#define AR5K_SLOT_TIME_MAX 0xffff
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812struct ath5k_athchan_2ghz {
813 u32 a2_flags;
814 u16 a2_athchan;
815};
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833enum ath5k_dmasize {
834 AR5K_DMASIZE_4B = 0,
835 AR5K_DMASIZE_8B,
836 AR5K_DMASIZE_16B,
837 AR5K_DMASIZE_32B,
838 AR5K_DMASIZE_64B,
839 AR5K_DMASIZE_128B,
840 AR5K_DMASIZE_256B,
841 AR5K_DMASIZE_512B
842};
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891
892
893
894#define AR5K_MAX_RATES 32
895
896
897#define ATH5K_RATE_CODE_1M 0x1B
898#define ATH5K_RATE_CODE_2M 0x1A
899#define ATH5K_RATE_CODE_5_5M 0x19
900#define ATH5K_RATE_CODE_11M 0x18
901
902#define ATH5K_RATE_CODE_6M 0x0B
903#define ATH5K_RATE_CODE_9M 0x0F
904#define ATH5K_RATE_CODE_12M 0x0A
905#define ATH5K_RATE_CODE_18M 0x0E
906#define ATH5K_RATE_CODE_24M 0x09
907#define ATH5K_RATE_CODE_36M 0x0D
908#define ATH5K_RATE_CODE_48M 0x08
909#define ATH5K_RATE_CODE_54M 0x0C
910
911
912
913#define AR5K_SET_SHORT_PREAMBLE 0x04
914
915
916
917
918
919#define AR5K_KEYCACHE_SIZE 8
920extern bool ath5k_modparam_nohwcrypt;
921
922
923
924
925
926
927
928
929#define AR5K_RSSI_EP_MULTIPLIER (1 << 7)
930
931#define AR5K_ASSERT_ENTRY(_e, _s) do { \
932 if (_e >= _s) \
933 return false; \
934} while (0)
935
936
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1003
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1007
1008enum ath5k_int {
1009 AR5K_INT_RXOK = 0x00000001,
1010 AR5K_INT_RXDESC = 0x00000002,
1011 AR5K_INT_RXERR = 0x00000004,
1012 AR5K_INT_RXNOFRM = 0x00000008,
1013 AR5K_INT_RXEOL = 0x00000010,
1014 AR5K_INT_RXORN = 0x00000020,
1015 AR5K_INT_TXOK = 0x00000040,
1016 AR5K_INT_TXDESC = 0x00000080,
1017 AR5K_INT_TXERR = 0x00000100,
1018 AR5K_INT_TXNOFRM = 0x00000200,
1019 AR5K_INT_TXEOL = 0x00000400,
1020 AR5K_INT_TXURN = 0x00000800,
1021 AR5K_INT_MIB = 0x00001000,
1022 AR5K_INT_SWI = 0x00002000,
1023 AR5K_INT_RXPHY = 0x00004000,
1024 AR5K_INT_RXKCM = 0x00008000,
1025 AR5K_INT_SWBA = 0x00010000,
1026 AR5K_INT_BRSSI = 0x00020000,
1027 AR5K_INT_BMISS = 0x00040000,
1028 AR5K_INT_FATAL = 0x00080000,
1029 AR5K_INT_BNR = 0x00100000,
1030 AR5K_INT_TIM = 0x00200000,
1031 AR5K_INT_DTIM = 0x00400000,
1032 AR5K_INT_DTIM_SYNC = 0x00800000,
1033 AR5K_INT_GPIO = 0x01000000,
1034 AR5K_INT_BCN_TIMEOUT = 0x02000000,
1035 AR5K_INT_CAB_TIMEOUT = 0x04000000,
1036 AR5K_INT_QCBRORN = 0x08000000,
1037 AR5K_INT_QCBRURN = 0x10000000,
1038 AR5K_INT_QTRIG = 0x20000000,
1039 AR5K_INT_GLOBAL = 0x80000000,
1040
1041 AR5K_INT_TX_ALL = AR5K_INT_TXOK
1042 | AR5K_INT_TXDESC
1043 | AR5K_INT_TXERR
1044 | AR5K_INT_TXNOFRM
1045 | AR5K_INT_TXEOL
1046 | AR5K_INT_TXURN,
1047
1048 AR5K_INT_RX_ALL = AR5K_INT_RXOK
1049 | AR5K_INT_RXDESC
1050 | AR5K_INT_RXERR
1051 | AR5K_INT_RXNOFRM
1052 | AR5K_INT_RXEOL
1053 | AR5K_INT_RXORN,
1054
1055 AR5K_INT_COMMON = AR5K_INT_RXOK
1056 | AR5K_INT_RXDESC
1057 | AR5K_INT_RXERR
1058 | AR5K_INT_RXNOFRM
1059 | AR5K_INT_RXEOL
1060 | AR5K_INT_RXORN
1061 | AR5K_INT_TXOK
1062 | AR5K_INT_TXDESC
1063 | AR5K_INT_TXERR
1064 | AR5K_INT_TXNOFRM
1065 | AR5K_INT_TXEOL
1066 | AR5K_INT_TXURN
1067 | AR5K_INT_MIB
1068 | AR5K_INT_SWI
1069 | AR5K_INT_RXPHY
1070 | AR5K_INT_RXKCM
1071 | AR5K_INT_SWBA
1072 | AR5K_INT_BRSSI
1073 | AR5K_INT_BMISS
1074 | AR5K_INT_GPIO
1075 | AR5K_INT_GLOBAL,
1076
1077 AR5K_INT_NOCARD = 0xffffffff
1078};
1079
1080
1081
1082
1083
1084
1085
1086
1087enum ath5k_calibration_mask {
1088 AR5K_CALIBRATION_FULL = 0x01,
1089 AR5K_CALIBRATION_SHORT = 0x02,
1090 AR5K_CALIBRATION_NF = 0x04,
1091 AR5K_CALIBRATION_ANI = 0x08,
1092};
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107enum ath5k_power_mode {
1108 AR5K_PM_UNDEFINED = 0,
1109 AR5K_PM_AUTO,
1110 AR5K_PM_AWAKE,
1111 AR5K_PM_FULL_SLEEP,
1112 AR5K_PM_NETWORK_SLEEP,
1113};
1114
1115
1116
1117
1118
1119
1120#define AR5K_LED_INIT 0
1121#define AR5K_LED_SCAN 1
1122#define AR5K_LED_AUTH 2
1123#define AR5K_LED_ASSOC 3
1124#define AR5K_LED_RUN 4
1125
1126
1127#define AR5K_SOFTLED_PIN 0
1128#define AR5K_SOFTLED_ON 0
1129#define AR5K_SOFTLED_OFF 1
1130
1131
1132
1133struct ath5k_capabilities {
1134
1135
1136
1137
1138 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX);
1139
1140
1141
1142
1143 struct {
1144 u16 range_2ghz_min;
1145 u16 range_2ghz_max;
1146 u16 range_5ghz_min;
1147 u16 range_5ghz_max;
1148 } cap_range;
1149
1150
1151
1152
1153 struct ath5k_eeprom_info cap_eeprom;
1154
1155
1156
1157
1158 struct {
1159 u8 q_tx_num;
1160 } cap_queues;
1161
1162 bool cap_has_phyerr_counters;
1163 bool cap_has_mrr_support;
1164 bool cap_needs_2GHz_ovr;
1165};
1166
1167
1168#define ATH5K_NF_CAL_HIST_MAX 8
1169struct ath5k_nfcal_hist {
1170 s16 index;
1171 s16 nfval[ATH5K_NF_CAL_HIST_MAX];
1172};
1173
1174#define ATH5K_LED_MAX_NAME_LEN 31
1175
1176
1177
1178
1179struct ath5k_led {
1180 char name[ATH5K_LED_MAX_NAME_LEN + 1];
1181 struct ath5k_hw *ah;
1182 struct led_classdev led_dev;
1183};
1184
1185
1186struct ath5k_rfkill {
1187
1188 u16 gpio;
1189
1190 bool polarity;
1191
1192 struct tasklet_struct toggleq;
1193};
1194
1195
1196struct ath5k_statistics {
1197
1198 unsigned int antenna_rx[5];
1199 unsigned int antenna_tx[5];
1200
1201
1202 unsigned int rx_all_count;
1203 unsigned int tx_all_count;
1204 unsigned int rx_bytes_count;
1205
1206
1207 unsigned int tx_bytes_count;
1208
1209
1210
1211 unsigned int rxerr_crc;
1212 unsigned int rxerr_phy;
1213 unsigned int rxerr_phy_code[32];
1214 unsigned int rxerr_fifo;
1215 unsigned int rxerr_decrypt;
1216 unsigned int rxerr_mic;
1217 unsigned int rxerr_proc;
1218 unsigned int rxerr_jumbo;
1219 unsigned int txerr_retry;
1220 unsigned int txerr_fifo;
1221 unsigned int txerr_filt;
1222
1223
1224 unsigned int ack_fail;
1225 unsigned int rts_fail;
1226 unsigned int rts_ok;
1227 unsigned int fcs_error;
1228 unsigned int beacons;
1229
1230 unsigned int mib_intr;
1231 unsigned int rxorn_intr;
1232 unsigned int rxeol_intr;
1233};
1234
1235
1236
1237
1238
1239#define AR5K_MAX_GPIO 10
1240#define AR5K_MAX_RF_BANKS 8
1241
1242#if CHAN_DEBUG
1243#define ATH_CHAN_MAX (26 + 26 + 26 + 200 + 200)
1244#else
1245#define ATH_CHAN_MAX (14 + 14 + 14 + 252 + 20)
1246#endif
1247
1248#define ATH_RXBUF 40
1249#define ATH_TXBUF 200
1250#define ATH_BCBUF 4
1251#define ATH5K_TXQ_LEN_MAX (ATH_TXBUF / 4)
1252#define ATH5K_TXQ_LEN_LOW (ATH5K_TXQ_LEN_MAX / 2)
1253
1254
1255struct ath5k_hw {
1256 struct ath_common common;
1257
1258 struct pci_dev *pdev;
1259 struct device *dev;
1260 int irq;
1261 u16 devid;
1262 void __iomem *iobase;
1263 struct mutex lock;
1264 struct ieee80211_hw *hw;
1265 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
1266 struct ieee80211_channel channels[ATH_CHAN_MAX];
1267 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
1268 s8 rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
1269 enum nl80211_iftype opmode;
1270
1271#ifdef CONFIG_ATH5K_DEBUG
1272 struct ath5k_dbg_info debug;
1273#endif
1274
1275 struct ath5k_buf *bufptr;
1276 struct ath5k_desc *desc;
1277 dma_addr_t desc_daddr;
1278 size_t desc_len;
1279
1280 DECLARE_BITMAP(status, 4);
1281#define ATH_STAT_INVALID 0
1282#define ATH_STAT_PROMISC 1
1283#define ATH_STAT_LEDSOFT 2
1284#define ATH_STAT_STARTED 3
1285
1286 unsigned int filter_flags;
1287 struct ieee80211_channel *curchan;
1288
1289 u16 nvifs;
1290
1291 enum ath5k_int imask;
1292
1293 spinlock_t irqlock;
1294 bool rx_pending;
1295 bool tx_pending;
1296
1297 u8 bssidmask[ETH_ALEN];
1298
1299 unsigned int led_pin,
1300 led_on;
1301
1302 struct work_struct reset_work;
1303 struct work_struct calib_work;
1304
1305 struct list_head rxbuf;
1306 spinlock_t rxbuflock;
1307 u32 *rxlink;
1308 struct tasklet_struct rxtq;
1309 struct ath5k_led rx_led;
1310
1311 struct list_head txbuf;
1312 spinlock_t txbuflock;
1313 unsigned int txbuf_len;
1314 struct ath5k_txq txqs[AR5K_NUM_TX_QUEUES];
1315 struct tasklet_struct txtq;
1316 struct ath5k_led tx_led;
1317
1318 struct ath5k_rfkill rf_kill;
1319
1320 spinlock_t block;
1321 struct tasklet_struct beacontq;
1322 struct list_head bcbuf;
1323 struct ieee80211_vif *bslot[ATH_BCBUF];
1324 u16 num_ap_vifs;
1325 u16 num_adhoc_vifs;
1326 u16 num_mesh_vifs;
1327 unsigned int bhalq,
1328 bmisscount,
1329 bintval,
1330 bsent;
1331 unsigned int nexttbtt;
1332 struct ath5k_txq *cabq;
1333
1334 bool assoc;
1335 bool enable_beacon;
1336
1337 struct ath5k_statistics stats;
1338
1339 struct ath5k_ani_state ani_state;
1340 struct tasklet_struct ani_tasklet;
1341
1342 struct delayed_work tx_complete_work;
1343
1344 struct survey_info survey;
1345
1346 enum ath5k_int ah_imr;
1347
1348 struct ieee80211_channel *ah_current_channel;
1349 bool ah_iq_cal_needed;
1350 bool ah_single_chip;
1351
1352 enum ath5k_version ah_version;
1353 enum ath5k_radio ah_radio;
1354 u32 ah_mac_srev;
1355 u16 ah_mac_version;
1356 u16 ah_phy_revision;
1357 u16 ah_radio_5ghz_revision;
1358 u16 ah_radio_2ghz_revision;
1359
1360#define ah_modes ah_capabilities.cap_mode
1361#define ah_ee_version ah_capabilities.cap_eeprom.ee_version
1362
1363 u8 ah_retry_long;
1364 u8 ah_retry_short;
1365
1366 u32 ah_use_32khz_clock;
1367
1368 u8 ah_coverage_class;
1369 bool ah_ack_bitrate_high;
1370 u8 ah_bwmode;
1371 bool ah_short_slot;
1372
1373
1374 u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
1375 u8 ah_ant_mode;
1376 u8 ah_tx_ant;
1377 u8 ah_def_ant;
1378
1379 struct ath5k_capabilities ah_capabilities;
1380
1381 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES];
1382 u32 ah_txq_status;
1383 u32 ah_txq_imr_txok;
1384 u32 ah_txq_imr_txerr;
1385 u32 ah_txq_imr_txurn;
1386 u32 ah_txq_imr_txdesc;
1387 u32 ah_txq_imr_txeol;
1388 u32 ah_txq_imr_cbrorn;
1389 u32 ah_txq_imr_cbrurn;
1390 u32 ah_txq_imr_qtrig;
1391 u32 ah_txq_imr_nofrm;
1392
1393 u32 ah_txq_isr_txok_all;
1394 u32 ah_txq_isr_txurn;
1395 u32 ah_txq_isr_qcborn;
1396 u32 ah_txq_isr_qcburn;
1397 u32 ah_txq_isr_qtrig;
1398
1399 u32 *ah_rf_banks;
1400 size_t ah_rf_banks_size;
1401 size_t ah_rf_regs_count;
1402 struct ath5k_gain ah_gain;
1403 u8 ah_offset[AR5K_MAX_RF_BANKS];
1404
1405
1406 struct {
1407
1408 u8 tmpL[AR5K_EEPROM_N_PD_GAINS]
1409 [AR5K_EEPROM_POWER_TABLE_SIZE];
1410 u8 tmpR[AR5K_EEPROM_N_PD_GAINS]
1411 [AR5K_EEPROM_POWER_TABLE_SIZE];
1412 u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2];
1413 u16 txp_rates_power_table[AR5K_MAX_RATES];
1414 u8 txp_min_idx;
1415 bool txp_tpc;
1416
1417 s16 txp_min_pwr;
1418 s16 txp_max_pwr;
1419 s16 txp_cur_pwr;
1420
1421 s16 txp_offset;
1422 s16 txp_ofdm;
1423 s16 txp_cck_ofdm_gainf_delta;
1424
1425 s16 txp_cck_ofdm_pwr_delta;
1426 bool txp_setup;
1427 int txp_requested;
1428 } ah_txpower;
1429
1430 struct ath5k_nfcal_hist ah_nfcal_hist;
1431
1432
1433 struct ewma ah_beacon_rssi_avg;
1434
1435
1436 s32 ah_noise_floor;
1437
1438
1439 unsigned long ah_cal_next_full;
1440 unsigned long ah_cal_next_short;
1441 unsigned long ah_cal_next_ani;
1442
1443
1444 u8 ah_cal_mask;
1445
1446
1447
1448
1449 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1450 unsigned int, unsigned int, int, enum ath5k_pkt_type,
1451 unsigned int, unsigned int, unsigned int, unsigned int,
1452 unsigned int, unsigned int, unsigned int, unsigned int);
1453 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1454 struct ath5k_tx_status *);
1455 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1456 struct ath5k_rx_status *);
1457};
1458
1459struct ath_bus_ops {
1460 enum ath_bus_type ath_bus_type;
1461 void (*read_cachesize)(struct ath_common *common, int *csz);
1462 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
1463 int (*eeprom_read_mac)(struct ath5k_hw *ah, u8 *mac);
1464};
1465
1466
1467
1468
1469extern const struct ieee80211_ops ath5k_hw_ops;
1470
1471
1472int ath5k_hw_init(struct ath5k_hw *ah);
1473void ath5k_hw_deinit(struct ath5k_hw *ah);
1474
1475int ath5k_sysfs_register(struct ath5k_hw *ah);
1476void ath5k_sysfs_unregister(struct ath5k_hw *ah);
1477
1478
1479int ath5k_hw_read_srev(struct ath5k_hw *ah);
1480
1481
1482int ath5k_init_leds(struct ath5k_hw *ah);
1483void ath5k_led_enable(struct ath5k_hw *ah);
1484void ath5k_led_off(struct ath5k_hw *ah);
1485void ath5k_unregister_leds(struct ath5k_hw *ah);
1486
1487
1488
1489int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1490int ath5k_hw_on_hold(struct ath5k_hw *ah);
1491int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1492 struct ieee80211_channel *channel, bool fast, bool skip_pcu);
1493int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
1494 bool is_set);
1495
1496
1497
1498
1499unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec);
1500unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock);
1501void ath5k_hw_set_clockrate(struct ath5k_hw *ah);
1502
1503
1504
1505void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
1506u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
1507int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
1508int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1509int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue);
1510u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
1511int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
1512 u32 phys_addr);
1513int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
1514
1515bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1516int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
1517enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask);
1518void ath5k_hw_update_mib_counters(struct ath5k_hw *ah);
1519
1520void ath5k_hw_dma_init(struct ath5k_hw *ah);
1521int ath5k_hw_dma_stop(struct ath5k_hw *ah);
1522
1523
1524int ath5k_eeprom_init(struct ath5k_hw *ah);
1525void ath5k_eeprom_detach(struct ath5k_hw *ah);
1526int ath5k_eeprom_mode_from_channel(struct ath5k_hw *ah,
1527 struct ieee80211_channel *channel);
1528
1529
1530
1531int ath5k_hw_get_frame_duration(struct ath5k_hw *ah, enum ieee80211_band band,
1532 int len, struct ieee80211_rate *rate, bool shortpre);
1533unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah);
1534unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah);
1535int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode);
1536void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class);
1537
1538int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
1539void ath5k_hw_set_bssid(struct ath5k_hw *ah);
1540void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
1541void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
1542u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1543void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
1544
1545void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
1546void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
1547
1548u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
1549void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
1550void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1551void ath5k_hw_init_beacon_timers(struct ath5k_hw *ah, u32 next_beacon,
1552 u32 interval);
1553bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval);
1554
1555void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode);
1556
1557
1558int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
1559 struct ath5k_txq_info *queue_info);
1560int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
1561 const struct ath5k_txq_info *queue_info);
1562int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
1563 enum ath5k_tx_queue queue_type,
1564 struct ath5k_txq_info *queue_info);
1565void ath5k_hw_set_tx_retry_limits(struct ath5k_hw *ah,
1566 unsigned int queue);
1567u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
1568void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1569int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1570int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time);
1571
1572int ath5k_hw_init_queues(struct ath5k_hw *ah);
1573
1574
1575int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
1576int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
1577 u32 size, unsigned int flags);
1578int ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
1579 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2,
1580 u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3);
1581
1582
1583
1584void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
1585int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
1586int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
1587u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
1588int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
1589void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
1590 u32 interrupt_level);
1591
1592
1593
1594void ath5k_rfkill_hw_start(struct ath5k_hw *ah);
1595void ath5k_rfkill_hw_stop(struct ath5k_hw *ah);
1596
1597
1598
1599int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
1600int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
1601int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
1602
1603
1604
1605int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
1606
1607
1608
1609
1610u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum ieee80211_band band);
1611int ath5k_hw_phy_disable(struct ath5k_hw *ah);
1612
1613enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
1614int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
1615
1616bool ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1617
1618void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah);
1619int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1620 struct ieee80211_channel *channel);
1621void ath5k_hw_update_noise_floor(struct ath5k_hw *ah);
1622
1623bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
1624 struct ieee80211_channel *channel);
1625
1626void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode);
1627void ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode);
1628
1629int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower);
1630
1631int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
1632 u8 mode, bool fast);
1633
1634
1635
1636
1637
1638static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah)
1639{
1640 return &ah->common;
1641}
1642
1643static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah)
1644{
1645 return &(ath5k_hw_common(ah)->regulatory);
1646}
1647
1648#ifdef CONFIG_ATHEROS_AR231X
1649#define AR5K_AR2315_PCI_BASE ((void __iomem *)0xb0100000)
1650
1651static inline void __iomem *ath5k_ahb_reg(struct ath5k_hw *ah, u16 reg)
1652{
1653
1654
1655 if (unlikely((reg >= 0x4000) && (reg < 0x5000) &&
1656 (ah->ah_mac_srev >= AR5K_SREV_AR2315_R6)))
1657 return AR5K_AR2315_PCI_BASE + reg;
1658
1659 return ah->iobase + reg;
1660}
1661
1662static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1663{
1664 return ioread32(ath5k_ahb_reg(ah, reg));
1665}
1666
1667static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1668{
1669 iowrite32(val, ath5k_ahb_reg(ah, reg));
1670}
1671
1672#else
1673
1674static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1675{
1676 return ioread32(ah->iobase + reg);
1677}
1678
1679static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1680{
1681 iowrite32(val, ah->iobase + reg);
1682}
1683
1684#endif
1685
1686static inline enum ath_bus_type ath5k_get_bus_type(struct ath5k_hw *ah)
1687{
1688 return ath5k_hw_common(ah)->bus_ops->ath_bus_type;
1689}
1690
1691static inline void ath5k_read_cachesize(struct ath_common *common, int *csz)
1692{
1693 common->bus_ops->read_cachesize(common, csz);
1694}
1695
1696static inline bool ath5k_hw_nvram_read(struct ath5k_hw *ah, u32 off, u16 *data)
1697{
1698 struct ath_common *common = ath5k_hw_common(ah);
1699 return common->bus_ops->eeprom_read(common, off, data);
1700}
1701
1702static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
1703{
1704 u32 retval = 0, bit, i;
1705
1706 for (i = 0; i < bits; i++) {
1707 bit = (val >> i) & 1;
1708 retval = (retval << 1) | bit;
1709 }
1710
1711 return retval;
1712}
1713
1714#endif
1715