linux/drivers/net/wireless/ath/ath5k/ath5k.h
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   1/*
   2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
   3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
   4 *
   5 * Permission to use, copy, modify, and distribute this software for any
   6 * purpose with or without fee is hereby granted, provided that the above
   7 * copyright notice and this permission notice appear in all copies.
   8 *
   9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16 */
  17
  18#ifndef _ATH5K_H
  19#define _ATH5K_H
  20
  21/* TODO: Clean up channel debugging (doesn't work anyway) and start
  22 * working on reg. control code using all available eeprom information
  23 * (rev. engineering needed) */
  24#define CHAN_DEBUG      0
  25
  26#include <linux/io.h>
  27#include <linux/interrupt.h>
  28#include <linux/types.h>
  29#include <linux/average.h>
  30#include <linux/leds.h>
  31#include <net/mac80211.h>
  32
  33/* RX/TX descriptor hw structs
  34 * TODO: Driver part should only see sw structs */
  35#include "desc.h"
  36
  37/* EEPROM structs/offsets
  38 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities)
  39 * and clean up common bits, then introduce set/get functions in eeprom.c */
  40#include "eeprom.h"
  41#include "debug.h"
  42#include "../ath.h"
  43#include "ani.h"
  44
  45/* PCI IDs */
  46#define PCI_DEVICE_ID_ATHEROS_AR5210            0x0007 /* AR5210 */
  47#define PCI_DEVICE_ID_ATHEROS_AR5311            0x0011 /* AR5311 */
  48#define PCI_DEVICE_ID_ATHEROS_AR5211            0x0012 /* AR5211 */
  49#define PCI_DEVICE_ID_ATHEROS_AR5212            0x0013 /* AR5212 */
  50#define PCI_DEVICE_ID_3COM_3CRDAG675            0x0013 /* 3CRDAG675 (Atheros AR5212) */
  51#define PCI_DEVICE_ID_3COM_2_3CRPAG175          0x0013 /* 3CRPAG175 (Atheros AR5212) */
  52#define PCI_DEVICE_ID_ATHEROS_AR5210_AP         0x0207 /* AR5210 (Early) */
  53#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM        0x1014 /* AR5212 (IBM MiniPCI) */
  54#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT    0x1107 /* AR5210 (no eeprom) */
  55#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT    0x1113 /* AR5212 (no eeprom) */
  56#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT    0x1112 /* AR5211 (no eeprom) */
  57#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA       0xf013 /* AR5212 (emulation board) */
  58#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY     0xff12 /* AR5211 (emulation board) */
  59#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B    0xf11b /* AR5211 (emulation board) */
  60#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2       0x0052 /* AR5312 WMAC (AP31) */
  61#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7       0x0057 /* AR5312 WMAC (AP30-040) */
  62#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8       0x0058 /* AR5312 WMAC (AP43-030) */
  63#define PCI_DEVICE_ID_ATHEROS_AR5212_0014       0x0014 /* AR5212 compatible */
  64#define PCI_DEVICE_ID_ATHEROS_AR5212_0015       0x0015 /* AR5212 compatible */
  65#define PCI_DEVICE_ID_ATHEROS_AR5212_0016       0x0016 /* AR5212 compatible */
  66#define PCI_DEVICE_ID_ATHEROS_AR5212_0017       0x0017 /* AR5212 compatible */
  67#define PCI_DEVICE_ID_ATHEROS_AR5212_0018       0x0018 /* AR5212 compatible */
  68#define PCI_DEVICE_ID_ATHEROS_AR5212_0019       0x0019 /* AR5212 compatible */
  69#define PCI_DEVICE_ID_ATHEROS_AR2413            0x001a /* AR2413 (Griffin-lite) */
  70#define PCI_DEVICE_ID_ATHEROS_AR5413            0x001b /* AR5413 (Eagle) */
  71#define PCI_DEVICE_ID_ATHEROS_AR5424            0x001c /* AR5424 (Condor PCI-E) */
  72#define PCI_DEVICE_ID_ATHEROS_AR5416            0x0023 /* AR5416 */
  73#define PCI_DEVICE_ID_ATHEROS_AR5418            0x0024 /* AR5418 */
  74
  75/****************************\
  76  GENERIC DRIVER DEFINITIONS
  77\****************************/
  78
  79#define ATH5K_PRINTF(fmt, ...)                                          \
  80        pr_warn("%s: " fmt, __func__, ##__VA_ARGS__)
  81
  82void __printf(3, 4)
  83_ath5k_printk(const struct ath5k_hw *ah, const char *level,
  84              const char *fmt, ...);
  85
  86#define ATH5K_PRINTK(_sc, _level, _fmt, ...)                            \
  87        _ath5k_printk(_sc, _level, _fmt, ##__VA_ARGS__)
  88
  89#define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...)                      \
  90do {                                                                    \
  91        if (net_ratelimit())                                            \
  92                ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__);         \
  93} while (0)
  94
  95#define ATH5K_INFO(_sc, _fmt, ...)                                      \
  96        ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)
  97
  98#define ATH5K_WARN(_sc, _fmt, ...)                                      \
  99        ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)
 100
 101#define ATH5K_ERR(_sc, _fmt, ...)                                       \
 102        ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)
 103
 104/*
 105 * AR5K REGISTER ACCESS
 106 */
 107
 108/* Some macros to read/write fields */
 109
 110/* First shift, then mask */
 111#define AR5K_REG_SM(_val, _flags)                                       \
 112        (((_val) << _flags##_S) & (_flags))
 113
 114/* First mask, then shift */
 115#define AR5K_REG_MS(_val, _flags)                                       \
 116        (((_val) & (_flags)) >> _flags##_S)
 117
 118/* Some registers can hold multiple values of interest. For this
 119 * reason when we want to write to these registers we must first
 120 * retrieve the values which we do not want to clear (lets call this
 121 * old_data) and then set the register with this and our new_value:
 122 * ( old_data | new_value) */
 123#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val)                     \
 124        ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
 125            (((_val) << _flags##_S) & (_flags)), _reg)
 126
 127#define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask)                   \
 128        ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) &           \
 129                        (_mask)) | (_flags), _reg)
 130
 131#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags)                          \
 132        ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
 133
 134#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags)                 \
 135        ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
 136
 137/* Access QCU registers per queue */
 138#define AR5K_REG_READ_Q(ah, _reg, _queue)                               \
 139        (ath5k_hw_reg_read(ah, _reg) & (1 << _queue))                   \
 140
 141#define AR5K_REG_WRITE_Q(ah, _reg, _queue)                              \
 142        ath5k_hw_reg_write(ah, (1 << _queue), _reg)
 143
 144#define AR5K_Q_ENABLE_BITS(_reg, _queue) do {                           \
 145        _reg |= 1 << _queue;                                            \
 146} while (0)
 147
 148#define AR5K_Q_DISABLE_BITS(_reg, _queue) do {                          \
 149        _reg &= ~(1 << _queue);                                         \
 150} while (0)
 151
 152/* Used while writing initvals */
 153#define AR5K_REG_WAIT(_i) do {                                          \
 154        if (_i % 64)                                                    \
 155                udelay(1);                                              \
 156} while (0)
 157
 158/*
 159 * Some tunable values (these should be changeable by the user)
 160 * TODO: Make use of them and add more options OR use debug/configfs
 161 */
 162#define AR5K_TUNE_DMA_BEACON_RESP               2
 163#define AR5K_TUNE_SW_BEACON_RESP                10
 164#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF       0
 165#define AR5K_TUNE_MIN_TX_FIFO_THRES             1
 166#define AR5K_TUNE_MAX_TX_FIFO_THRES     ((IEEE80211_MAX_FRAME_LEN / 64) + 1)
 167#define AR5K_TUNE_REGISTER_TIMEOUT              20000
 168/* Register for RSSI threshold has a mask of 0xff, so 255 seems to
 169 * be the max value. */
 170#define AR5K_TUNE_RSSI_THRES                    129
 171/* This must be set when setting the RSSI threshold otherwise it can
 172 * prevent a reset. If AR5K_RSSI_THR is read after writing to it
 173 * the BMISS_THRES will be seen as 0, seems hardware doesn't keep
 174 * track of it. Max value depends on hardware. For AR5210 this is just 7.
 175 * For AR5211+ this seems to be up to 255. */
 176#define AR5K_TUNE_BMISS_THRES                   7
 177#define AR5K_TUNE_REGISTER_DWELL_TIME           20000
 178#define AR5K_TUNE_BEACON_INTERVAL               100
 179#define AR5K_TUNE_AIFS                          2
 180#define AR5K_TUNE_AIFS_11B                      2
 181#define AR5K_TUNE_AIFS_XR                       0
 182#define AR5K_TUNE_CWMIN                         15
 183#define AR5K_TUNE_CWMIN_11B                     31
 184#define AR5K_TUNE_CWMIN_XR                      3
 185#define AR5K_TUNE_CWMAX                         1023
 186#define AR5K_TUNE_CWMAX_11B                     1023
 187#define AR5K_TUNE_CWMAX_XR                      7
 188#define AR5K_TUNE_NOISE_FLOOR                   -72
 189#define AR5K_TUNE_CCA_MAX_GOOD_VALUE            -95
 190#define AR5K_TUNE_MAX_TXPOWER                   63
 191#define AR5K_TUNE_DEFAULT_TXPOWER               25
 192#define AR5K_TUNE_TPC_TXPOWER                   false
 193#define ATH5K_TUNE_CALIBRATION_INTERVAL_FULL    60000   /* 60 sec */
 194#define ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT   10000   /* 10 sec */
 195#define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI     1000    /* 1 sec */
 196#define ATH5K_TX_COMPLETE_POLL_INT              3000    /* 3 sec */
 197
 198#define AR5K_INIT_CARR_SENSE_EN                 1
 199
 200/*Swap RX/TX Descriptor for big endian archs*/
 201#if defined(__BIG_ENDIAN)
 202#define AR5K_INIT_CFG   (               \
 203        AR5K_CFG_SWTD | AR5K_CFG_SWRD   \
 204)
 205#else
 206#define AR5K_INIT_CFG   0x00000000
 207#endif
 208
 209/* Initial values */
 210#define AR5K_INIT_CYCRSSI_THR1                  2
 211
 212/* Tx retry limit defaults from standard */
 213#define AR5K_INIT_RETRY_SHORT                   7
 214#define AR5K_INIT_RETRY_LONG                    4
 215
 216/* Slot time */
 217#define AR5K_INIT_SLOT_TIME_TURBO               6
 218#define AR5K_INIT_SLOT_TIME_DEFAULT             9
 219#define AR5K_INIT_SLOT_TIME_HALF_RATE           13
 220#define AR5K_INIT_SLOT_TIME_QUARTER_RATE        21
 221#define AR5K_INIT_SLOT_TIME_B                   20
 222#define AR5K_SLOT_TIME_MAX                      0xffff
 223
 224/* SIFS */
 225#define AR5K_INIT_SIFS_TURBO                    6
 226#define AR5K_INIT_SIFS_DEFAULT_BG               10
 227#define AR5K_INIT_SIFS_DEFAULT_A                16
 228#define AR5K_INIT_SIFS_HALF_RATE                32
 229#define AR5K_INIT_SIFS_QUARTER_RATE             64
 230
 231/* Used to calculate tx time for non 5/10/40MHz
 232 * operation */
 233/* It's preamble time + signal time (16 + 4) */
 234#define AR5K_INIT_OFDM_PREAMPLE_TIME            20
 235/* Preamble time for 40MHz (turbo) operation (min ?) */
 236#define AR5K_INIT_OFDM_PREAMBLE_TIME_MIN        14
 237#define AR5K_INIT_OFDM_SYMBOL_TIME              4
 238#define AR5K_INIT_OFDM_PLCP_BITS                22
 239
 240/* Rx latency for 5 and 10MHz operation (max ?) */
 241#define AR5K_INIT_RX_LAT_MAX                    63
 242/* Tx latencies from initvals (5212 only but no problem
 243 * because we only tweak them on 5212) */
 244#define AR5K_INIT_TX_LAT_A                      54
 245#define AR5K_INIT_TX_LAT_BG                     384
 246/* Tx latency for 40MHz (turbo) operation (min ?) */
 247#define AR5K_INIT_TX_LAT_MIN                    32
 248/* Default Tx/Rx latencies (same for 5211)*/
 249#define AR5K_INIT_TX_LATENCY_5210               54
 250#define AR5K_INIT_RX_LATENCY_5210               29
 251
 252/* Tx frame to Tx data start delay */
 253#define AR5K_INIT_TXF2TXD_START_DEFAULT         14
 254#define AR5K_INIT_TXF2TXD_START_DELAY_10MHZ     12
 255#define AR5K_INIT_TXF2TXD_START_DELAY_5MHZ      13
 256
 257/* We need to increase PHY switch and agc settling time
 258 * on turbo mode */
 259#define AR5K_SWITCH_SETTLING                    5760
 260#define AR5K_SWITCH_SETTLING_TURBO              7168
 261
 262#define AR5K_AGC_SETTLING                       28
 263/* 38 on 5210 but shouldn't matter */
 264#define AR5K_AGC_SETTLING_TURBO                 37
 265
 266
 267
 268/*****************************\
 269* GENERIC CHIPSET DEFINITIONS *
 270\*****************************/
 271
 272/**
 273 * enum ath5k_version - MAC Chips
 274 * @AR5K_AR5210: AR5210 (Crete)
 275 * @AR5K_AR5211: AR5211 (Oahu/Maui)
 276 * @AR5K_AR5212: AR5212 (Venice) and newer
 277 */
 278enum ath5k_version {
 279        AR5K_AR5210     = 0,
 280        AR5K_AR5211     = 1,
 281        AR5K_AR5212     = 2,
 282};
 283
 284/**
 285 * enum ath5k_radio - PHY Chips
 286 * @AR5K_RF5110: RF5110 (Fez)
 287 * @AR5K_RF5111: RF5111 (Sombrero)
 288 * @AR5K_RF5112: RF2112/5112(A) (Derby/Derby2)
 289 * @AR5K_RF2413: RF2413/2414 (Griffin/Griffin-Lite)
 290 * @AR5K_RF5413: RF5413/5414/5424 (Eagle/Condor)
 291 * @AR5K_RF2316: RF2315/2316 (Cobra SoC)
 292 * @AR5K_RF2317: RF2317 (Spider SoC)
 293 * @AR5K_RF2425: RF2425/2417 (Swan/Nalla)
 294 */
 295enum ath5k_radio {
 296        AR5K_RF5110     = 0,
 297        AR5K_RF5111     = 1,
 298        AR5K_RF5112     = 2,
 299        AR5K_RF2413     = 3,
 300        AR5K_RF5413     = 4,
 301        AR5K_RF2316     = 5,
 302        AR5K_RF2317     = 6,
 303        AR5K_RF2425     = 7,
 304};
 305
 306/*
 307 * Common silicon revision/version values
 308 */
 309
 310#define AR5K_SREV_UNKNOWN       0xffff
 311
 312#define AR5K_SREV_AR5210        0x00 /* Crete */
 313#define AR5K_SREV_AR5311        0x10 /* Maui 1 */
 314#define AR5K_SREV_AR5311A       0x20 /* Maui 2 */
 315#define AR5K_SREV_AR5311B       0x30 /* Spirit */
 316#define AR5K_SREV_AR5211        0x40 /* Oahu */
 317#define AR5K_SREV_AR5212        0x50 /* Venice */
 318#define AR5K_SREV_AR5312_R2     0x52 /* AP31 */
 319#define AR5K_SREV_AR5212_V4     0x54 /* ??? */
 320#define AR5K_SREV_AR5213        0x55 /* ??? */
 321#define AR5K_SREV_AR5312_R7     0x57 /* AP30 */
 322#define AR5K_SREV_AR2313_R8     0x58 /* AP43 */
 323#define AR5K_SREV_AR5213A       0x59 /* Hainan */
 324#define AR5K_SREV_AR2413        0x78 /* Griffin lite */
 325#define AR5K_SREV_AR2414        0x70 /* Griffin */
 326#define AR5K_SREV_AR2315_R6     0x86 /* AP51-Light */
 327#define AR5K_SREV_AR2315_R7     0x87 /* AP51-Full */
 328#define AR5K_SREV_AR5424        0x90 /* Condor */
 329#define AR5K_SREV_AR2317_R1     0x90 /* AP61-Light */
 330#define AR5K_SREV_AR2317_R2     0x91 /* AP61-Full */
 331#define AR5K_SREV_AR5413        0xa4 /* Eagle lite */
 332#define AR5K_SREV_AR5414        0xa0 /* Eagle */
 333#define AR5K_SREV_AR2415        0xb0 /* Talon */
 334#define AR5K_SREV_AR5416        0xc0 /* PCI-E */
 335#define AR5K_SREV_AR5418        0xca /* PCI-E */
 336#define AR5K_SREV_AR2425        0xe0 /* Swan */
 337#define AR5K_SREV_AR2417        0xf0 /* Nala */
 338
 339#define AR5K_SREV_RAD_5110      0x00
 340#define AR5K_SREV_RAD_5111      0x10
 341#define AR5K_SREV_RAD_5111A     0x15
 342#define AR5K_SREV_RAD_2111      0x20
 343#define AR5K_SREV_RAD_5112      0x30
 344#define AR5K_SREV_RAD_5112A     0x35
 345#define AR5K_SREV_RAD_5112B     0x36
 346#define AR5K_SREV_RAD_2112      0x40
 347#define AR5K_SREV_RAD_2112A     0x45
 348#define AR5K_SREV_RAD_2112B     0x46
 349#define AR5K_SREV_RAD_2413      0x50
 350#define AR5K_SREV_RAD_5413      0x60
 351#define AR5K_SREV_RAD_2316      0x70 /* Cobra SoC */
 352#define AR5K_SREV_RAD_2317      0x80
 353#define AR5K_SREV_RAD_5424      0xa0 /* Mostly same as 5413 */
 354#define AR5K_SREV_RAD_2425      0xa2
 355#define AR5K_SREV_RAD_5133      0xc0
 356
 357#define AR5K_SREV_PHY_5211      0x30
 358#define AR5K_SREV_PHY_5212      0x41
 359#define AR5K_SREV_PHY_5212A     0x42
 360#define AR5K_SREV_PHY_5212B     0x43
 361#define AR5K_SREV_PHY_2413      0x45
 362#define AR5K_SREV_PHY_5413      0x61
 363#define AR5K_SREV_PHY_2425      0x70
 364
 365/* TODO add support to mac80211 for vendor-specific rates and modes */
 366
 367/**
 368 * DOC: Atheros XR
 369 *
 370 * Some of this information is based on Documentation from:
 371 *
 372 * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG
 373 *
 374 * Atheros' eXtended Range - range enhancing extension is a modulation scheme
 375 * that is supposed to double the link distance between an Atheros XR-enabled
 376 * client device with an Atheros XR-enabled access point. This is achieved
 377 * by increasing the receiver sensitivity up to, -105dBm, which is about 20dB
 378 * above what the 802.11 specifications demand. In addition, new (proprietary)
 379 * data rates are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
 380 *
 381 * Please note that can you either use XR or TURBO but you cannot use both,
 382 * they are exclusive.
 383 *
 384 * Also note that we do not plan to support XR mode at least for now. You can
 385 * get a mode similar to XR by using 5MHz bwmode.
 386 */
 387
 388
 389/**
 390 * DOC: Atheros SuperAG
 391 *
 392 * In addition to XR we have another modulation scheme called TURBO mode
 393 * that is supposed to provide a throughput transmission speed up to 40Mbit/s
 394 * -60Mbit/s at a 108Mbit/s signaling rate achieved through the bonding of two
 395 * 54Mbit/s 802.11g channels. To use this feature both ends must support it.
 396 * There is also a distinction between "static" and "dynamic" turbo modes:
 397 *
 398 * - Static: is the dumb version: devices set to this mode stick to it until
 399 *     the mode is turned off.
 400 *
 401 * - Dynamic: is the intelligent version, the network decides itself if it
 402 *     is ok to use turbo. As soon as traffic is detected on adjacent channels
 403 *     (which would get used in turbo mode), or when a non-turbo station joins
 404 *     the network, turbo mode won't be used until the situation changes again.
 405 *     Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
 406 *     monitors the used radio band in order to decide whether turbo mode may
 407 *     be used or not.
 408 *
 409 * This article claims Super G sticks to bonding of channels 5 and 6 for
 410 * USA:
 411 *
 412 * http://www.pcworld.com/article/id,113428-page,1/article.html
 413 *
 414 * The channel bonding seems to be driver specific though.
 415 *
 416 * In addition to TURBO modes we also have the following features for even
 417 * greater speed-up:
 418 *
 419 * - Bursting: allows multiple frames to be sent at once, rather than pausing
 420 *     after each frame. Bursting is a standards-compliant feature that can be
 421 *     used with any Access Point.
 422 *
 423 * - Fast frames: increases the amount of information that can be sent per
 424 *     frame, also resulting in a reduction of transmission overhead. It is a
 425 *     proprietary feature that needs to be supported by the Access Point.
 426 *
 427 * - Compression: data frames are compressed in real time using a Lempel Ziv
 428 *     algorithm. This is done transparently. Once this feature is enabled,
 429 *     compression and decompression takes place inside the chipset, without
 430 *     putting additional load on the host CPU.
 431 *
 432 * As with XR we also don't plan to support SuperAG features for now. You can
 433 * get a mode similar to TURBO by using 40MHz bwmode.
 434 */
 435
 436
 437/**
 438 * enum ath5k_driver_mode - PHY operation mode
 439 * @AR5K_MODE_11A: 802.11a
 440 * @AR5K_MODE_11B: 802.11b
 441 * @AR5K_MODE_11G: 801.11g
 442 * @AR5K_MODE_MAX: Used for boundary checks
 443 *
 444 * Do not change the order here, we use these as
 445 * array indices and it also maps EEPROM structures.
 446 */
 447enum ath5k_driver_mode {
 448        AR5K_MODE_11A           =       0,
 449        AR5K_MODE_11B           =       1,
 450        AR5K_MODE_11G           =       2,
 451        AR5K_MODE_MAX           =       3
 452};
 453
 454/**
 455 * enum ath5k_ant_mode - Antenna operation mode
 456 * @AR5K_ANTMODE_DEFAULT: Default antenna setup
 457 * @AR5K_ANTMODE_FIXED_A: Only antenna A is present
 458 * @AR5K_ANTMODE_FIXED_B: Only antenna B is present
 459 * @AR5K_ANTMODE_SINGLE_AP: STA locked on a single ap
 460 * @AR5K_ANTMODE_SECTOR_AP: AP with tx antenna set on tx desc
 461 * @AR5K_ANTMODE_SECTOR_STA: STA with tx antenna set on tx desc
 462 * @AR5K_ANTMODE_DEBUG: Debug mode -A -> Rx, B-> Tx-
 463 * @AR5K_ANTMODE_MAX: Used for boundary checks
 464 *
 465 * For more infos on antenna control check out phy.c
 466 */
 467enum ath5k_ant_mode {
 468        AR5K_ANTMODE_DEFAULT    = 0,
 469        AR5K_ANTMODE_FIXED_A    = 1,
 470        AR5K_ANTMODE_FIXED_B    = 2,
 471        AR5K_ANTMODE_SINGLE_AP  = 3,
 472        AR5K_ANTMODE_SECTOR_AP  = 4,
 473        AR5K_ANTMODE_SECTOR_STA = 5,
 474        AR5K_ANTMODE_DEBUG      = 6,
 475        AR5K_ANTMODE_MAX,
 476};
 477
 478/**
 479 * enum ath5k_bw_mode - Bandwidth operation mode
 480 * @AR5K_BWMODE_DEFAULT: 20MHz, default operation
 481 * @AR5K_BWMODE_5MHZ: Quarter rate
 482 * @AR5K_BWMODE_10MHZ: Half rate
 483 * @AR5K_BWMODE_40MHZ: Turbo
 484 */
 485enum ath5k_bw_mode {
 486        AR5K_BWMODE_DEFAULT     = 0,
 487        AR5K_BWMODE_5MHZ        = 1,
 488        AR5K_BWMODE_10MHZ       = 2,
 489        AR5K_BWMODE_40MHZ       = 3
 490};
 491
 492
 493
 494/****************\
 495  TX DEFINITIONS
 496\****************/
 497
 498/**
 499 * struct ath5k_tx_status - TX Status descriptor
 500 * @ts_seqnum: Sequence number
 501 * @ts_tstamp: Timestamp
 502 * @ts_status: Status code
 503 * @ts_final_idx: Final transmission series index
 504 * @ts_final_retry: Final retry count
 505 * @ts_rssi: RSSI for received ACK
 506 * @ts_shortretry: Short retry count
 507 * @ts_virtcol: Virtual collision count
 508 * @ts_antenna: Antenna used
 509 *
 510 * TX status descriptor gets filled by the hw
 511 * on each transmission attempt.
 512 */
 513struct ath5k_tx_status {
 514        u16     ts_seqnum;
 515        u16     ts_tstamp;
 516        u8      ts_status;
 517        u8      ts_final_idx;
 518        u8      ts_final_retry;
 519        s8      ts_rssi;
 520        u8      ts_shortretry;
 521        u8      ts_virtcol;
 522        u8      ts_antenna;
 523};
 524
 525#define AR5K_TXSTAT_ALTRATE     0x80
 526#define AR5K_TXERR_XRETRY       0x01
 527#define AR5K_TXERR_FILT         0x02
 528#define AR5K_TXERR_FIFO         0x04
 529
 530/**
 531 * enum ath5k_tx_queue - Queue types used to classify tx queues.
 532 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
 533 * @AR5K_TX_QUEUE_DATA: A normal data queue
 534 * @AR5K_TX_QUEUE_BEACON: The beacon queue
 535 * @AR5K_TX_QUEUE_CAB: The after-beacon queue
 536 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
 537 */
 538enum ath5k_tx_queue {
 539        AR5K_TX_QUEUE_INACTIVE = 0,
 540        AR5K_TX_QUEUE_DATA,
 541        AR5K_TX_QUEUE_BEACON,
 542        AR5K_TX_QUEUE_CAB,
 543        AR5K_TX_QUEUE_UAPSD,
 544};
 545
 546#define AR5K_NUM_TX_QUEUES              10
 547#define AR5K_NUM_TX_QUEUES_NOQCU        2
 548
 549/**
 550 * enum ath5k_tx_queue_subtype - Queue sub-types to classify normal data queues
 551 * @AR5K_WME_AC_BK: Background traffic
 552 * @AR5K_WME_AC_BE: Best-effort (normal) traffic
 553 * @AR5K_WME_AC_VI: Video traffic
 554 * @AR5K_WME_AC_VO: Voice traffic
 555 *
 556 * These are the 4 Access Categories as defined in
 557 * WME spec. 0 is the lowest priority and 4 is the
 558 * highest. Normal data that hasn't been classified
 559 * goes to the Best Effort AC.
 560 */
 561enum ath5k_tx_queue_subtype {
 562        AR5K_WME_AC_BK = 0,
 563        AR5K_WME_AC_BE,
 564        AR5K_WME_AC_VI,
 565        AR5K_WME_AC_VO,
 566};
 567
 568/**
 569 * enum ath5k_tx_queue_id - Queue ID numbers as returned by the hw functions
 570 * @AR5K_TX_QUEUE_ID_NOQCU_DATA: Data queue on AR5210 (no QCU available)
 571 * @AR5K_TX_QUEUE_ID_NOQCU_BEACON: Beacon queue on AR5210 (no QCU available)
 572 * @AR5K_TX_QUEUE_ID_DATA_MIN: Data queue min index
 573 * @AR5K_TX_QUEUE_ID_DATA_MAX: Data queue max index
 574 * @AR5K_TX_QUEUE_ID_CAB: Content after beacon queue
 575 * @AR5K_TX_QUEUE_ID_BEACON: Beacon queue
 576 * @AR5K_TX_QUEUE_ID_UAPSD: Urgent Automatic Power Save Delivery,
 577 *
 578 * Each number represents a hw queue. If hw does not support hw queues
 579 * (eg 5210) all data goes in one queue.
 580 */
 581enum ath5k_tx_queue_id {
 582        AR5K_TX_QUEUE_ID_NOQCU_DATA     = 0,
 583        AR5K_TX_QUEUE_ID_NOQCU_BEACON   = 1,
 584        AR5K_TX_QUEUE_ID_DATA_MIN       = 0,
 585        AR5K_TX_QUEUE_ID_DATA_MAX       = 3,
 586        AR5K_TX_QUEUE_ID_UAPSD          = 7,
 587        AR5K_TX_QUEUE_ID_CAB            = 8,
 588        AR5K_TX_QUEUE_ID_BEACON         = 9,
 589};
 590
 591/*
 592 * Flags to set hw queue's parameters...
 593 */
 594#define AR5K_TXQ_FLAG_TXOKINT_ENABLE            0x0001  /* Enable TXOK interrupt */
 595#define AR5K_TXQ_FLAG_TXERRINT_ENABLE           0x0002  /* Enable TXERR interrupt */
 596#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE           0x0004  /* Enable TXEOL interrupt -not used- */
 597#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE          0x0008  /* Enable TXDESC interrupt -not used- */
 598#define AR5K_TXQ_FLAG_TXURNINT_ENABLE           0x0010  /* Enable TXURN interrupt */
 599#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE          0x0020  /* Enable CBRORN interrupt */
 600#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE          0x0040  /* Enable CBRURN interrupt */
 601#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE           0x0080  /* Enable QTRIG interrupt */
 602#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE         0x0100  /* Enable TXNOFRM interrupt */
 603#define AR5K_TXQ_FLAG_BACKOFF_DISABLE           0x0200  /* Disable random post-backoff */
 604#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300  /* Enable ready time expiry policy (?)*/
 605#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800  /* Enable backoff while bursting */
 606#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS         0x1000  /* Disable backoff while bursting */
 607#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE        0x2000  /* Enable hw compression -not implemented-*/
 608
 609/**
 610 * struct ath5k_txq - Transmit queue state
 611 * @qnum: Hardware q number
 612 * @link: Link ptr in last TX desc
 613 * @q: Transmit queue (&struct list_head)
 614 * @lock: Lock on q and link
 615 * @setup: Is the queue configured
 616 * @txq_len:Number of queued buffers
 617 * @txq_max: Max allowed num of queued buffers
 618 * @txq_poll_mark: Used to check if queue got stuck
 619 * @txq_stuck: Queue stuck counter
 620 *
 621 * One of these exists for each hardware transmit queue.
 622 * Packets sent to us from above are assigned to queues based
 623 * on their priority.  Not all devices support a complete set
 624 * of hardware transmit queues. For those devices the array
 625 * sc_ac2q will map multiple priorities to fewer hardware queues
 626 * (typically all to one hardware queue).
 627 */
 628struct ath5k_txq {
 629        unsigned int            qnum;
 630        u32                     *link;
 631        struct list_head        q;
 632        spinlock_t              lock;
 633        bool                    setup;
 634        int                     txq_len;
 635        int                     txq_max;
 636        bool                    txq_poll_mark;
 637        unsigned int            txq_stuck;
 638};
 639
 640/**
 641 * struct ath5k_txq_info - A struct to hold TX queue's parameters
 642 * @tqi_type: One of enum ath5k_tx_queue
 643 * @tqi_subtype: One of enum ath5k_tx_queue_subtype
 644 * @tqi_flags: TX queue flags (see above)
 645 * @tqi_aifs: Arbitrated Inter-frame Space
 646 * @tqi_cw_min: Minimum Contention Window
 647 * @tqi_cw_max: Maximum Contention Window
 648 * @tqi_cbr_period: Constant bit rate period
 649 * @tqi_ready_time: Time queue waits after an event when RDYTIME is enabled
 650 */
 651struct ath5k_txq_info {
 652        enum ath5k_tx_queue tqi_type;
 653        enum ath5k_tx_queue_subtype tqi_subtype;
 654        u16     tqi_flags;
 655        u8      tqi_aifs;
 656        u16     tqi_cw_min;
 657        u16     tqi_cw_max;
 658        u32     tqi_cbr_period;
 659        u32     tqi_cbr_overflow_limit;
 660        u32     tqi_burst_time;
 661        u32     tqi_ready_time;
 662};
 663
 664/**
 665 * enum ath5k_pkt_type - Transmit packet types
 666 * @AR5K_PKT_TYPE_NORMAL: Normal data
 667 * @AR5K_PKT_TYPE_ATIM: ATIM
 668 * @AR5K_PKT_TYPE_PSPOLL: PS-Poll
 669 * @AR5K_PKT_TYPE_BEACON: Beacon
 670 * @AR5K_PKT_TYPE_PROBE_RESP: Probe response
 671 * @AR5K_PKT_TYPE_PIFS: PIFS
 672 * Used on tx control descriptor
 673 */
 674enum ath5k_pkt_type {
 675        AR5K_PKT_TYPE_NORMAL            = 0,
 676        AR5K_PKT_TYPE_ATIM              = 1,
 677        AR5K_PKT_TYPE_PSPOLL            = 2,
 678        AR5K_PKT_TYPE_BEACON            = 3,
 679        AR5K_PKT_TYPE_PROBE_RESP        = 4,
 680        AR5K_PKT_TYPE_PIFS              = 5,
 681};
 682
 683/*
 684 * TX power and TPC settings
 685 */
 686#define AR5K_TXPOWER_OFDM(_r, _v)       (                       \
 687        ((0 & 1) << ((_v) + 6)) |                               \
 688        (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
 689)
 690
 691#define AR5K_TXPOWER_CCK(_r, _v)        (                       \
 692        (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v)     \
 693)
 694
 695
 696
 697/****************\
 698  RX DEFINITIONS
 699\****************/
 700
 701/**
 702 * struct ath5k_rx_status - RX Status descriptor
 703 * @rs_datalen: Data length
 704 * @rs_tstamp: Timestamp
 705 * @rs_status: Status code
 706 * @rs_phyerr: PHY error mask
 707 * @rs_rssi: RSSI in 0.5dbm units
 708 * @rs_keyix: Index to the key used for decrypting
 709 * @rs_rate: Rate used to decode the frame
 710 * @rs_antenna: Antenna used to receive the frame
 711 * @rs_more: Indicates this is a frame fragment (Fast frames)
 712 */
 713struct ath5k_rx_status {
 714        u16     rs_datalen;
 715        u16     rs_tstamp;
 716        u8      rs_status;
 717        u8      rs_phyerr;
 718        s8      rs_rssi;
 719        u8      rs_keyix;
 720        u8      rs_rate;
 721        u8      rs_antenna;
 722        u8      rs_more;
 723};
 724
 725#define AR5K_RXERR_CRC          0x01
 726#define AR5K_RXERR_PHY          0x02
 727#define AR5K_RXERR_FIFO         0x04
 728#define AR5K_RXERR_DECRYPT      0x08
 729#define AR5K_RXERR_MIC          0x10
 730#define AR5K_RXKEYIX_INVALID    ((u8) -1)
 731#define AR5K_TXKEYIX_INVALID    ((u32) -1)
 732
 733
 734/**************************\
 735 BEACON TIMERS DEFINITIONS
 736\**************************/
 737
 738#define AR5K_BEACON_PERIOD      0x0000ffff
 739#define AR5K_BEACON_ENA         0x00800000 /*enable beacon xmit*/
 740#define AR5K_BEACON_RESET_TSF   0x01000000 /*force a TSF reset*/
 741
 742
 743/*
 744 * TSF to TU conversion:
 745 *
 746 * TSF is a 64bit value in usec (microseconds).
 747 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
 748 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
 749 */
 750#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
 751
 752
 753
 754/*******************************\
 755  GAIN OPTIMIZATION DEFINITIONS
 756\*******************************/
 757
 758/**
 759 * enum ath5k_rfgain - RF Gain optimization engine state
 760 * @AR5K_RFGAIN_INACTIVE: Engine disabled
 761 * @AR5K_RFGAIN_ACTIVE: Probe active
 762 * @AR5K_RFGAIN_READ_REQUESTED: Probe requested
 763 * @AR5K_RFGAIN_NEED_CHANGE: Gain_F needs change
 764 */
 765enum ath5k_rfgain {
 766        AR5K_RFGAIN_INACTIVE = 0,
 767        AR5K_RFGAIN_ACTIVE,
 768        AR5K_RFGAIN_READ_REQUESTED,
 769        AR5K_RFGAIN_NEED_CHANGE,
 770};
 771
 772/**
 773 * struct ath5k_gain - RF Gain optimization engine state data
 774 * @g_step_idx: Current step index
 775 * @g_current: Current gain
 776 * @g_target: Target gain
 777 * @g_low: Low gain boundary
 778 * @g_high: High gain boundary
 779 * @g_f_corr: Gain_F correction
 780 * @g_state: One of enum ath5k_rfgain
 781 */
 782struct ath5k_gain {
 783        u8                      g_step_idx;
 784        u8                      g_current;
 785        u8                      g_target;
 786        u8                      g_low;
 787        u8                      g_high;
 788        u8                      g_f_corr;
 789        u8                      g_state;
 790};
 791
 792
 793
 794/********************\
 795  COMMON DEFINITIONS
 796\********************/
 797
 798#define AR5K_SLOT_TIME_9        396
 799#define AR5K_SLOT_TIME_20       880
 800#define AR5K_SLOT_TIME_MAX      0xffff
 801
 802/**
 803 * struct ath5k_athchan_2ghz - 2GHz to 5GHZ map for RF5111
 804 * @a2_flags: Channel flags (internal)
 805 * @a2_athchan: HW channel number (internal)
 806 *
 807 * This structure is used to map 2GHz channels to
 808 * 5GHz Atheros channels on 2111 frequency converter
 809 * that comes together with RF5111
 810 * TODO: Clean up
 811 */
 812struct ath5k_athchan_2ghz {
 813        u32     a2_flags;
 814        u16     a2_athchan;
 815};
 816
 817/**
 818 * enum ath5k_dmasize -  DMA size definitions (2^(n+2))
 819 * @AR5K_DMASIZE_4B: 4Bytes
 820 * @AR5K_DMASIZE_8B: 8Bytes
 821 * @AR5K_DMASIZE_16B: 16Bytes
 822 * @AR5K_DMASIZE_32B: 32Bytes
 823 * @AR5K_DMASIZE_64B: 64Bytes (Default)
 824 * @AR5K_DMASIZE_128B: 128Bytes
 825 * @AR5K_DMASIZE_256B: 256Bytes
 826 * @AR5K_DMASIZE_512B: 512Bytes
 827 *
 828 * These are used to set DMA burst size on hw
 829 *
 830 * Note: Some platforms can't handle more than 4Bytes
 831 * be careful on embedded boards.
 832 */
 833enum ath5k_dmasize {
 834        AR5K_DMASIZE_4B = 0,
 835        AR5K_DMASIZE_8B,
 836        AR5K_DMASIZE_16B,
 837        AR5K_DMASIZE_32B,
 838        AR5K_DMASIZE_64B,
 839        AR5K_DMASIZE_128B,
 840        AR5K_DMASIZE_256B,
 841        AR5K_DMASIZE_512B
 842};
 843
 844
 845
 846/******************\
 847  RATE DEFINITIONS
 848\******************/
 849
 850/**
 851 * DOC: Rate codes
 852 *
 853 * Seems the ar5xxx hardware supports up to 32 rates, indexed by 1-32.
 854 *
 855 * The rate code is used to get the RX rate or set the TX rate on the
 856 * hardware descriptors. It is also used for internal modulation control
 857 * and settings.
 858 *
 859 * This is the hardware rate map we are aware of (html unfriendly):
 860 *
 861 * Rate code    Rate (Kbps)
 862 * ---------    -----------
 863 * 0x01          3000 (XR)
 864 * 0x02          1000 (XR)
 865 * 0x03           250 (XR)
 866 * 0x04 - 05    -Reserved-
 867 * 0x06          2000 (XR)
 868 * 0x07           500 (XR)
 869 * 0x08         48000 (OFDM)
 870 * 0x09         24000 (OFDM)
 871 * 0x0A         12000 (OFDM)
 872 * 0x0B          6000 (OFDM)
 873 * 0x0C         54000 (OFDM)
 874 * 0x0D         36000 (OFDM)
 875 * 0x0E         18000 (OFDM)
 876 * 0x0F          9000 (OFDM)
 877 * 0x10 - 17    -Reserved-
 878 * 0x18         11000L (CCK)
 879 * 0x19          5500L (CCK)
 880 * 0x1A          2000L (CCK)
 881 * 0x1B          1000L (CCK)
 882 * 0x1C         11000S (CCK)
 883 * 0x1D          5500S (CCK)
 884 * 0x1E          2000S (CCK)
 885 * 0x1F         -Reserved-
 886 *
 887 * "S" indicates CCK rates with short preamble and "L" with long preamble.
 888 *
 889 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
 890 * lowest 4 bits, so they are the same as above with a 0xF mask.
 891 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
 892 * We handle this in ath5k_setup_bands().
 893 */
 894#define AR5K_MAX_RATES 32
 895
 896/* B */
 897#define ATH5K_RATE_CODE_1M      0x1B
 898#define ATH5K_RATE_CODE_2M      0x1A
 899#define ATH5K_RATE_CODE_5_5M    0x19
 900#define ATH5K_RATE_CODE_11M     0x18
 901/* A and G */
 902#define ATH5K_RATE_CODE_6M      0x0B
 903#define ATH5K_RATE_CODE_9M      0x0F
 904#define ATH5K_RATE_CODE_12M     0x0A
 905#define ATH5K_RATE_CODE_18M     0x0E
 906#define ATH5K_RATE_CODE_24M     0x09
 907#define ATH5K_RATE_CODE_36M     0x0D
 908#define ATH5K_RATE_CODE_48M     0x08
 909#define ATH5K_RATE_CODE_54M     0x0C
 910
 911/* Adding this flag to rate_code on B rates
 912 * enables short preamble */
 913#define AR5K_SET_SHORT_PREAMBLE 0x04
 914
 915/*
 916 * Crypto definitions
 917 */
 918
 919#define AR5K_KEYCACHE_SIZE      8
 920extern bool ath5k_modparam_nohwcrypt;
 921
 922/***********************\
 923 HW RELATED DEFINITIONS
 924\***********************/
 925
 926/*
 927 * Misc definitions
 928 */
 929#define AR5K_RSSI_EP_MULTIPLIER (1 << 7)
 930
 931#define AR5K_ASSERT_ENTRY(_e, _s) do {          \
 932        if (_e >= _s)                           \
 933                return false;                   \
 934} while (0)
 935
 936/*
 937 * Hardware interrupt abstraction
 938 */
 939
 940/**
 941 * enum ath5k_int - Hardware interrupt masks helpers
 942 * @AR5K_INT_RXOK: Frame successfully received
 943 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor
 944 * @AR5K_INT_RXERR: Frame reception failed
 945 * @AR5K_INT_RXNOFRM: No frame received within a specified time period
 946 * @AR5K_INT_RXEOL: Reached "End Of List", means we need more RX descriptors
 947 * @AR5K_INT_RXORN: Indicates we got RX FIFO overrun. Note that Rx overrun is
 948 *              not always fatal, on some chips we can continue operation
 949 *              without resetting the card, that's why %AR5K_INT_FATAL is not
 950 *              common for all chips.
 951 * @AR5K_INT_RX_ALL: Mask to identify all RX related interrupts
 952 *
 953 * @AR5K_INT_TXOK: Frame transmission success
 954 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor
 955 * @AR5K_INT_TXERR: Frame transmission failure
 956 * @AR5K_INT_TXEOL: Received End Of List for VEOL (Virtual End Of List). The
 957 *              Queue Control Unit (QCU) signals an EOL interrupt only if a
 958 *              descriptor's LinkPtr is NULL. For more details, refer to:
 959 *              "http://www.freepatentsonline.com/20030225739.html"
 960 * @AR5K_INT_TXNOFRM: No frame was transmitted within a specified time period
 961 * @AR5K_INT_TXURN: Indicates we got TX FIFO underrun. In such case we should
 962 *              increase the TX trigger threshold.
 963 * @AR5K_INT_TX_ALL: Mask to identify all TX related interrupts
 964 *
 965 * @AR5K_INT_MIB: Indicates the either Management Information Base counters or
 966 *              one of the PHY error counters reached the maximum value and
 967 *              should be read and cleared.
 968 * @AR5K_INT_SWI: Software triggered interrupt.
 969 * @AR5K_INT_RXPHY: RX PHY Error
 970 * @AR5K_INT_RXKCM: RX Key cache miss
 971 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
 972 *              beacon that must be handled in software. The alternative is if
 973 *              you have VEOL support, in that case you let the hardware deal
 974 *              with things.
 975 * @AR5K_INT_BRSSI: Beacon received with an RSSI value below our threshold
 976 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
 977 *              beacons from the AP have associated with, we should probably
 978 *              try to reassociate. When in IBSS mode this might mean we have
 979 *              not received any beacons from any local stations. Note that
 980 *              every station in an IBSS schedules to send beacons at the
 981 *              Target Beacon Transmission Time (TBTT) with a random backoff.
 982 * @AR5K_INT_BNR: Beacon queue got triggered (DMA beacon alert) while empty.
 983 * @AR5K_INT_TIM: Beacon with local station's TIM bit set
 984 * @AR5K_INT_DTIM: Beacon with DTIM bit and zero DTIM count received
 985 * @AR5K_INT_DTIM_SYNC: DTIM sync lost
 986 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill switches connected to
 987 *              our GPIO pins.
 988 * @AR5K_INT_BCN_TIMEOUT: Beacon timeout, we waited after TBTT but got noting
 989 * @AR5K_INT_CAB_TIMEOUT: We waited for CAB traffic after the beacon but got
 990 *              nothing or an incomplete CAB frame sequence.
 991 * @AR5K_INT_QCBRORN: A queue got it's CBR counter expired
 992 * @AR5K_INT_QCBRURN: A queue got triggered wile empty
 993 * @AR5K_INT_QTRIG: A queue got triggered
 994 *
 995 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by bus/DMA
 996 *              errors. Indicates we need to reset the card.
 997 * @AR5K_INT_GLOBAL: Used to clear and set the IER
 998 * @AR5K_INT_NOCARD: Signals the card has been removed
 999 * @AR5K_INT_COMMON: Common interrupts shared among MACs with the same
1000 *              bit value
1001 *
1002 * These are mapped to take advantage of some common bits
1003 * between the MACs, to be able to set intr properties
1004 * easier. Some of them are not used yet inside hw.c. Most map
1005 * to the respective hw interrupt value as they are common among different
1006 * MACs.
1007 */
1008enum ath5k_int {
1009        AR5K_INT_RXOK   = 0x00000001,
1010        AR5K_INT_RXDESC = 0x00000002,
1011        AR5K_INT_RXERR  = 0x00000004,
1012        AR5K_INT_RXNOFRM = 0x00000008,
1013        AR5K_INT_RXEOL  = 0x00000010,
1014        AR5K_INT_RXORN  = 0x00000020,
1015        AR5K_INT_TXOK   = 0x00000040,
1016        AR5K_INT_TXDESC = 0x00000080,
1017        AR5K_INT_TXERR  = 0x00000100,
1018        AR5K_INT_TXNOFRM = 0x00000200,
1019        AR5K_INT_TXEOL  = 0x00000400,
1020        AR5K_INT_TXURN  = 0x00000800,
1021        AR5K_INT_MIB    = 0x00001000,
1022        AR5K_INT_SWI    = 0x00002000,
1023        AR5K_INT_RXPHY  = 0x00004000,
1024        AR5K_INT_RXKCM  = 0x00008000,
1025        AR5K_INT_SWBA   = 0x00010000,
1026        AR5K_INT_BRSSI  = 0x00020000,
1027        AR5K_INT_BMISS  = 0x00040000,
1028        AR5K_INT_FATAL  = 0x00080000, /* Non common */
1029        AR5K_INT_BNR    = 0x00100000, /* Non common */
1030        AR5K_INT_TIM    = 0x00200000, /* Non common */
1031        AR5K_INT_DTIM   = 0x00400000, /* Non common */
1032        AR5K_INT_DTIM_SYNC =    0x00800000, /* Non common */
1033        AR5K_INT_GPIO   =       0x01000000,
1034        AR5K_INT_BCN_TIMEOUT =  0x02000000, /* Non common */
1035        AR5K_INT_CAB_TIMEOUT =  0x04000000, /* Non common */
1036        AR5K_INT_QCBRORN =      0x08000000, /* Non common */
1037        AR5K_INT_QCBRURN =      0x10000000, /* Non common */
1038        AR5K_INT_QTRIG  =       0x20000000, /* Non common */
1039        AR5K_INT_GLOBAL =       0x80000000,
1040
1041        AR5K_INT_TX_ALL = AR5K_INT_TXOK
1042                | AR5K_INT_TXDESC
1043                | AR5K_INT_TXERR
1044                | AR5K_INT_TXNOFRM
1045                | AR5K_INT_TXEOL
1046                | AR5K_INT_TXURN,
1047
1048        AR5K_INT_RX_ALL = AR5K_INT_RXOK
1049                | AR5K_INT_RXDESC
1050                | AR5K_INT_RXERR
1051                | AR5K_INT_RXNOFRM
1052                | AR5K_INT_RXEOL
1053                | AR5K_INT_RXORN,
1054
1055        AR5K_INT_COMMON  = AR5K_INT_RXOK
1056                | AR5K_INT_RXDESC
1057                | AR5K_INT_RXERR
1058                | AR5K_INT_RXNOFRM
1059                | AR5K_INT_RXEOL
1060                | AR5K_INT_RXORN
1061                | AR5K_INT_TXOK
1062                | AR5K_INT_TXDESC
1063                | AR5K_INT_TXERR
1064                | AR5K_INT_TXNOFRM
1065                | AR5K_INT_TXEOL
1066                | AR5K_INT_TXURN
1067                | AR5K_INT_MIB
1068                | AR5K_INT_SWI
1069                | AR5K_INT_RXPHY
1070                | AR5K_INT_RXKCM
1071                | AR5K_INT_SWBA
1072                | AR5K_INT_BRSSI
1073                | AR5K_INT_BMISS
1074                | AR5K_INT_GPIO
1075                | AR5K_INT_GLOBAL,
1076
1077        AR5K_INT_NOCARD = 0xffffffff
1078};
1079
1080/**
1081 * enum ath5k_calibration_mask - Mask which calibration is active at the moment
1082 * @AR5K_CALIBRATION_FULL: Full calibration (AGC + SHORT)
1083 * @AR5K_CALIBRATION_SHORT: Short calibration (NF + I/Q)
1084 * @AR5K_CALIBRATION_NF: Noise Floor calibration
1085 * @AR5K_CALIBRATION_ANI: Adaptive Noise Immunity
1086 */
1087enum ath5k_calibration_mask {
1088        AR5K_CALIBRATION_FULL = 0x01,
1089        AR5K_CALIBRATION_SHORT = 0x02,
1090        AR5K_CALIBRATION_NF = 0x04,
1091        AR5K_CALIBRATION_ANI = 0x08,
1092};
1093
1094/**
1095 * enum ath5k_power_mode - Power management modes
1096 * @AR5K_PM_UNDEFINED: Undefined
1097 * @AR5K_PM_AUTO: Allow card to sleep if possible
1098 * @AR5K_PM_AWAKE: Force card to wake up
1099 * @AR5K_PM_FULL_SLEEP: Force card to full sleep (DANGEROUS)
1100 * @AR5K_PM_NETWORK_SLEEP: Allow to sleep for a specified duration
1101 *
1102 * Currently only PM_AWAKE is used, FULL_SLEEP and NETWORK_SLEEP/AUTO
1103 * are also known to have problems on some cards. This is not a big
1104 * problem though because we can have almost the same effect as
1105 * FULL_SLEEP by putting card on warm reset (it's almost powered down).
1106 */
1107enum ath5k_power_mode {
1108        AR5K_PM_UNDEFINED = 0,
1109        AR5K_PM_AUTO,
1110        AR5K_PM_AWAKE,
1111        AR5K_PM_FULL_SLEEP,
1112        AR5K_PM_NETWORK_SLEEP,
1113};
1114
1115/*
1116 * These match net80211 definitions (not used in
1117 * mac80211).
1118 * TODO: Clean this up
1119 */
1120#define AR5K_LED_INIT   0 /*IEEE80211_S_INIT*/
1121#define AR5K_LED_SCAN   1 /*IEEE80211_S_SCAN*/
1122#define AR5K_LED_AUTH   2 /*IEEE80211_S_AUTH*/
1123#define AR5K_LED_ASSOC  3 /*IEEE80211_S_ASSOC*/
1124#define AR5K_LED_RUN    4 /*IEEE80211_S_RUN*/
1125
1126/* GPIO-controlled software LED */
1127#define AR5K_SOFTLED_PIN        0
1128#define AR5K_SOFTLED_ON         0
1129#define AR5K_SOFTLED_OFF        1
1130
1131
1132/* XXX: we *may* move cap_range stuff to struct wiphy */
1133struct ath5k_capabilities {
1134        /*
1135         * Supported PHY modes
1136         * (ie. AR5K_MODE_11A, AR5K_MODE_11B, ...)
1137         */
1138        DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX);
1139
1140        /*
1141         * Frequency range (without regulation restrictions)
1142         */
1143        struct {
1144                u16     range_2ghz_min;
1145                u16     range_2ghz_max;
1146                u16     range_5ghz_min;
1147                u16     range_5ghz_max;
1148        } cap_range;
1149
1150        /*
1151         * Values stored in the EEPROM (some of them...)
1152         */
1153        struct ath5k_eeprom_info        cap_eeprom;
1154
1155        /*
1156         * Queue information
1157         */
1158        struct {
1159                u8      q_tx_num;
1160        } cap_queues;
1161
1162        bool cap_has_phyerr_counters;
1163        bool cap_has_mrr_support;
1164        bool cap_needs_2GHz_ovr;
1165};
1166
1167/* size of noise floor history (keep it a power of two) */
1168#define ATH5K_NF_CAL_HIST_MAX   8
1169struct ath5k_nfcal_hist {
1170        s16 index;                              /* current index into nfval */
1171        s16 nfval[ATH5K_NF_CAL_HIST_MAX];       /* last few noise floors */
1172};
1173
1174#define ATH5K_LED_MAX_NAME_LEN 31
1175
1176/*
1177 * State for LED triggers
1178 */
1179struct ath5k_led {
1180        char name[ATH5K_LED_MAX_NAME_LEN + 1];  /* name of the LED in sysfs */
1181        struct ath5k_hw *ah;                    /* driver state */
1182        struct led_classdev led_dev;            /* led classdev */
1183};
1184
1185/* Rfkill */
1186struct ath5k_rfkill {
1187        /* GPIO PIN for rfkill */
1188        u16 gpio;
1189        /* polarity of rfkill GPIO PIN */
1190        bool polarity;
1191        /* RFKILL toggle tasklet */
1192        struct tasklet_struct toggleq;
1193};
1194
1195/* statistics */
1196struct ath5k_statistics {
1197        /* antenna use */
1198        unsigned int antenna_rx[5];     /* frames count per antenna RX */
1199        unsigned int antenna_tx[5];     /* frames count per antenna TX */
1200
1201        /* frame errors */
1202        unsigned int rx_all_count;      /* all RX frames, including errors */
1203        unsigned int tx_all_count;      /* all TX frames, including errors */
1204        unsigned int rx_bytes_count;    /* all RX bytes, including errored pkts
1205                                         * and the MAC headers for each packet
1206                                         */
1207        unsigned int tx_bytes_count;    /* all TX bytes, including errored pkts
1208                                         * and the MAC headers and padding for
1209                                         * each packet.
1210                                         */
1211        unsigned int rxerr_crc;
1212        unsigned int rxerr_phy;
1213        unsigned int rxerr_phy_code[32];
1214        unsigned int rxerr_fifo;
1215        unsigned int rxerr_decrypt;
1216        unsigned int rxerr_mic;
1217        unsigned int rxerr_proc;
1218        unsigned int rxerr_jumbo;
1219        unsigned int txerr_retry;
1220        unsigned int txerr_fifo;
1221        unsigned int txerr_filt;
1222
1223        /* MIB counters */
1224        unsigned int ack_fail;
1225        unsigned int rts_fail;
1226        unsigned int rts_ok;
1227        unsigned int fcs_error;
1228        unsigned int beacons;
1229
1230        unsigned int mib_intr;
1231        unsigned int rxorn_intr;
1232        unsigned int rxeol_intr;
1233};
1234
1235/*
1236 * Misc defines
1237 */
1238
1239#define AR5K_MAX_GPIO           10
1240#define AR5K_MAX_RF_BANKS       8
1241
1242#if CHAN_DEBUG
1243#define ATH_CHAN_MAX    (26 + 26 + 26 + 200 + 200)
1244#else
1245#define ATH_CHAN_MAX    (14 + 14 + 14 + 252 + 20)
1246#endif
1247
1248#define ATH_RXBUF       40              /* number of RX buffers */
1249#define ATH_TXBUF       200             /* number of TX buffers */
1250#define ATH_BCBUF       4               /* number of beacon buffers */
1251#define ATH5K_TXQ_LEN_MAX       (ATH_TXBUF / 4)         /* bufs per queue */
1252#define ATH5K_TXQ_LEN_LOW       (ATH5K_TXQ_LEN_MAX / 2) /* low mark */
1253
1254/* Driver state associated with an instance of a device */
1255struct ath5k_hw {
1256        struct ath_common       common;
1257
1258        struct pci_dev          *pdev;
1259        struct device           *dev;           /* for dma mapping */
1260        int irq;
1261        u16 devid;
1262        void __iomem            *iobase;        /* address of the device */
1263        struct mutex            lock;           /* dev-level lock */
1264        struct ieee80211_hw     *hw;            /* IEEE 802.11 common */
1265        struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
1266        struct ieee80211_channel channels[ATH_CHAN_MAX];
1267        struct ieee80211_rate   rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
1268        s8                      rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
1269        enum nl80211_iftype     opmode;
1270
1271#ifdef CONFIG_ATH5K_DEBUG
1272        struct ath5k_dbg_info   debug;          /* debug info */
1273#endif /* CONFIG_ATH5K_DEBUG */
1274
1275        struct ath5k_buf        *bufptr;        /* allocated buffer ptr */
1276        struct ath5k_desc       *desc;          /* TX/RX descriptors */
1277        dma_addr_t              desc_daddr;     /* DMA (physical) address */
1278        size_t                  desc_len;       /* size of TX/RX descriptors */
1279
1280        DECLARE_BITMAP(status, 4);
1281#define ATH_STAT_INVALID        0               /* disable hardware accesses */
1282#define ATH_STAT_PROMISC        1
1283#define ATH_STAT_LEDSOFT        2               /* enable LED gpio status */
1284#define ATH_STAT_STARTED        3               /* opened & irqs enabled */
1285
1286        unsigned int            filter_flags;   /* HW flags, AR5K_RX_FILTER_* */
1287        struct ieee80211_channel *curchan;      /* current h/w channel */
1288
1289        u16                     nvifs;
1290
1291        enum ath5k_int          imask;          /* interrupt mask copy */
1292
1293        spinlock_t              irqlock;
1294        bool                    rx_pending;     /* rx tasklet pending */
1295        bool                    tx_pending;     /* tx tasklet pending */
1296
1297        u8                      bssidmask[ETH_ALEN];
1298
1299        unsigned int            led_pin,        /* GPIO pin for driving LED */
1300                                led_on;         /* pin setting for LED on */
1301
1302        struct work_struct      reset_work;     /* deferred chip reset */
1303        struct work_struct      calib_work;     /* deferred phy calibration */
1304
1305        struct list_head        rxbuf;          /* receive buffer */
1306        spinlock_t              rxbuflock;
1307        u32                     *rxlink;        /* link ptr in last RX desc */
1308        struct tasklet_struct   rxtq;           /* rx intr tasklet */
1309        struct ath5k_led        rx_led;         /* rx led */
1310
1311        struct list_head        txbuf;          /* transmit buffer */
1312        spinlock_t              txbuflock;
1313        unsigned int            txbuf_len;      /* buf count in txbuf list */
1314        struct ath5k_txq        txqs[AR5K_NUM_TX_QUEUES];       /* tx queues */
1315        struct tasklet_struct   txtq;           /* tx intr tasklet */
1316        struct ath5k_led        tx_led;         /* tx led */
1317
1318        struct ath5k_rfkill     rf_kill;
1319
1320        spinlock_t              block;          /* protects beacon */
1321        struct tasklet_struct   beacontq;       /* beacon intr tasklet */
1322        struct list_head        bcbuf;          /* beacon buffer */
1323        struct ieee80211_vif    *bslot[ATH_BCBUF];
1324        u16                     num_ap_vifs;
1325        u16                     num_adhoc_vifs;
1326        u16                     num_mesh_vifs;
1327        unsigned int            bhalq,          /* SW q for outgoing beacons */
1328                                bmisscount,     /* missed beacon transmits */
1329                                bintval,        /* beacon interval in TU */
1330                                bsent;
1331        unsigned int            nexttbtt;       /* next beacon time in TU */
1332        struct ath5k_txq        *cabq;          /* content after beacon */
1333
1334        bool                    assoc;          /* associate state */
1335        bool                    enable_beacon;  /* true if beacons are on */
1336
1337        struct ath5k_statistics stats;
1338
1339        struct ath5k_ani_state  ani_state;
1340        struct tasklet_struct   ani_tasklet;    /* ANI calibration */
1341
1342        struct delayed_work     tx_complete_work;
1343
1344        struct survey_info      survey;         /* collected survey info */
1345
1346        enum ath5k_int          ah_imr;
1347
1348        struct ieee80211_channel *ah_current_channel;
1349        bool                    ah_iq_cal_needed;
1350        bool                    ah_single_chip;
1351
1352        enum ath5k_version      ah_version;
1353        enum ath5k_radio        ah_radio;
1354        u32                     ah_mac_srev;
1355        u16                     ah_mac_version;
1356        u16                     ah_phy_revision;
1357        u16                     ah_radio_5ghz_revision;
1358        u16                     ah_radio_2ghz_revision;
1359
1360#define ah_modes                ah_capabilities.cap_mode
1361#define ah_ee_version           ah_capabilities.cap_eeprom.ee_version
1362
1363        u8                      ah_retry_long;
1364        u8                      ah_retry_short;
1365
1366        u32                     ah_use_32khz_clock;
1367
1368        u8                      ah_coverage_class;
1369        bool                    ah_ack_bitrate_high;
1370        u8                      ah_bwmode;
1371        bool                    ah_short_slot;
1372
1373        /* Antenna Control */
1374        u32                     ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
1375        u8                      ah_ant_mode;
1376        u8                      ah_tx_ant;
1377        u8                      ah_def_ant;
1378
1379        struct ath5k_capabilities ah_capabilities;
1380
1381        struct ath5k_txq_info   ah_txq[AR5K_NUM_TX_QUEUES];
1382        u32                     ah_txq_status;
1383        u32                     ah_txq_imr_txok;
1384        u32                     ah_txq_imr_txerr;
1385        u32                     ah_txq_imr_txurn;
1386        u32                     ah_txq_imr_txdesc;
1387        u32                     ah_txq_imr_txeol;
1388        u32                     ah_txq_imr_cbrorn;
1389        u32                     ah_txq_imr_cbrurn;
1390        u32                     ah_txq_imr_qtrig;
1391        u32                     ah_txq_imr_nofrm;
1392
1393        u32                     ah_txq_isr_txok_all;
1394        u32                     ah_txq_isr_txurn;
1395        u32                     ah_txq_isr_qcborn;
1396        u32                     ah_txq_isr_qcburn;
1397        u32                     ah_txq_isr_qtrig;
1398
1399        u32                     *ah_rf_banks;
1400        size_t                  ah_rf_banks_size;
1401        size_t                  ah_rf_regs_count;
1402        struct ath5k_gain       ah_gain;
1403        u8                      ah_offset[AR5K_MAX_RF_BANKS];
1404
1405
1406        struct {
1407                /* Temporary tables used for interpolation */
1408                u8              tmpL[AR5K_EEPROM_N_PD_GAINS]
1409                                        [AR5K_EEPROM_POWER_TABLE_SIZE];
1410                u8              tmpR[AR5K_EEPROM_N_PD_GAINS]
1411                                        [AR5K_EEPROM_POWER_TABLE_SIZE];
1412                u8              txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2];
1413                u16             txp_rates_power_table[AR5K_MAX_RATES];
1414                u8              txp_min_idx;
1415                bool            txp_tpc;
1416                /* Values in 0.25dB units */
1417                s16             txp_min_pwr;
1418                s16             txp_max_pwr;
1419                s16             txp_cur_pwr;
1420                /* Values in 0.5dB units */
1421                s16             txp_offset;
1422                s16             txp_ofdm;
1423                s16             txp_cck_ofdm_gainf_delta;
1424                /* Value in dB units */
1425                s16             txp_cck_ofdm_pwr_delta;
1426                bool            txp_setup;
1427                int             txp_requested;  /* Requested tx power in dBm */
1428        } ah_txpower;
1429
1430        struct ath5k_nfcal_hist ah_nfcal_hist;
1431
1432        /* average beacon RSSI in our BSS (used by ANI) */
1433        struct ewma             ah_beacon_rssi_avg;
1434
1435        /* noise floor from last periodic calibration */
1436        s32                     ah_noise_floor;
1437
1438        /* Calibration timestamp */
1439        unsigned long           ah_cal_next_full;
1440        unsigned long           ah_cal_next_short;
1441        unsigned long           ah_cal_next_ani;
1442
1443        /* Calibration mask */
1444        u8                      ah_cal_mask;
1445
1446        /*
1447         * Function pointers
1448         */
1449        int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1450                unsigned int, unsigned int, int, enum ath5k_pkt_type,
1451                unsigned int, unsigned int, unsigned int, unsigned int,
1452                unsigned int, unsigned int, unsigned int, unsigned int);
1453        int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1454                struct ath5k_tx_status *);
1455        int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1456                struct ath5k_rx_status *);
1457};
1458
1459struct ath_bus_ops {
1460        enum ath_bus_type ath_bus_type;
1461        void (*read_cachesize)(struct ath_common *common, int *csz);
1462        bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
1463        int (*eeprom_read_mac)(struct ath5k_hw *ah, u8 *mac);
1464};
1465
1466/*
1467 * Prototypes
1468 */
1469extern const struct ieee80211_ops ath5k_hw_ops;
1470
1471/* Initialization and detach functions */
1472int ath5k_hw_init(struct ath5k_hw *ah);
1473void ath5k_hw_deinit(struct ath5k_hw *ah);
1474
1475int ath5k_sysfs_register(struct ath5k_hw *ah);
1476void ath5k_sysfs_unregister(struct ath5k_hw *ah);
1477
1478/*Chip id helper functions */
1479int ath5k_hw_read_srev(struct ath5k_hw *ah);
1480
1481/* LED functions */
1482int ath5k_init_leds(struct ath5k_hw *ah);
1483void ath5k_led_enable(struct ath5k_hw *ah);
1484void ath5k_led_off(struct ath5k_hw *ah);
1485void ath5k_unregister_leds(struct ath5k_hw *ah);
1486
1487
1488/* Reset Functions */
1489int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1490int ath5k_hw_on_hold(struct ath5k_hw *ah);
1491int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1492           struct ieee80211_channel *channel, bool fast, bool skip_pcu);
1493int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
1494                              bool is_set);
1495/* Power management functions */
1496
1497
1498/* Clock rate related functions */
1499unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec);
1500unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock);
1501void ath5k_hw_set_clockrate(struct ath5k_hw *ah);
1502
1503
1504/* DMA Related Functions */
1505void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
1506u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
1507int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
1508int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1509int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue);
1510u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
1511int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
1512                                u32 phys_addr);
1513int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
1514/* Interrupt handling */
1515bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1516int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
1517enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask);
1518void ath5k_hw_update_mib_counters(struct ath5k_hw *ah);
1519/* Init/Stop functions */
1520void ath5k_hw_dma_init(struct ath5k_hw *ah);
1521int ath5k_hw_dma_stop(struct ath5k_hw *ah);
1522
1523/* EEPROM access functions */
1524int ath5k_eeprom_init(struct ath5k_hw *ah);
1525void ath5k_eeprom_detach(struct ath5k_hw *ah);
1526int ath5k_eeprom_mode_from_channel(struct ath5k_hw *ah,
1527                struct ieee80211_channel *channel);
1528
1529/* Protocol Control Unit Functions */
1530/* Helpers */
1531int ath5k_hw_get_frame_duration(struct ath5k_hw *ah, enum ieee80211_band band,
1532                int len, struct ieee80211_rate *rate, bool shortpre);
1533unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah);
1534unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah);
1535int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode);
1536void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class);
1537/* RX filter control*/
1538int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
1539void ath5k_hw_set_bssid(struct ath5k_hw *ah);
1540void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
1541void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
1542u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1543void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
1544/* Receive (DRU) start/stop functions */
1545void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
1546void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
1547/* Beacon control functions */
1548u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
1549void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
1550void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1551void ath5k_hw_init_beacon_timers(struct ath5k_hw *ah, u32 next_beacon,
1552                                                        u32 interval);
1553bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval);
1554/* Init function */
1555void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode);
1556
1557/* Queue Control Unit, DFS Control Unit Functions */
1558int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
1559                               struct ath5k_txq_info *queue_info);
1560int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
1561                               const struct ath5k_txq_info *queue_info);
1562int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
1563                            enum ath5k_tx_queue queue_type,
1564                            struct ath5k_txq_info *queue_info);
1565void ath5k_hw_set_tx_retry_limits(struct ath5k_hw *ah,
1566                                  unsigned int queue);
1567u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
1568void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1569int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1570int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time);
1571/* Init function */
1572int ath5k_hw_init_queues(struct ath5k_hw *ah);
1573
1574/* Hardware Descriptor Functions */
1575int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
1576int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
1577                           u32 size, unsigned int flags);
1578int ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
1579        unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2,
1580        u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3);
1581
1582
1583/* GPIO Functions */
1584void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
1585int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
1586int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
1587u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
1588int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
1589void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
1590                            u32 interrupt_level);
1591
1592
1593/* RFkill Functions */
1594void ath5k_rfkill_hw_start(struct ath5k_hw *ah);
1595void ath5k_rfkill_hw_stop(struct ath5k_hw *ah);
1596
1597
1598/* Misc functions TODO: Cleanup */
1599int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
1600int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
1601int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
1602
1603
1604/* Initial register settings functions */
1605int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
1606
1607
1608/* PHY functions */
1609/* Misc PHY functions */
1610u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum ieee80211_band band);
1611int ath5k_hw_phy_disable(struct ath5k_hw *ah);
1612/* Gain_F optimization */
1613enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
1614int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
1615/* PHY/RF channel functions */
1616bool ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1617/* PHY calibration */
1618void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah);
1619int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1620                           struct ieee80211_channel *channel);
1621void ath5k_hw_update_noise_floor(struct ath5k_hw *ah);
1622/* Spur mitigation */
1623bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
1624                                  struct ieee80211_channel *channel);
1625/* Antenna control */
1626void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode);
1627void ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode);
1628/* TX power setup */
1629int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower);
1630/* Init function */
1631int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
1632                                u8 mode, bool fast);
1633
1634/*
1635 * Functions used internally
1636 */
1637
1638static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah)
1639{
1640        return &ah->common;
1641}
1642
1643static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah)
1644{
1645        return &(ath5k_hw_common(ah)->regulatory);
1646}
1647
1648#ifdef CONFIG_ATHEROS_AR231X
1649#define AR5K_AR2315_PCI_BASE    ((void __iomem *)0xb0100000)
1650
1651static inline void __iomem *ath5k_ahb_reg(struct ath5k_hw *ah, u16 reg)
1652{
1653        /* On AR2315 and AR2317 the PCI clock domain registers
1654         * are outside of the WMAC register space */
1655        if (unlikely((reg >= 0x4000) && (reg < 0x5000) &&
1656            (ah->ah_mac_srev >= AR5K_SREV_AR2315_R6)))
1657                return AR5K_AR2315_PCI_BASE + reg;
1658
1659        return ah->iobase + reg;
1660}
1661
1662static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1663{
1664        return ioread32(ath5k_ahb_reg(ah, reg));
1665}
1666
1667static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1668{
1669        iowrite32(val, ath5k_ahb_reg(ah, reg));
1670}
1671
1672#else
1673
1674static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1675{
1676        return ioread32(ah->iobase + reg);
1677}
1678
1679static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1680{
1681        iowrite32(val, ah->iobase + reg);
1682}
1683
1684#endif
1685
1686static inline enum ath_bus_type ath5k_get_bus_type(struct ath5k_hw *ah)
1687{
1688        return ath5k_hw_common(ah)->bus_ops->ath_bus_type;
1689}
1690
1691static inline void ath5k_read_cachesize(struct ath_common *common, int *csz)
1692{
1693        common->bus_ops->read_cachesize(common, csz);
1694}
1695
1696static inline bool ath5k_hw_nvram_read(struct ath5k_hw *ah, u32 off, u16 *data)
1697{
1698        struct ath_common *common = ath5k_hw_common(ah);
1699        return common->bus_ops->eeprom_read(common, off, data);
1700}
1701
1702static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
1703{
1704        u32 retval = 0, bit, i;
1705
1706        for (i = 0; i < bits; i++) {
1707                bit = (val >> i) & 1;
1708                retval = (retval << 1) | bit;
1709        }
1710
1711        return retval;
1712}
1713
1714#endif
1715