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39#ifndef __CARL9170_SHARED_FWCMD_H
40#define __CARL9170_SHARED_FWCMD_H
41
42#define CARL9170_MAX_CMD_LEN 64
43#define CARL9170_MAX_CMD_PAYLOAD_LEN 60
44
45#define CARL9170FW_API_MIN_VER 1
46#define CARL9170FW_API_MAX_VER 1
47
48enum carl9170_cmd_oids {
49 CARL9170_CMD_RREG = 0x00,
50 CARL9170_CMD_WREG = 0x01,
51 CARL9170_CMD_ECHO = 0x02,
52 CARL9170_CMD_SWRST = 0x03,
53 CARL9170_CMD_REBOOT = 0x04,
54 CARL9170_CMD_BCN_CTRL = 0x05,
55 CARL9170_CMD_READ_TSF = 0x06,
56 CARL9170_CMD_RX_FILTER = 0x07,
57 CARL9170_CMD_WOL = 0x08,
58 CARL9170_CMD_TALLY = 0x09,
59
60
61 CARL9170_CMD_EKEY = 0x10,
62 CARL9170_CMD_DKEY = 0x11,
63
64
65 CARL9170_CMD_FREQUENCY = 0x20,
66 CARL9170_CMD_RF_INIT = 0x21,
67 CARL9170_CMD_SYNTH = 0x22,
68 CARL9170_CMD_FREQ_START = 0x23,
69 CARL9170_CMD_PSM = 0x24,
70
71
72 CARL9170_CMD_ASYNC_FLAG = 0x40,
73 CARL9170_CMD_WREG_ASYNC = (CARL9170_CMD_WREG |
74 CARL9170_CMD_ASYNC_FLAG),
75 CARL9170_CMD_REBOOT_ASYNC = (CARL9170_CMD_REBOOT |
76 CARL9170_CMD_ASYNC_FLAG),
77 CARL9170_CMD_BCN_CTRL_ASYNC = (CARL9170_CMD_BCN_CTRL |
78 CARL9170_CMD_ASYNC_FLAG),
79 CARL9170_CMD_PSM_ASYNC = (CARL9170_CMD_PSM |
80 CARL9170_CMD_ASYNC_FLAG),
81
82
83 CARL9170_RSP_FLAG = 0xc0,
84 CARL9170_RSP_PRETBTT = 0xc0,
85 CARL9170_RSP_TXCOMP = 0xc1,
86 CARL9170_RSP_BEACON_CONFIG = 0xc2,
87 CARL9170_RSP_ATIM = 0xc3,
88 CARL9170_RSP_WATCHDOG = 0xc6,
89 CARL9170_RSP_TEXT = 0xca,
90 CARL9170_RSP_HEXDUMP = 0xcc,
91 CARL9170_RSP_RADAR = 0xcd,
92 CARL9170_RSP_GPIO = 0xce,
93 CARL9170_RSP_BOOT = 0xcf,
94};
95
96struct carl9170_set_key_cmd {
97 __le16 user;
98 __le16 keyId;
99 __le16 type;
100 u8 macAddr[6];
101 u32 key[4];
102} __packed __aligned(4);
103#define CARL9170_SET_KEY_CMD_SIZE 28
104
105struct carl9170_disable_key_cmd {
106 __le16 user;
107 __le16 padding;
108} __packed __aligned(4);
109#define CARL9170_DISABLE_KEY_CMD_SIZE 4
110
111struct carl9170_u32_list {
112 u32 vals[0];
113} __packed;
114
115struct carl9170_reg_list {
116 __le32 regs[0];
117} __packed;
118
119struct carl9170_write_reg {
120 struct {
121 __le32 addr;
122 __le32 val;
123 } regs[0] __packed;
124} __packed;
125
126#define CARL9170FW_PHY_HT_ENABLE 0x4
127#define CARL9170FW_PHY_HT_DYN2040 0x8
128#define CARL9170FW_PHY_HT_EXT_CHAN_OFF 0x3
129#define CARL9170FW_PHY_HT_EXT_CHAN_OFF_S 2
130
131struct carl9170_rf_init {
132 __le32 freq;
133 u8 ht_settings;
134 u8 padding2[3];
135 __le32 delta_slope_coeff_exp;
136 __le32 delta_slope_coeff_man;
137 __le32 delta_slope_coeff_exp_shgi;
138 __le32 delta_slope_coeff_man_shgi;
139 __le32 finiteLoopCount;
140} __packed;
141#define CARL9170_RF_INIT_SIZE 28
142
143struct carl9170_rf_init_result {
144 __le32 ret;
145} __packed;
146#define CARL9170_RF_INIT_RESULT_SIZE 4
147
148#define CARL9170_PSM_SLEEP 0x1000
149#define CARL9170_PSM_SOFTWARE 0
150#define CARL9170_PSM_WAKE 0
151#define CARL9170_PSM_COUNTER 0xfff
152#define CARL9170_PSM_COUNTER_S 0
153
154struct carl9170_psm {
155 __le32 state;
156} __packed;
157#define CARL9170_PSM_SIZE 4
158
159
160
161
162
163
164
165
166
167struct carl9170_rx_filter_cmd {
168 __le32 rx_filter;
169} __packed;
170#define CARL9170_RX_FILTER_CMD_SIZE 4
171
172#define CARL9170_RX_FILTER_BAD 0x01
173#define CARL9170_RX_FILTER_OTHER_RA 0x02
174#define CARL9170_RX_FILTER_DECRY_FAIL 0x04
175#define CARL9170_RX_FILTER_CTL_OTHER 0x08
176#define CARL9170_RX_FILTER_CTL_PSPOLL 0x10
177#define CARL9170_RX_FILTER_CTL_BACKR 0x20
178#define CARL9170_RX_FILTER_MGMT 0x40
179#define CARL9170_RX_FILTER_DATA 0x80
180#define CARL9170_RX_FILTER_EVERYTHING (~0)
181
182struct carl9170_bcn_ctrl_cmd {
183 __le32 vif_id;
184 __le32 mode;
185 __le32 bcn_addr;
186 __le32 bcn_len;
187} __packed;
188#define CARL9170_BCN_CTRL_CMD_SIZE 16
189
190#define CARL9170_BCN_CTRL_DRAIN 0
191#define CARL9170_BCN_CTRL_CAB_TRIGGER 1
192
193struct carl9170_wol_cmd {
194 __le32 flags;
195 u8 mac[6];
196 u8 bssid[6];
197 __le32 null_interval;
198 __le32 free_for_use2;
199 __le32 mask;
200 u8 pattern[32];
201} __packed;
202
203#define CARL9170_WOL_CMD_SIZE 60
204
205#define CARL9170_WOL_DISCONNECT 1
206#define CARL9170_WOL_MAGIC_PKT 2
207
208struct carl9170_cmd_head {
209 union {
210 struct {
211 u8 len;
212 u8 cmd;
213 u8 seq;
214 u8 ext;
215 } __packed;
216
217 u32 hdr_data;
218 } __packed;
219} __packed;
220
221struct carl9170_cmd {
222 struct carl9170_cmd_head hdr;
223 union {
224 struct carl9170_set_key_cmd setkey;
225 struct carl9170_disable_key_cmd disablekey;
226 struct carl9170_u32_list echo;
227 struct carl9170_reg_list rreg;
228 struct carl9170_write_reg wreg;
229 struct carl9170_rf_init rf_init;
230 struct carl9170_psm psm;
231 struct carl9170_wol_cmd wol;
232 struct carl9170_bcn_ctrl_cmd bcn_ctrl;
233 struct carl9170_rx_filter_cmd rx_filter;
234 u8 data[CARL9170_MAX_CMD_PAYLOAD_LEN];
235 } __packed;
236} __packed __aligned(4);
237
238#define CARL9170_TX_STATUS_QUEUE 3
239#define CARL9170_TX_STATUS_QUEUE_S 0
240#define CARL9170_TX_STATUS_RIX_S 2
241#define CARL9170_TX_STATUS_RIX (3 << CARL9170_TX_STATUS_RIX_S)
242#define CARL9170_TX_STATUS_TRIES_S 4
243#define CARL9170_TX_STATUS_TRIES (7 << CARL9170_TX_STATUS_TRIES_S)
244#define CARL9170_TX_STATUS_SUCCESS 0x80
245
246#ifdef __CARL9170FW__
247
248
249
250
251
252struct carl9170_tx_status {
253
254
255
256
257 u8 cookie;
258 u8 queue:2;
259 u8 rix:2;
260 u8 tries:3;
261 u8 success:1;
262} __packed;
263#endif
264
265struct _carl9170_tx_status {
266
267
268
269
270 u8 cookie;
271 u8 info;
272} __packed;
273#define CARL9170_TX_STATUS_SIZE 2
274
275#define CARL9170_RSP_TX_STATUS_NUM (CARL9170_MAX_CMD_PAYLOAD_LEN / \
276 sizeof(struct _carl9170_tx_status))
277
278#define CARL9170_TX_MAX_RATE_TRIES 7
279
280#define CARL9170_TX_MAX_RATES 4
281#define CARL9170_TX_MAX_RETRY_RATES (CARL9170_TX_MAX_RATES - 1)
282#define CARL9170_ERR_MAGIC "ERR:"
283#define CARL9170_BUG_MAGIC "BUG:"
284
285struct carl9170_gpio {
286 __le32 gpio;
287} __packed;
288#define CARL9170_GPIO_SIZE 4
289
290struct carl9170_tsf_rsp {
291 union {
292 __le32 tsf[2];
293 __le64 tsf_64;
294 } __packed;
295} __packed;
296#define CARL9170_TSF_RSP_SIZE 8
297
298struct carl9170_tally_rsp {
299 __le32 active;
300 __le32 cca;
301 __le32 tx_time;
302 __le32 rx_total;
303 __le32 rx_overrun;
304 __le32 tick;
305} __packed;
306
307struct carl9170_rsp {
308 struct carl9170_cmd_head hdr;
309
310 union {
311 struct carl9170_rf_init_result rf_init_res;
312 struct carl9170_u32_list rreg_res;
313 struct carl9170_u32_list echo;
314#ifdef __CARL9170FW__
315 struct carl9170_tx_status tx_status[0];
316#endif
317 struct _carl9170_tx_status _tx_status[0];
318 struct carl9170_gpio gpio;
319 struct carl9170_tsf_rsp tsf;
320 struct carl9170_psm psm;
321 struct carl9170_tally_rsp tally;
322 u8 data[CARL9170_MAX_CMD_PAYLOAD_LEN];
323 } __packed;
324} __packed __aligned(4);
325
326#endif
327