1#ifndef B43_H_
2#define B43_H_
3
4#include <linux/kernel.h>
5#include <linux/spinlock.h>
6#include <linux/interrupt.h>
7#include <linux/hw_random.h>
8#include <linux/bcma/bcma.h>
9#include <linux/ssb/ssb.h>
10#include <linux/completion.h>
11#include <net/mac80211.h>
12
13#include "debugfs.h"
14#include "leds.h"
15#include "rfkill.h"
16#include "bus.h"
17#include "lo.h"
18#include "phy_common.h"
19
20
21#ifdef CONFIG_B43_DEBUG
22# define B43_DEBUG 1
23#else
24# define B43_DEBUG 0
25#endif
26
27
28#define B43_MMIO_DMA0_REASON 0x20
29#define B43_MMIO_DMA0_IRQ_MASK 0x24
30#define B43_MMIO_DMA1_REASON 0x28
31#define B43_MMIO_DMA1_IRQ_MASK 0x2C
32#define B43_MMIO_DMA2_REASON 0x30
33#define B43_MMIO_DMA2_IRQ_MASK 0x34
34#define B43_MMIO_DMA3_REASON 0x38
35#define B43_MMIO_DMA3_IRQ_MASK 0x3C
36#define B43_MMIO_DMA4_REASON 0x40
37#define B43_MMIO_DMA4_IRQ_MASK 0x44
38#define B43_MMIO_DMA5_REASON 0x48
39#define B43_MMIO_DMA5_IRQ_MASK 0x4C
40#define B43_MMIO_MACCTL 0x120
41#define B43_MMIO_MACCMD 0x124
42#define B43_MMIO_GEN_IRQ_REASON 0x128
43#define B43_MMIO_GEN_IRQ_MASK 0x12C
44#define B43_MMIO_RAM_CONTROL 0x130
45#define B43_MMIO_RAM_DATA 0x134
46#define B43_MMIO_PS_STATUS 0x140
47#define B43_MMIO_RADIO_HWENABLED_HI 0x158
48#define B43_MMIO_SHM_CONTROL 0x160
49#define B43_MMIO_SHM_DATA 0x164
50#define B43_MMIO_SHM_DATA_UNALIGNED 0x166
51#define B43_MMIO_XMITSTAT_0 0x170
52#define B43_MMIO_XMITSTAT_1 0x174
53#define B43_MMIO_REV3PLUS_TSF_LOW 0x180
54#define B43_MMIO_REV3PLUS_TSF_HIGH 0x184
55#define B43_MMIO_TSF_CFP_REP 0x188
56#define B43_MMIO_TSF_CFP_START 0x18C
57#define B43_MMIO_TSF_CFP_MAXDUR 0x190
58
59
60#define B43_MMIO_DMA32_BASE0 0x200
61#define B43_MMIO_DMA32_BASE1 0x220
62#define B43_MMIO_DMA32_BASE2 0x240
63#define B43_MMIO_DMA32_BASE3 0x260
64#define B43_MMIO_DMA32_BASE4 0x280
65#define B43_MMIO_DMA32_BASE5 0x2A0
66
67#define B43_MMIO_DMA64_BASE0 0x200
68#define B43_MMIO_DMA64_BASE1 0x240
69#define B43_MMIO_DMA64_BASE2 0x280
70#define B43_MMIO_DMA64_BASE3 0x2C0
71#define B43_MMIO_DMA64_BASE4 0x300
72#define B43_MMIO_DMA64_BASE5 0x340
73
74
75#define B43_MMIO_PIO_BASE0 0x300
76#define B43_MMIO_PIO_BASE1 0x310
77#define B43_MMIO_PIO_BASE2 0x320
78#define B43_MMIO_PIO_BASE3 0x330
79#define B43_MMIO_PIO_BASE4 0x340
80#define B43_MMIO_PIO_BASE5 0x350
81#define B43_MMIO_PIO_BASE6 0x360
82#define B43_MMIO_PIO_BASE7 0x370
83
84#define B43_MMIO_PIO11_BASE0 0x200
85#define B43_MMIO_PIO11_BASE1 0x240
86#define B43_MMIO_PIO11_BASE2 0x280
87#define B43_MMIO_PIO11_BASE3 0x2C0
88#define B43_MMIO_PIO11_BASE4 0x300
89#define B43_MMIO_PIO11_BASE5 0x340
90
91#define B43_MMIO_RADIO24_CONTROL 0x3D8
92#define B43_MMIO_RADIO24_DATA 0x3DA
93#define B43_MMIO_PHY_VER 0x3E0
94#define B43_MMIO_PHY_RADIO 0x3E2
95#define B43_MMIO_PHY0 0x3E6
96#define B43_MMIO_ANTENNA 0x3E8
97#define B43_MMIO_CHANNEL 0x3F0
98#define B43_MMIO_CHANNEL_EXT 0x3F4
99#define B43_MMIO_RADIO_CONTROL 0x3F6
100#define B43_MMIO_RADIO_DATA_HIGH 0x3F8
101#define B43_MMIO_RADIO_DATA_LOW 0x3FA
102#define B43_MMIO_PHY_CONTROL 0x3FC
103#define B43_MMIO_PHY_DATA 0x3FE
104#define B43_MMIO_MACFILTER_CONTROL 0x420
105#define B43_MMIO_MACFILTER_DATA 0x422
106#define B43_MMIO_RCMTA_COUNT 0x43C
107#define B43_MMIO_PSM_PHY_HDR 0x492
108#define B43_MMIO_RADIO_HWENABLED_LO 0x49A
109#define B43_MMIO_GPIO_CONTROL 0x49C
110#define B43_MMIO_GPIO_MASK 0x49E
111#define B43_MMIO_TXE0_CTL 0x500
112#define B43_MMIO_TXE0_AUX 0x502
113#define B43_MMIO_TXE0_TS_LOC 0x504
114#define B43_MMIO_TXE0_TIME_OUT 0x506
115#define B43_MMIO_TXE0_WM_0 0x508
116#define B43_MMIO_TXE0_WM_1 0x50A
117#define B43_MMIO_TXE0_PHYCTL 0x50C
118#define B43_MMIO_TXE0_STATUS 0x50E
119#define B43_MMIO_TXE0_MMPLCP0 0x510
120#define B43_MMIO_TXE0_MMPLCP1 0x512
121#define B43_MMIO_TXE0_PHYCTL1 0x514
122#define B43_MMIO_XMTFIFODEF 0x520
123#define B43_MMIO_XMTFIFO_FRAME_CNT 0x522
124#define B43_MMIO_XMTFIFO_BYTE_CNT 0x524
125#define B43_MMIO_XMTFIFO_HEAD 0x526
126#define B43_MMIO_XMTFIFO_RD_PTR 0x528
127#define B43_MMIO_XMTFIFO_WR_PTR 0x52A
128#define B43_MMIO_XMTFIFODEF1 0x52C
129#define B43_MMIO_XMTFIFOCMD 0x540
130#define B43_MMIO_XMTFIFOFLUSH 0x542
131#define B43_MMIO_XMTFIFOTHRESH 0x544
132#define B43_MMIO_XMTFIFORDY 0x546
133#define B43_MMIO_XMTFIFOPRIRDY 0x548
134#define B43_MMIO_XMTFIFORQPRI 0x54A
135#define B43_MMIO_XMTTPLATETXPTR 0x54C
136#define B43_MMIO_XMTTPLATEPTR 0x550
137#define B43_MMIO_SMPL_CLCT_STRPTR 0x552
138#define B43_MMIO_SMPL_CLCT_STPPTR 0x554
139#define B43_MMIO_SMPL_CLCT_CURPTR 0x556
140#define B43_MMIO_XMTTPLATEDATALO 0x560
141#define B43_MMIO_XMTTPLATEDATAHI 0x562
142#define B43_MMIO_XMTSEL 0x568
143#define B43_MMIO_XMTTXCNT 0x56A
144#define B43_MMIO_XMTTXSHMADDR 0x56C
145#define B43_MMIO_TSF_CFP_START_LOW 0x604
146#define B43_MMIO_TSF_CFP_START_HIGH 0x606
147#define B43_MMIO_TSF_CFP_PRETBTT 0x612
148#define B43_MMIO_TSF_CLK_FRAC_LOW 0x62E
149#define B43_MMIO_TSF_CLK_FRAC_HIGH 0x630
150#define B43_MMIO_TSF_0 0x632
151#define B43_MMIO_TSF_1 0x634
152#define B43_MMIO_TSF_2 0x636
153#define B43_MMIO_TSF_3 0x638
154#define B43_MMIO_RNG 0x65A
155#define B43_MMIO_IFSSLOT 0x684
156#define B43_MMIO_IFSCTL 0x688
157#define B43_MMIO_IFSSTAT 0x690
158#define B43_MMIO_IFSMEDBUSYCTL 0x692
159#define B43_MMIO_IFTXDUR 0x694
160#define B43_MMIO_IFSCTL_USE_EDCF 0x0004
161#define B43_MMIO_POWERUP_DELAY 0x6A8
162#define B43_MMIO_BTCOEX_CTL 0x6B4
163#define B43_MMIO_BTCOEX_STAT 0x6B6
164#define B43_MMIO_BTCOEX_TXCTL 0x6B8
165#define B43_MMIO_WEPCTL 0x7C0
166
167
168#define B43_BFL_BTCOEXIST 0x0001
169#define B43_BFL_PACTRL 0x0002
170#define B43_BFL_AIRLINEMODE 0x0004
171#define B43_BFL_RSSI 0x0008
172#define B43_BFL_ENETSPI 0x0010
173#define B43_BFL_XTAL_NOSLOW 0x0020
174#define B43_BFL_CCKHIPWR 0x0040
175#define B43_BFL_ENETADM 0x0080
176#define B43_BFL_ENETVLAN 0x0100
177#define B43_BFL_AFTERBURNER 0x0200
178#define B43_BFL_NOPCI 0x0400
179#define B43_BFL_FEM 0x0800
180#define B43_BFL_EXTLNA 0x1000
181#define B43_BFL_HGPA 0x2000
182#define B43_BFL_BTCMOD 0x4000
183#define B43_BFL_ALTIQ 0x8000
184
185
186#define B43_BFH_NOPA 0x0001
187#define B43_BFH_RSSIINV 0x0002
188#define B43_BFH_PAREF 0x0004
189#define B43_BFH_3TSWITCH 0x0008
190
191#define B43_BFH_PHASESHIFT 0x0010
192#define B43_BFH_BUCKBOOST 0x0020
193#define B43_BFH_FEM_BT 0x0040
194
195#define B43_BFH_NOCBUCK 0x0080
196#define B43_BFH_PALDO 0x0200
197#define B43_BFH_EXTLNA_5GHZ 0x1000
198
199
200#define B43_BFL2_RXBB_INT_REG_DIS 0x0001
201#define B43_BFL2_APLL_WAR 0x0002
202#define B43_BFL2_TXPWRCTRL_EN 0x0004
203#define B43_BFL2_2X4_DIV 0x0008
204#define B43_BFL2_5G_PWRGAIN 0x0010
205#define B43_BFL2_PCIEWAR_OVR 0x0020
206#define B43_BFL2_CAESERS_BRD 0x0040
207#define B43_BFL2_BTC3WIRE 0x0080
208#define B43_BFL2_SKWRKFEM_BRD 0x0100
209#define B43_BFL2_SPUR_WAR 0x0200
210#define B43_BFL2_GPLL_WAR 0x0400
211#define B43_BFL2_SINGLEANT_CCK 0x1000
212#define B43_BFL2_2G_SPUR_WAR 0x2000
213
214
215#define B43_BFH2_GPLL_WAR2 0x0001
216#define B43_BFH2_IPALVLSHIFT_3P3 0x0002
217#define B43_BFH2_INTERNDET_TXIQCAL 0x0004
218#define B43_BFH2_XTALBUFOUTEN 0x0008
219
220
221#define B43_GPIO_CONTROL 0x6c
222
223
224enum {
225 B43_SHM_UCODE,
226 B43_SHM_SHARED,
227 B43_SHM_SCRATCH,
228 B43_SHM_HW,
229 B43_SHM_RCMTA,
230};
231
232#define B43_SHM_AUTOINC_R 0x0200
233#define B43_SHM_AUTOINC_W 0x0100
234#define B43_SHM_AUTOINC_RW (B43_SHM_AUTOINC_R | \
235 B43_SHM_AUTOINC_W)
236
237
238#define B43_SHM_SH_WLCOREREV 0x0016
239#define B43_SHM_SH_PCTLWDPOS 0x0008
240#define B43_SHM_SH_RXPADOFF 0x0034
241#define B43_SHM_SH_FWCAPA 0x0042
242#define B43_SHM_SH_PHYVER 0x0050
243#define B43_SHM_SH_PHYTYPE 0x0052
244#define B43_SHM_SH_ANTSWAP 0x005C
245#define B43_SHM_SH_HOSTF1 0x005E
246#define B43_SHM_SH_HOSTF2 0x0060
247#define B43_SHM_SH_HOSTF3 0x0062
248#define B43_SHM_SH_RFATT 0x0064
249#define B43_SHM_SH_RADAR 0x0066
250#define B43_SHM_SH_PHYTXNOI 0x006E
251#define B43_SHM_SH_RFRXSP1 0x0072
252#define B43_SHM_SH_HOSTF4 0x0078
253#define B43_SHM_SH_CHAN 0x00A0
254#define B43_SHM_SH_CHAN_5GHZ 0x0100
255#define B43_SHM_SH_CHAN_40MHZ 0x0200
256#define B43_SHM_SH_HOSTF5 0x00D4
257#define B43_SHM_SH_BCMCFIFOID 0x0108
258
259#define B43_SHM_SH_TSSI_CCK 0x0058
260#define B43_SHM_SH_TSSI_OFDM_A 0x0068
261#define B43_SHM_SH_TSSI_OFDM_G 0x0070
262#define B43_TSSI_MAX 0x7F
263
264#define B43_SHM_SH_SIZE01 0x0098
265#define B43_SHM_SH_SIZE23 0x009A
266#define B43_SHM_SH_SIZE45 0x009C
267#define B43_SHM_SH_SIZE67 0x009E
268
269#define B43_SHM_SH_JSSI0 0x0088
270#define B43_SHM_SH_JSSI1 0x008A
271#define B43_SHM_SH_JSSIAUX 0x008C
272
273#define B43_SHM_SH_DEFAULTIV 0x003C
274#define B43_SHM_SH_NRRXTRANS 0x003E
275#define B43_SHM_SH_KTP 0x0056
276#define B43_SHM_SH_TKIPTSCTTAK 0x0318
277#define B43_SHM_SH_KEYIDXBLOCK 0x05D4
278#define B43_SHM_SH_PSM 0x05F4
279
280#define B43_SHM_SH_EDCFSTAT 0x000E
281#define B43_SHM_SH_TXFCUR 0x0030
282#define B43_SHM_SH_EDCFQ 0x0240
283
284#define B43_SHM_SH_SLOTT 0x0010
285#define B43_SHM_SH_DTIMPER 0x0012
286#define B43_SHM_SH_NOSLPZNATDTIM 0x004C
287
288#define B43_SHM_SH_BT_BASE0 0x0068
289#define B43_SHM_SH_BTL0 0x0018
290#define B43_SHM_SH_BT_BASE1 0x0468
291#define B43_SHM_SH_BTL1 0x001A
292#define B43_SHM_SH_BTSFOFF 0x001C
293#define B43_SHM_SH_TIMBPOS 0x001E
294#define B43_SHM_SH_DTIMP 0x0012
295#define B43_SHM_SH_MCASTCOOKIE 0x00A8
296#define B43_SHM_SH_SFFBLIM 0x0044
297#define B43_SHM_SH_LFFBLIM 0x0046
298#define B43_SHM_SH_BEACPHYCTL 0x0054
299#define B43_SHM_SH_EXTNPHYCTL 0x00B0
300
301#define B43_SHM_SH_ACKCTSPHYCTL 0x0022
302
303#define B43_SHM_SH_PRSSID 0x0160
304#define B43_SHM_SH_PRSSIDLEN 0x0048
305#define B43_SHM_SH_PRTLEN 0x004A
306#define B43_SHM_SH_PRMAXTIME 0x0074
307#define B43_SHM_SH_PRPHYCTL 0x0188
308
309#define B43_SHM_SH_OFDMDIRECT 0x01C0
310#define B43_SHM_SH_OFDMBASIC 0x01E0
311#define B43_SHM_SH_CCKDIRECT 0x0200
312#define B43_SHM_SH_CCKBASIC 0x0220
313
314#define B43_SHM_SH_UCODEREV 0x0000
315#define B43_SHM_SH_UCODEPATCH 0x0002
316#define B43_SHM_SH_UCODEDATE 0x0004
317#define B43_SHM_SH_UCODETIME 0x0006
318#define B43_SHM_SH_UCODESTAT 0x0040
319#define B43_SHM_SH_UCODESTAT_INVALID 0
320#define B43_SHM_SH_UCODESTAT_INIT 1
321#define B43_SHM_SH_UCODESTAT_ACTIVE 2
322#define B43_SHM_SH_UCODESTAT_SUSP 3
323#define B43_SHM_SH_UCODESTAT_SLEEP 4
324#define B43_SHM_SH_MAXBFRAMES 0x0080
325#define B43_SHM_SH_SPUWKUP 0x0094
326#define B43_SHM_SH_PRETBTT 0x0096
327
328#define B43_SHM_SH_NPHY_TXIQW0 0x0700
329#define B43_SHM_SH_NPHY_TXIQW1 0x0702
330#define B43_SHM_SH_NPHY_TXIQW2 0x0704
331#define B43_SHM_SH_NPHY_TXIQW3 0x0706
332
333#define B43_SHM_SH_NPHY_TXPWR_INDX0 0x0708
334#define B43_SHM_SH_NPHY_TXPWR_INDX1 0x070E
335
336
337#define B43_SHM_SC_MINCONT 0x0003
338#define B43_SHM_SC_MAXCONT 0x0004
339#define B43_SHM_SC_CURCONT 0x0005
340#define B43_SHM_SC_SRLIMIT 0x0006
341#define B43_SHM_SC_LRLIMIT 0x0007
342#define B43_SHM_SC_DTIMC 0x0008
343#define B43_SHM_SC_BTL0LEN 0x0015
344#define B43_SHM_SC_BTL1LEN 0x0016
345#define B43_SHM_SC_SCFB 0x0017
346#define B43_SHM_SC_LCFB 0x0018
347
348
349#define B43_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
350#define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
351
352
353#define B43_HF_ANTDIVHELP 0x000000000001ULL
354#define B43_HF_SYMW 0x000000000002ULL
355#define B43_HF_RXPULLW 0x000000000004ULL
356#define B43_HF_CCKBOOST 0x000000000008ULL
357#define B43_HF_BTCOEX 0x000000000010ULL
358#define B43_HF_GDCW 0x000000000020ULL
359#define B43_HF_OFDMPABOOST 0x000000000040ULL
360#define B43_HF_ACPR 0x000000000080ULL
361#define B43_HF_EDCF 0x000000000100ULL
362#define B43_HF_TSSIRPSMW 0x000000000200ULL
363#define B43_HF_20IN40IQW 0x000000000200ULL
364#define B43_HF_DSCRQ 0x000000000400ULL
365#define B43_HF_ACIW 0x000000000800ULL
366#define B43_HF_2060W 0x000000001000ULL
367#define B43_HF_RADARW 0x000000002000ULL
368#define B43_HF_USEDEFKEYS 0x000000004000ULL
369#define B43_HF_AFTERBURNER 0x000000008000ULL
370#define B43_HF_BT4PRIOCOEX 0x000000010000ULL
371#define B43_HF_FWKUP 0x000000020000ULL
372#define B43_HF_VCORECALC 0x000000040000ULL
373#define B43_HF_PCISCW 0x000000080000ULL
374#define B43_HF_4318TSSI 0x000000200000ULL
375#define B43_HF_FBCMCFIFO 0x000000400000ULL
376#define B43_HF_HWPCTL 0x000000800000ULL
377#define B43_HF_BTCOEXALT 0x000001000000ULL
378#define B43_HF_TXBTCHECK 0x000002000000ULL
379#define B43_HF_SKCFPUP 0x000004000000ULL
380#define B43_HF_N40W 0x000008000000ULL
381#define B43_HF_ANTSEL 0x000020000000ULL
382#define B43_HF_BT3COEXT 0x000020000000ULL
383#define B43_HF_BTCANT 0x000040000000ULL
384#define B43_HF_ANTSELEN 0x000100000000ULL
385#define B43_HF_ANTSELMODE 0x000200000000ULL
386#define B43_HF_MLADVW 0x001000000000ULL
387#define B43_HF_PR45960W 0x080000000000ULL
388
389
390#define B43_FWCAPA_HWCRYPTO 0x0001
391#define B43_FWCAPA_QOS 0x0002
392
393
394#define B43_MACFILTER_SELF 0x0000
395#define B43_MACFILTER_BSSID 0x0003
396
397
398#define B43_PCTL_IN 0xB0
399#define B43_PCTL_OUT 0xB4
400#define B43_PCTL_OUTENABLE 0xB8
401#define B43_PCTL_XTAL_POWERUP 0x40
402#define B43_PCTL_PLL_POWERDOWN 0x80
403
404
405#define B43_PCTL_CLK_FAST 0x00
406#define B43_PCTL_CLK_SLOW 0x01
407#define B43_PCTL_CLK_DYNAMIC 0x02
408
409#define B43_PCTL_FORCE_SLOW 0x0800
410#define B43_PCTL_FORCE_PLL 0x1000
411#define B43_PCTL_DYN_XTAL 0x2000
412
413
414#define B43_PHYTYPE_A 0x00
415#define B43_PHYTYPE_B 0x01
416#define B43_PHYTYPE_G 0x02
417#define B43_PHYTYPE_N 0x04
418#define B43_PHYTYPE_LP 0x05
419#define B43_PHYTYPE_SSLPN 0x06
420#define B43_PHYTYPE_HT 0x07
421#define B43_PHYTYPE_LCN 0x08
422#define B43_PHYTYPE_LCNXN 0x09
423#define B43_PHYTYPE_LCN40 0x0a
424#define B43_PHYTYPE_AC 0x0b
425
426
427#define B43_PHY_ILT_A_CTRL 0x0072
428#define B43_PHY_ILT_A_DATA1 0x0073
429#define B43_PHY_ILT_A_DATA2 0x0074
430#define B43_PHY_G_LO_CONTROL 0x0810
431#define B43_PHY_ILT_G_CTRL 0x0472
432#define B43_PHY_ILT_G_DATA1 0x0473
433#define B43_PHY_ILT_G_DATA2 0x0474
434#define B43_PHY_A_PCTL 0x007B
435#define B43_PHY_G_PCTL 0x0029
436#define B43_PHY_A_CRS 0x0029
437#define B43_PHY_RADIO_BITFIELD 0x0401
438#define B43_PHY_G_CRS 0x0429
439#define B43_PHY_NRSSILT_CTRL 0x0803
440#define B43_PHY_NRSSILT_DATA 0x0804
441
442
443#define B43_RADIOCTL_ID 0x01
444
445
446#define B43_MACCTL_ENABLED 0x00000001
447#define B43_MACCTL_PSM_RUN 0x00000002
448#define B43_MACCTL_PSM_JMP0 0x00000004
449#define B43_MACCTL_SHM_ENABLED 0x00000100
450#define B43_MACCTL_SHM_UPPER 0x00000200
451#define B43_MACCTL_IHR_ENABLED 0x00000400
452#define B43_MACCTL_PSM_DBG 0x00002000
453#define B43_MACCTL_GPOUTSMSK 0x0000C000
454#define B43_MACCTL_BE 0x00010000
455#define B43_MACCTL_INFRA 0x00020000
456#define B43_MACCTL_AP 0x00040000
457#define B43_MACCTL_RADIOLOCK 0x00080000
458#define B43_MACCTL_BEACPROMISC 0x00100000
459#define B43_MACCTL_KEEP_BADPLCP 0x00200000
460#define B43_MACCTL_KEEP_CTL 0x00400000
461#define B43_MACCTL_KEEP_BAD 0x00800000
462#define B43_MACCTL_PROMISC 0x01000000
463#define B43_MACCTL_HWPS 0x02000000
464#define B43_MACCTL_AWAKE 0x04000000
465#define B43_MACCTL_CLOSEDNET 0x08000000
466#define B43_MACCTL_TBTTHOLD 0x10000000
467#define B43_MACCTL_DISCTXSTAT 0x20000000
468#define B43_MACCTL_DISCPMQ 0x40000000
469#define B43_MACCTL_GMODE 0x80000000
470
471
472#define B43_MACCMD_BEACON0_VALID 0x00000001
473#define B43_MACCMD_BEACON1_VALID 0x00000002
474#define B43_MACCMD_DFQ_VALID 0x00000004
475#define B43_MACCMD_CCA 0x00000008
476#define B43_MACCMD_BGNOISE 0x00000010
477
478
479#define B43_BCMA_CLKCTLST_80211_PLL_REQ 0x00000100
480#define B43_BCMA_CLKCTLST_PHY_PLL_REQ 0x00000200
481#define B43_BCMA_CLKCTLST_80211_PLL_ST 0x01000000
482#define B43_BCMA_CLKCTLST_PHY_PLL_ST 0x02000000
483
484
485#define B43_BCMA_IOCTL_PHY_CLKEN 0x00000004
486#define B43_BCMA_IOCTL_PHY_RESET 0x00000008
487#define B43_BCMA_IOCTL_MACPHYCLKEN 0x00000010
488#define B43_BCMA_IOCTL_PLLREFSEL 0x00000020
489#define B43_BCMA_IOCTL_PHY_BW 0x000000C0
490#define B43_BCMA_IOCTL_PHY_BW_10MHZ 0x00000000
491#define B43_BCMA_IOCTL_PHY_BW_20MHZ 0x00000040
492#define B43_BCMA_IOCTL_PHY_BW_40MHZ 0x00000080
493#define B43_BCMA_IOCTL_GMODE 0x00002000
494
495
496#define B43_BCMA_IOST_2G_PHY 0x00000001
497#define B43_BCMA_IOST_5G_PHY 0x00000002
498#define B43_BCMA_IOST_FASTCLKA 0x00000004
499#define B43_BCMA_IOST_DUALB_PHY 0x00000008
500
501
502#define B43_TMSLOW_GMODE 0x20000000
503#define B43_TMSLOW_PHY_BANDWIDTH 0x00C00000
504#define B43_TMSLOW_PHY_BANDWIDTH_10MHZ 0x00000000
505#define B43_TMSLOW_PHY_BANDWIDTH_20MHZ 0x00400000
506#define B43_TMSLOW_PHY_BANDWIDTH_40MHZ 0x00800000
507#define B43_TMSLOW_PLLREFSEL 0x00200000
508#define B43_TMSLOW_MACPHYCLKEN 0x00100000
509#define B43_TMSLOW_PHYRESET 0x00080000
510#define B43_TMSLOW_PHYCLKEN 0x00040000
511
512
513#define B43_TMSHIGH_DUALBAND_PHY 0x00080000
514#define B43_TMSHIGH_FCLOCK 0x00040000
515#define B43_TMSHIGH_HAVE_5GHZ_PHY 0x00020000
516#define B43_TMSHIGH_HAVE_2GHZ_PHY 0x00010000
517
518
519#define B43_IRQ_MAC_SUSPENDED 0x00000001
520#define B43_IRQ_BEACON 0x00000002
521#define B43_IRQ_TBTT_INDI 0x00000004
522#define B43_IRQ_BEACON_TX_OK 0x00000008
523#define B43_IRQ_BEACON_CANCEL 0x00000010
524#define B43_IRQ_ATIM_END 0x00000020
525#define B43_IRQ_PMQ 0x00000040
526#define B43_IRQ_PIO_WORKAROUND 0x00000100
527#define B43_IRQ_MAC_TXERR 0x00000200
528#define B43_IRQ_PHY_TXERR 0x00000800
529#define B43_IRQ_PMEVENT 0x00001000
530#define B43_IRQ_TIMER0 0x00002000
531#define B43_IRQ_TIMER1 0x00004000
532#define B43_IRQ_DMA 0x00008000
533#define B43_IRQ_TXFIFO_FLUSH_OK 0x00010000
534#define B43_IRQ_CCA_MEASURE_OK 0x00020000
535#define B43_IRQ_NOISESAMPLE_OK 0x00040000
536#define B43_IRQ_UCODE_DEBUG 0x08000000
537#define B43_IRQ_RFKILL 0x10000000
538#define B43_IRQ_TX_OK 0x20000000
539#define B43_IRQ_PHY_G_CHANGED 0x40000000
540#define B43_IRQ_TIMEOUT 0x80000000
541
542#define B43_IRQ_ALL 0xFFFFFFFF
543#define B43_IRQ_MASKTEMPLATE (B43_IRQ_TBTT_INDI | \
544 B43_IRQ_ATIM_END | \
545 B43_IRQ_PMQ | \
546 B43_IRQ_MAC_TXERR | \
547 B43_IRQ_PHY_TXERR | \
548 B43_IRQ_DMA | \
549 B43_IRQ_TXFIFO_FLUSH_OK | \
550 B43_IRQ_NOISESAMPLE_OK | \
551 B43_IRQ_UCODE_DEBUG | \
552 B43_IRQ_RFKILL | \
553 B43_IRQ_TX_OK)
554
555
556#define B43_DEBUGIRQ_REASON_REG 63
557
558#define B43_DEBUGIRQ_PANIC 0
559#define B43_DEBUGIRQ_DUMP_SHM 1
560#define B43_DEBUGIRQ_DUMP_REGS 2
561#define B43_DEBUGIRQ_MARKER 3
562#define B43_DEBUGIRQ_ACK 0xFFFF
563
564
565#define B43_MARKER_ID_REG 2
566#define B43_MARKER_LINE_REG 3
567
568
569#define B43_FWPANIC_REASON_REG 3
570
571#define B43_FWPANIC_DIE 0
572#define B43_FWPANIC_RESTART 1
573
574
575#define B43_WATCHDOG_REG 1
576
577
578
579
580#define B43_CCK_RATE_1MB 0x02
581#define B43_CCK_RATE_2MB 0x04
582#define B43_CCK_RATE_5MB 0x0B
583#define B43_CCK_RATE_11MB 0x16
584#define B43_OFDM_RATE_6MB 0x0C
585#define B43_OFDM_RATE_9MB 0x12
586#define B43_OFDM_RATE_12MB 0x18
587#define B43_OFDM_RATE_18MB 0x24
588#define B43_OFDM_RATE_24MB 0x30
589#define B43_OFDM_RATE_36MB 0x48
590#define B43_OFDM_RATE_48MB 0x60
591#define B43_OFDM_RATE_54MB 0x6C
592
593#define B43_RATE_TO_BASE100KBPS(rate) (((rate) * 10) / 2)
594
595#define B43_DEFAULT_SHORT_RETRY_LIMIT 7
596#define B43_DEFAULT_LONG_RETRY_LIMIT 4
597
598#define B43_PHY_TX_BADNESS_LIMIT 1000
599
600
601#define B43_SEC_KEYSIZE 16
602
603#define B43_NR_GROUP_KEYS 4
604
605#define B43_NR_PAIRWISE_KEYS 50
606
607enum {
608 B43_SEC_ALGO_NONE = 0,
609 B43_SEC_ALGO_WEP40,
610 B43_SEC_ALGO_TKIP,
611 B43_SEC_ALGO_AES,
612 B43_SEC_ALGO_WEP104,
613 B43_SEC_ALGO_AES_LEGACY,
614};
615
616struct b43_dmaring;
617
618
619#define B43_FW_TYPE_UCODE 'u'
620#define B43_FW_TYPE_PCM 'p'
621#define B43_FW_TYPE_IV 'i'
622struct b43_fw_header {
623
624 u8 type;
625
626 u8 ver;
627 u8 __padding[2];
628
629
630 __be32 size;
631} __packed;
632
633
634#define B43_IV_OFFSET_MASK 0x7FFF
635#define B43_IV_32BIT 0x8000
636struct b43_iv {
637 __be16 offset_size;
638 union {
639 __be16 d16;
640 __be32 d32;
641 } data __packed;
642} __packed;
643
644
645
646struct b43_dma {
647 struct b43_dmaring *tx_ring_AC_BK;
648 struct b43_dmaring *tx_ring_AC_BE;
649 struct b43_dmaring *tx_ring_AC_VI;
650 struct b43_dmaring *tx_ring_AC_VO;
651 struct b43_dmaring *tx_ring_mcast;
652
653 struct b43_dmaring *rx_ring;
654
655 u32 translation;
656 bool translation_in_low;
657 bool parity;
658};
659
660struct b43_pio_txqueue;
661struct b43_pio_rxqueue;
662
663
664struct b43_pio {
665 struct b43_pio_txqueue *tx_queue_AC_BK;
666 struct b43_pio_txqueue *tx_queue_AC_BE;
667 struct b43_pio_txqueue *tx_queue_AC_VI;
668 struct b43_pio_txqueue *tx_queue_AC_VO;
669 struct b43_pio_txqueue *tx_queue_mcast;
670
671 struct b43_pio_rxqueue *rx_queue;
672};
673
674
675struct b43_noise_calculation {
676 bool calculation_running;
677 u8 nr_samples;
678 s8 samples[8][4];
679};
680
681struct b43_stats {
682 u8 link_noise;
683};
684
685struct b43_key {
686
687
688
689 struct ieee80211_key_conf *keyconf;
690 u8 algorithm;
691};
692
693
694#define B43_QOS_QUEUE_NUM 4
695#define B43_QOS_PARAMS(queue) (B43_SHM_SH_EDCFQ + \
696 (B43_NR_QOSPARAMS * sizeof(u16) * (queue)))
697#define B43_QOS_BACKGROUND B43_QOS_PARAMS(0)
698#define B43_QOS_BESTEFFORT B43_QOS_PARAMS(1)
699#define B43_QOS_VIDEO B43_QOS_PARAMS(2)
700#define B43_QOS_VOICE B43_QOS_PARAMS(3)
701
702
703#define B43_NR_QOSPARAMS 16
704enum {
705 B43_QOSPARAM_TXOP = 0,
706 B43_QOSPARAM_CWMIN,
707 B43_QOSPARAM_CWMAX,
708 B43_QOSPARAM_CWCUR,
709 B43_QOSPARAM_AIFS,
710 B43_QOSPARAM_BSLOTS,
711 B43_QOSPARAM_REGGAP,
712 B43_QOSPARAM_STATUS,
713};
714
715
716struct b43_qos_params {
717
718 struct ieee80211_tx_queue_params p;
719};
720
721struct b43_wl;
722
723
724enum b43_firmware_file_type {
725 B43_FWTYPE_PROPRIETARY,
726 B43_FWTYPE_OPENSOURCE,
727 B43_NR_FWTYPES,
728};
729
730
731struct b43_request_fw_context {
732
733 struct b43_wldev *dev;
734
735 struct completion fw_load_complete;
736
737 const struct firmware *blob;
738
739 enum b43_firmware_file_type req_type;
740
741 char errors[B43_NR_FWTYPES][128];
742
743 char fwname[64];
744
745
746 int fatal_failure;
747};
748
749
750struct b43_firmware_file {
751 const char *filename;
752 const struct firmware *data;
753
754
755
756
757
758
759 enum b43_firmware_file_type type;
760};
761
762enum b43_firmware_hdr_format {
763 B43_FW_HDR_598,
764 B43_FW_HDR_410,
765 B43_FW_HDR_351,
766};
767
768
769struct b43_firmware {
770
771 struct b43_firmware_file ucode;
772
773 struct b43_firmware_file pcm;
774
775 struct b43_firmware_file initvals;
776
777 struct b43_firmware_file initvals_band;
778
779
780 u16 rev;
781
782 u16 patch;
783
784
785 enum b43_firmware_hdr_format hdr_format;
786
787
788
789 bool opensource;
790
791
792
793 bool pcm_request_failed;
794};
795
796
797enum {
798 B43_STAT_UNINIT = 0,
799 B43_STAT_INITIALIZED = 1,
800 B43_STAT_STARTED = 2,
801};
802#define b43_status(wldev) atomic_read(&(wldev)->__init_status)
803#define b43_set_status(wldev, stat) do { \
804 atomic_set(&(wldev)->__init_status, (stat)); \
805 smp_wmb(); \
806 } while (0)
807
808
809struct b43_wldev {
810 struct b43_bus_dev *dev;
811 struct b43_wl *wl;
812
813
814
815 atomic_t __init_status;
816
817 bool bad_frames_preempt;
818 bool dfq_valid;
819 bool radio_hw_enable;
820 bool qos_enabled;
821 bool hwcrypto_enabled;
822 bool use_pio;
823
824
825 struct b43_phy phy;
826
827 union {
828
829 struct b43_dma dma;
830
831 struct b43_pio pio;
832 };
833
834
835 bool __using_pio_transfers;
836
837
838 struct b43_stats stats;
839
840
841 u32 irq_reason;
842 u32 dma_reason[6];
843
844 u32 irq_mask;
845
846
847 struct b43_noise_calculation noisecalc;
848
849 int mac_suspended;
850
851
852 struct delayed_work periodic_work;
853 unsigned int periodic_state;
854
855 struct work_struct restart_work;
856
857
858 u16 ktp;
859 struct b43_key key[B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS];
860
861
862 struct b43_firmware fw;
863
864
865 struct list_head list;
866
867
868#ifdef CONFIG_B43_DEBUG
869 struct b43_dfsentry *dfsentry;
870 unsigned int irq_count;
871 unsigned int irq_bit_count[32];
872 unsigned int tx_count;
873 unsigned int rx_count;
874#endif
875};
876
877
878struct b43_wl {
879
880 struct b43_wldev *current_dev;
881
882 struct ieee80211_hw *hw;
883
884
885 struct mutex mutex;
886
887
888 spinlock_t hardirq_lock;
889
890
891
892 bool hw_registred;
893
894
895
896
897
898 struct ieee80211_vif *vif;
899
900 u8 mac_addr[ETH_ALEN];
901
902 u8 bssid[ETH_ALEN];
903
904 int if_type;
905
906 bool operating;
907
908 unsigned int filter_flags;
909
910 struct ieee80211_low_level_stats ieee_stats;
911
912#ifdef CONFIG_B43_HWRNG
913 struct hwrng rng;
914 bool rng_initialized;
915 char rng_name[30 + 1];
916#endif
917
918
919 struct list_head devlist;
920 u8 nr_devs;
921
922 bool radiotap_enabled;
923 bool radio_enabled;
924
925
926 struct sk_buff *current_beacon;
927 bool beacon0_uploaded;
928 bool beacon1_uploaded;
929 bool beacon_templates_virgin;
930 struct work_struct beacon_update_trigger;
931
932
933 struct b43_qos_params qos_params[B43_QOS_QUEUE_NUM];
934
935
936
937
938 struct work_struct txpower_adjust_work;
939
940
941 struct work_struct tx_work;
942
943
944 struct sk_buff_head tx_queue[B43_QOS_QUEUE_NUM];
945
946
947 bool tx_queue_stopped[B43_QOS_QUEUE_NUM];
948
949
950 struct work_struct firmware_load;
951
952
953 struct b43_leds leds;
954
955
956 u8 pio_scratchspace[118] __attribute__((__aligned__(8)));
957 u8 pio_tailspace[4] __attribute__((__aligned__(8)));
958};
959
960static inline struct b43_wl *hw_to_b43_wl(struct ieee80211_hw *hw)
961{
962 return hw->priv;
963}
964
965static inline struct b43_wldev *dev_to_b43_wldev(struct device *dev)
966{
967 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
968 return ssb_get_drvdata(ssb_dev);
969}
970
971
972static inline int b43_is_mode(struct b43_wl *wl, int type)
973{
974 return (wl->operating && wl->if_type == type);
975}
976
977
978
979
980
981static inline enum ieee80211_band b43_current_band(struct b43_wl *wl)
982{
983 return wl->hw->conf.chandef.chan->band;
984}
985
986static inline int b43_bus_may_powerdown(struct b43_wldev *wldev)
987{
988 return wldev->dev->bus_may_powerdown(wldev->dev);
989}
990static inline int b43_bus_powerup(struct b43_wldev *wldev, bool dynamic_pctl)
991{
992 return wldev->dev->bus_powerup(wldev->dev, dynamic_pctl);
993}
994static inline int b43_device_is_enabled(struct b43_wldev *wldev)
995{
996 return wldev->dev->device_is_enabled(wldev->dev);
997}
998static inline void b43_device_enable(struct b43_wldev *wldev,
999 u32 core_specific_flags)
1000{
1001 wldev->dev->device_enable(wldev->dev, core_specific_flags);
1002}
1003static inline void b43_device_disable(struct b43_wldev *wldev,
1004 u32 core_specific_flags)
1005{
1006 wldev->dev->device_disable(wldev->dev, core_specific_flags);
1007}
1008
1009static inline u16 b43_read16(struct b43_wldev *dev, u16 offset)
1010{
1011 return dev->dev->read16(dev->dev, offset);
1012}
1013
1014static inline void b43_write16(struct b43_wldev *dev, u16 offset, u16 value)
1015{
1016 dev->dev->write16(dev->dev, offset, value);
1017}
1018
1019static inline void b43_maskset16(struct b43_wldev *dev, u16 offset, u16 mask,
1020 u16 set)
1021{
1022 b43_write16(dev, offset, (b43_read16(dev, offset) & mask) | set);
1023}
1024
1025static inline u32 b43_read32(struct b43_wldev *dev, u16 offset)
1026{
1027 return dev->dev->read32(dev->dev, offset);
1028}
1029
1030static inline void b43_write32(struct b43_wldev *dev, u16 offset, u32 value)
1031{
1032 dev->dev->write32(dev->dev, offset, value);
1033}
1034
1035static inline void b43_maskset32(struct b43_wldev *dev, u16 offset, u32 mask,
1036 u32 set)
1037{
1038 b43_write32(dev, offset, (b43_read32(dev, offset) & mask) | set);
1039}
1040
1041static inline void b43_block_read(struct b43_wldev *dev, void *buffer,
1042 size_t count, u16 offset, u8 reg_width)
1043{
1044 dev->dev->block_read(dev->dev, buffer, count, offset, reg_width);
1045}
1046
1047static inline void b43_block_write(struct b43_wldev *dev, const void *buffer,
1048 size_t count, u16 offset, u8 reg_width)
1049{
1050 dev->dev->block_write(dev->dev, buffer, count, offset, reg_width);
1051}
1052
1053static inline bool b43_using_pio_transfers(struct b43_wldev *dev)
1054{
1055 return dev->__using_pio_transfers;
1056}
1057
1058
1059__printf(2, 3) void b43info(struct b43_wl *wl, const char *fmt, ...);
1060__printf(2, 3) void b43err(struct b43_wl *wl, const char *fmt, ...);
1061__printf(2, 3) void b43warn(struct b43_wl *wl, const char *fmt, ...);
1062__printf(2, 3) void b43dbg(struct b43_wl *wl, const char *fmt, ...);
1063
1064
1065
1066
1067#if B43_DEBUG
1068# define B43_WARN_ON(x) WARN_ON(x)
1069#else
1070static inline bool __b43_warn_on_dummy(bool x) { return x; }
1071# define B43_WARN_ON(x) __b43_warn_on_dummy(unlikely(!!(x)))
1072#endif
1073
1074
1075#define INT_TO_Q52(i) ((i) << 2)
1076
1077#define Q52_TO_INT(q52) ((q52) >> 2)
1078
1079#define Q52_FMT "%u.%u"
1080#define Q52_ARG(q52) Q52_TO_INT(q52), ((((q52) & 0x3) * 100) / 4)
1081
1082#endif
1083