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17#ifndef _BRCM_PHY_INT_H_
18#define _BRCM_PHY_INT_H_
19
20#include <types.h>
21#include <brcmu_utils.h>
22#include <brcmu_wifi.h>
23
24#define PHY_VERSION { 1, 82, 8, 0 }
25
26#define LCNXN_BASEREV 16
27
28struct phy_shim_info;
29
30struct brcms_phy_srom_fem {
31
32 u8 tssipos;
33
34 u8 extpagain;
35
36 u8 pdetrange;
37
38 u8 triso;
39
40 u8 antswctrllut;
41};
42
43#define ISNPHY(pi) PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_N)
44#define ISLCNPHY(pi) PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_LCN)
45
46#define PHY_GET_RFATTN(rfgain) ((rfgain) & 0x0f)
47#define PHY_GET_PADMIX(rfgain) (((rfgain) & 0x10) >> 4)
48#define PHY_GET_RFGAINID(rfattn, padmix, width) ((rfattn) + ((padmix)*(width)))
49#define PHY_SAT(x, n) ((x) > ((1<<((n)-1))-1) ? ((1<<((n)-1))-1) : \
50 ((x) < -(1<<((n)-1)) ? -(1<<((n)-1)) : (x)))
51#define PHY_SHIFT_ROUND(x, n) ((x) >= 0 ? ((x)+(1<<((n)-1)))>>(n) : (x)>>(n))
52#define PHY_HW_ROUND(x, s) ((x >> s) + ((x >> (s-1)) & (s != 0)))
53
54#define CH_5G_GROUP 3
55#define A_LOW_CHANS 0
56#define A_MID_CHANS 1
57#define A_HIGH_CHANS 2
58#define CH_2G_GROUP 1
59#define G_ALL_CHANS 0
60
61#define FIRST_REF5_CHANNUM 149
62#define LAST_REF5_CHANNUM 165
63#define FIRST_5G_CHAN 14
64#define LAST_5G_CHAN 50
65#define FIRST_MID_5G_CHAN 14
66#define LAST_MID_5G_CHAN 35
67#define FIRST_HIGH_5G_CHAN 36
68#define LAST_HIGH_5G_CHAN 41
69#define FIRST_LOW_5G_CHAN 42
70#define LAST_LOW_5G_CHAN 50
71
72#define BASE_LOW_5G_CHAN 4900
73#define BASE_MID_5G_CHAN 5100
74#define BASE_HIGH_5G_CHAN 5500
75
76#define CHAN5G_FREQ(chan) (5000 + chan*5)
77#define CHAN2G_FREQ(chan) (2407 + chan*5)
78
79#define TXP_FIRST_CCK 0
80#define TXP_LAST_CCK 3
81#define TXP_FIRST_OFDM 4
82#define TXP_LAST_OFDM 11
83#define TXP_FIRST_OFDM_20_CDD 12
84#define TXP_LAST_OFDM_20_CDD 19
85#define TXP_FIRST_MCS_20_SISO 20
86#define TXP_LAST_MCS_20_SISO 27
87#define TXP_FIRST_MCS_20_CDD 28
88#define TXP_LAST_MCS_20_CDD 35
89#define TXP_FIRST_MCS_20_STBC 36
90#define TXP_LAST_MCS_20_STBC 43
91#define TXP_FIRST_MCS_20_SDM 44
92#define TXP_LAST_MCS_20_SDM 51
93#define TXP_FIRST_OFDM_40_SISO 52
94#define TXP_LAST_OFDM_40_SISO 59
95#define TXP_FIRST_OFDM_40_CDD 60
96#define TXP_LAST_OFDM_40_CDD 67
97#define TXP_FIRST_MCS_40_SISO 68
98#define TXP_LAST_MCS_40_SISO 75
99#define TXP_FIRST_MCS_40_CDD 76
100#define TXP_LAST_MCS_40_CDD 83
101#define TXP_FIRST_MCS_40_STBC 84
102#define TXP_LAST_MCS_40_STBC 91
103#define TXP_FIRST_MCS_40_SDM 92
104#define TXP_LAST_MCS_40_SDM 99
105#define TXP_MCS_32 100
106#define TXP_NUM_RATES 101
107#define ADJ_PWR_TBL_LEN 84
108
109#define TXP_FIRST_SISO_MCS_20 20
110#define TXP_LAST_SISO_MCS_20 27
111
112#define PHY_CORE_NUM_1 1
113#define PHY_CORE_NUM_2 2
114#define PHY_CORE_NUM_3 3
115#define PHY_CORE_NUM_4 4
116#define PHY_CORE_MAX PHY_CORE_NUM_4
117#define PHY_CORE_0 0
118#define PHY_CORE_1 1
119#define PHY_CORE_2 2
120#define PHY_CORE_3 3
121
122#define MA_WINDOW_SZ 8
123
124#define PHY_NOISE_SAMPLE_MON 1
125#define PHY_NOISE_SAMPLE_EXTERNAL 2
126#define PHY_NOISE_WINDOW_SZ 16
127#define PHY_NOISE_GLITCH_INIT_MA 10
128#define PHY_NOISE_GLITCH_INIT_MA_BADPlCP 10
129#define PHY_NOISE_STATE_MON 0x1
130#define PHY_NOISE_STATE_EXTERNAL 0x2
131#define PHY_NOISE_SAMPLE_LOG_NUM_NPHY 10
132#define PHY_NOISE_SAMPLE_LOG_NUM_UCODE 9
133
134#define PHY_NOISE_OFFSETFACT_4322 (-103)
135#define PHY_NOISE_MA_WINDOW_SZ 2
136
137#define PHY_RSSI_TABLE_SIZE 64
138#define RSSI_ANT_MERGE_MAX 0
139#define RSSI_ANT_MERGE_MIN 1
140#define RSSI_ANT_MERGE_AVG 2
141
142#define PHY_TSSI_TABLE_SIZE 64
143#define APHY_TSSI_TABLE_SIZE 256
144#define TX_GAIN_TABLE_LENGTH 64
145#define DEFAULT_11A_TXP_IDX 24
146#define NUM_TSSI_FRAMES 4
147#define NULL_TSSI 0x7f
148#define NULL_TSSI_W 0x7f7f
149
150#define PHY_PAPD_EPS_TBL_SIZE_LCNPHY 64
151
152#define LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL 9
153
154#define PHY_TXPWR_MIN 10
155#define PHY_TXPWR_MIN_NPHY 8
156#define RADIOPWR_OVERRIDE_DEF (-1)
157
158#define PWRTBL_NUM_COEFF 3
159
160#define SPURAVOID_DISABLE 0
161#define SPURAVOID_AUTO 1
162#define SPURAVOID_FORCEON 2
163#define SPURAVOID_FORCEON2 3
164
165#define PHY_SW_TIMER_FAST 15
166#define PHY_SW_TIMER_SLOW 60
167#define PHY_SW_TIMER_GLACIAL 120
168
169#define PHY_PERICAL_AUTO 0
170#define PHY_PERICAL_FULL 1
171#define PHY_PERICAL_PARTIAL 2
172
173#define PHY_PERICAL_NODELAY 0
174#define PHY_PERICAL_INIT_DELAY 5
175#define PHY_PERICAL_ASSOC_DELAY 5
176#define PHY_PERICAL_WDOG_DELAY 5
177
178#define MPHASE_TXCAL_NUMCMDS 2
179
180#define PHY_PERICAL_MPHASE_PENDING(pi) \
181 (pi->mphase_cal_phase_id > MPHASE_CAL_STATE_IDLE)
182
183enum {
184 MPHASE_CAL_STATE_IDLE = 0,
185 MPHASE_CAL_STATE_INIT = 1,
186 MPHASE_CAL_STATE_TXPHASE0,
187 MPHASE_CAL_STATE_TXPHASE1,
188 MPHASE_CAL_STATE_TXPHASE2,
189 MPHASE_CAL_STATE_TXPHASE3,
190 MPHASE_CAL_STATE_TXPHASE4,
191 MPHASE_CAL_STATE_TXPHASE5,
192 MPHASE_CAL_STATE_PAPDCAL,
193 MPHASE_CAL_STATE_RXCAL,
194 MPHASE_CAL_STATE_RSSICAL,
195 MPHASE_CAL_STATE_IDLETSSI
196};
197
198enum phy_cal_mode {
199 CAL_FULL,
200 CAL_RECAL,
201 CAL_CURRECAL,
202 CAL_DIGCAL,
203 CAL_GCTRL,
204 CAL_SOFT,
205 CAL_DIGLO
206};
207
208#define RDR_NTIERS 1
209#define RDR_TIER_SIZE 64
210#define RDR_LIST_SIZE (512/3)
211#define RDR_EPOCH_SIZE 40
212#define RDR_NANTENNAS 2
213#define RDR_NTIER_SIZE RDR_LIST_SIZE
214#define RDR_LP_BUFFER_SIZE 64
215#define LP_LEN_HIS_SIZE 10
216
217#define STATIC_NUM_RF 32
218#define STATIC_NUM_BB 9
219
220#define BB_MULT_MASK 0x0000ffff
221#define BB_MULT_VALID_MASK 0x80000000
222
223#define CORDIC_AG 39797
224#define CORDIC_NI 18
225#define FIXED(X) ((s32)((X) << 16))
226
227#define FLOAT(X) \
228 (((X) >= 0) ? ((((X) >> 15) + 1) >> 1) : -((((-(X)) >> 15) + 1) >> 1))
229
230#define PHY_CHAIN_TX_DISABLE_TEMP 115
231#define PHY_HYSTERESIS_DELTATEMP 5
232
233#define SCAN_INPROG_PHY(pi) \
234 (mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN))
235
236#define PLT_INPROG_PHY(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_PLT))
237
238#define ASSOC_INPROG_PHY(pi) \
239 (mboolisset(pi->measure_hold, PHY_HOLD_FOR_ASSOC))
240
241#define SCAN_RM_IN_PROGRESS(pi) \
242 (mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN | PHY_HOLD_FOR_RM))
243
244#define PHY_MUTED(pi) \
245 (mboolisset(pi->measure_hold, PHY_HOLD_FOR_MUTE))
246
247#define PUB_NOT_ASSOC(pi) \
248 (mboolisset(pi->measure_hold, PHY_HOLD_FOR_NOT_ASSOC))
249
250struct phy_table_info {
251 uint table;
252 int q;
253 uint max;
254};
255
256struct phytbl_info {
257 const void *tbl_ptr;
258 u32 tbl_len;
259 u32 tbl_id;
260 u32 tbl_offset;
261 u32 tbl_width;
262};
263
264struct interference_info {
265 u8 curr_home_channel;
266 u16 crsminpwrthld_40_stored;
267 u16 crsminpwrthld_20L_stored;
268 u16 crsminpwrthld_20U_stored;
269 u16 init_gain_code_core1_stored;
270 u16 init_gain_code_core2_stored;
271 u16 init_gain_codeb_core1_stored;
272 u16 init_gain_codeb_core2_stored;
273 u16 init_gain_table_stored[4];
274
275 u16 clip1_hi_gain_code_core1_stored;
276 u16 clip1_hi_gain_code_core2_stored;
277 u16 clip1_hi_gain_codeb_core1_stored;
278 u16 clip1_hi_gain_codeb_core2_stored;
279 u16 nb_clip_thresh_core1_stored;
280 u16 nb_clip_thresh_core2_stored;
281 u16 init_ofdmlna2gainchange_stored[4];
282 u16 init_ccklna2gainchange_stored[4];
283 u16 clip1_lo_gain_code_core1_stored;
284 u16 clip1_lo_gain_code_core2_stored;
285 u16 clip1_lo_gain_codeb_core1_stored;
286 u16 clip1_lo_gain_codeb_core2_stored;
287 u16 w1_clip_thresh_core1_stored;
288 u16 w1_clip_thresh_core2_stored;
289 u16 radio_2056_core1_rssi_gain_stored;
290 u16 radio_2056_core2_rssi_gain_stored;
291 u16 energy_drop_timeout_len_stored;
292
293 u16 ed_crs40_assertthld0_stored;
294 u16 ed_crs40_assertthld1_stored;
295 u16 ed_crs40_deassertthld0_stored;
296 u16 ed_crs40_deassertthld1_stored;
297 u16 ed_crs20L_assertthld0_stored;
298 u16 ed_crs20L_assertthld1_stored;
299 u16 ed_crs20L_deassertthld0_stored;
300 u16 ed_crs20L_deassertthld1_stored;
301 u16 ed_crs20U_assertthld0_stored;
302 u16 ed_crs20U_assertthld1_stored;
303 u16 ed_crs20U_deassertthld0_stored;
304 u16 ed_crs20U_deassertthld1_stored;
305
306 u16 badplcp_ma;
307 u16 badplcp_ma_previous;
308 u16 badplcp_ma_total;
309 u16 badplcp_ma_list[MA_WINDOW_SZ];
310 int badplcp_ma_index;
311 s16 pre_badplcp_cnt;
312 s16 bphy_pre_badplcp_cnt;
313
314 u16 init_gain_core1;
315 u16 init_gain_core2;
316 u16 init_gainb_core1;
317 u16 init_gainb_core2;
318 u16 init_gain_rfseq[4];
319
320 u16 crsminpwr0;
321 u16 crsminpwrl0;
322 u16 crsminpwru0;
323
324 s16 crsminpwr_index;
325
326 u16 radio_2057_core1_rssi_wb1a_gc_stored;
327 u16 radio_2057_core2_rssi_wb1a_gc_stored;
328 u16 radio_2057_core1_rssi_wb1g_gc_stored;
329 u16 radio_2057_core2_rssi_wb1g_gc_stored;
330 u16 radio_2057_core1_rssi_wb2_gc_stored;
331 u16 radio_2057_core2_rssi_wb2_gc_stored;
332 u16 radio_2057_core1_rssi_nb_gc_stored;
333 u16 radio_2057_core2_rssi_nb_gc_stored;
334};
335
336struct aci_save_gphy {
337 u16 rc_cal_ovr;
338 u16 phycrsth1;
339 u16 phycrsth2;
340 u16 init_n1p1_gain;
341 u16 p1_p2_gain;
342 u16 n1_n2_gain;
343 u16 n1_p1_gain;
344 u16 div_search_gain;
345 u16 div_p1_p2_gain;
346 u16 div_search_gn_change;
347 u16 table_7_2;
348 u16 table_7_3;
349 u16 cckshbits_gnref;
350 u16 clip_thresh;
351 u16 clip2_thresh;
352 u16 clip3_thresh;
353 u16 clip_p2_thresh;
354 u16 clip_pwdn_thresh;
355 u16 clip_n1p1_thresh;
356 u16 clip_n1_pwdn_thresh;
357 u16 bbconfig;
358 u16 cthr_sthr_shdin;
359 u16 energy;
360 u16 clip_p1_p2_thresh;
361 u16 threshold;
362 u16 reg15;
363 u16 reg16;
364 u16 reg17;
365 u16 div_srch_idx;
366 u16 div_srch_p1_p2;
367 u16 div_srch_gn_back;
368 u16 ant_dwell;
369 u16 ant_wr_settle;
370};
371
372struct lo_complex_abgphy_info {
373 s8 i;
374 s8 q;
375};
376
377struct nphy_iq_comp {
378 s16 a0;
379 s16 b0;
380 s16 a1;
381 s16 b1;
382};
383
384struct nphy_txpwrindex {
385 s8 index;
386 s8 index_internal;
387 s8 index_internal_save;
388 u16 AfectrlOverride;
389 u16 AfeCtrlDacGain;
390 u16 rad_gain;
391 u8 bbmult;
392 u16 iqcomp_a;
393 u16 iqcomp_b;
394 u16 locomp;
395};
396
397struct txiqcal_cache {
398
399 u16 txcal_coeffs_2G[8];
400 u16 txcal_radio_regs_2G[8];
401 struct nphy_iq_comp rxcal_coeffs_2G;
402
403 u16 txcal_coeffs_5G[8];
404 u16 txcal_radio_regs_5G[8];
405 struct nphy_iq_comp rxcal_coeffs_5G;
406};
407
408struct nphy_pwrctrl {
409 s8 max_pwr_2g;
410 s8 idle_targ_2g;
411 s16 pwrdet_2g_a1;
412 s16 pwrdet_2g_b0;
413 s16 pwrdet_2g_b1;
414 s8 max_pwr_5gm;
415 s8 idle_targ_5gm;
416 s8 max_pwr_5gh;
417 s8 max_pwr_5gl;
418 s16 pwrdet_5gm_a1;
419 s16 pwrdet_5gm_b0;
420 s16 pwrdet_5gm_b1;
421 s16 pwrdet_5gl_a1;
422 s16 pwrdet_5gl_b0;
423 s16 pwrdet_5gl_b1;
424 s16 pwrdet_5gh_a1;
425 s16 pwrdet_5gh_b0;
426 s16 pwrdet_5gh_b1;
427 s8 idle_targ_5gl;
428 s8 idle_targ_5gh;
429 s8 idle_tssi_2g;
430 s8 idle_tssi_5g;
431 s8 idle_tssi;
432 s16 a1;
433 s16 b0;
434 s16 b1;
435};
436
437struct nphy_txgains {
438 u16 txlpf[2];
439 u16 txgm[2];
440 u16 pga[2];
441 u16 pad[2];
442 u16 ipa[2];
443};
444
445#define PHY_NOISEVAR_BUFSIZE 10
446
447struct nphy_noisevar_buf {
448 int bufcount;
449 int tone_id[PHY_NOISEVAR_BUFSIZE];
450 u32 noise_vars[PHY_NOISEVAR_BUFSIZE];
451 u32 min_noise_vars[PHY_NOISEVAR_BUFSIZE];
452};
453
454struct rssical_cache {
455 u16 rssical_radio_regs_2G[2];
456 u16 rssical_phyregs_2G[12];
457
458 u16 rssical_radio_regs_5G[2];
459 u16 rssical_phyregs_5G[12];
460};
461
462struct lcnphy_cal_results {
463
464 u16 txiqlocal_a;
465 u16 txiqlocal_b;
466 u16 txiqlocal_didq;
467 u8 txiqlocal_ei0;
468 u8 txiqlocal_eq0;
469 u8 txiqlocal_fi0;
470 u8 txiqlocal_fq0;
471
472 u16 txiqlocal_bestcoeffs[11];
473 u16 txiqlocal_bestcoeffs_valid;
474
475 u32 papd_eps_tbl[PHY_PAPD_EPS_TBL_SIZE_LCNPHY];
476 u16 analog_gain_ref;
477 u16 lut_begin;
478 u16 lut_end;
479 u16 lut_step;
480 u16 rxcompdbm;
481 u16 papdctrl;
482 u16 sslpnCalibClkEnCtrl;
483
484 u16 rxiqcal_coeff_a0;
485 u16 rxiqcal_coeff_b0;
486};
487
488struct shared_phy {
489 struct brcms_phy *phy_head;
490 uint unit;
491 struct phy_shim_info *physhim;
492 uint corerev;
493 u32 machwcap;
494 bool up;
495 bool clk;
496 uint now;
497 u16 vid;
498 u16 did;
499 uint chip;
500 uint chiprev;
501 uint chippkg;
502 uint sromrev;
503 uint boardtype;
504 uint boardrev;
505 u32 boardflags;
506 u32 boardflags2;
507 uint fast_timer;
508 uint slow_timer;
509 uint glacial_timer;
510 u8 rx_antdiv;
511 s8 phy_noise_window[MA_WINDOW_SZ];
512 uint phy_noise_index;
513 u8 hw_phytxchain;
514 u8 hw_phyrxchain;
515 u8 phytxchain;
516 u8 phyrxchain;
517 u8 rssi_mode;
518 bool _rifs_phy;
519};
520
521struct brcms_phy_pub {
522 uint phy_type;
523 uint phy_rev;
524 u8 phy_corenum;
525 u16 radioid;
526 u8 radiorev;
527 u8 radiover;
528
529 uint coreflags;
530 uint ana_rev;
531 bool abgphy_encore;
532};
533
534struct phy_func_ptr {
535 void (*init)(struct brcms_phy *);
536 void (*calinit)(struct brcms_phy *);
537 void (*chanset)(struct brcms_phy *, u16 chanspec);
538 void (*txpwrrecalc)(struct brcms_phy *);
539 int (*longtrn)(struct brcms_phy *, int);
540 void (*txiqccget)(struct brcms_phy *, u16 *, u16 *);
541 void (*txiqccset)(struct brcms_phy *, u16, u16);
542 u16 (*txloccget)(struct brcms_phy *);
543 void (*radioloftget)(struct brcms_phy *, u8 *, u8 *, u8 *, u8 *);
544 void (*carrsuppr)(struct brcms_phy *);
545 s32 (*rxsigpwr)(struct brcms_phy *, s32);
546 void (*detach)(struct brcms_phy *);
547};
548
549struct brcms_phy {
550 struct brcms_phy_pub pubpi_ro;
551 struct shared_phy *sh;
552 struct phy_func_ptr pi_fptr;
553
554 union {
555 struct brcms_phy_lcnphy *pi_lcnphy;
556 } u;
557 bool user_txpwr_at_rfport;
558
559 struct bcma_device *d11core;
560 struct brcms_phy *next;
561 struct brcms_phy_pub pubpi;
562
563 bool do_initcal;
564 bool phytest_on;
565 bool ofdm_rateset_war;
566 bool bf_preempt_4306;
567 u16 radio_chanspec;
568 u8 antsel_type;
569 u16 bw;
570 u8 txpwr_percent;
571 bool phy_init_por;
572
573 bool init_in_progress;
574 bool initialized;
575 bool sbtml_gm;
576 uint refcnt;
577 bool watchdog_override;
578 u8 phynoise_state;
579 uint phynoise_now;
580 int phynoise_chan_watchdog;
581 bool phynoise_polling;
582 bool disable_percal;
583 u32 measure_hold;
584
585 s16 txpa_2g[PWRTBL_NUM_COEFF];
586 s16 txpa_2g_low_temp[PWRTBL_NUM_COEFF];
587 s16 txpa_2g_high_temp[PWRTBL_NUM_COEFF];
588 s16 txpa_5g_low[PWRTBL_NUM_COEFF];
589 s16 txpa_5g_mid[PWRTBL_NUM_COEFF];
590 s16 txpa_5g_hi[PWRTBL_NUM_COEFF];
591
592 u8 tx_srom_max_2g;
593 u8 tx_srom_max_5g_low;
594 u8 tx_srom_max_5g_mid;
595 u8 tx_srom_max_5g_hi;
596 u8 tx_srom_max_rate_2g[TXP_NUM_RATES];
597 u8 tx_srom_max_rate_5g_low[TXP_NUM_RATES];
598 u8 tx_srom_max_rate_5g_mid[TXP_NUM_RATES];
599 u8 tx_srom_max_rate_5g_hi[TXP_NUM_RATES];
600 u8 tx_user_target[TXP_NUM_RATES];
601 s8 tx_power_offset[TXP_NUM_RATES];
602 u8 tx_power_target[TXP_NUM_RATES];
603
604 struct brcms_phy_srom_fem srom_fem2g;
605 struct brcms_phy_srom_fem srom_fem5g;
606
607 u8 tx_power_max;
608 u8 tx_power_max_rate_ind;
609 bool hwpwrctrl;
610 u8 nphy_txpwrctrl;
611 s8 nphy_txrx_chain;
612 bool phy_5g_pwrgain;
613
614 u16 phy_wreg;
615 u16 phy_wreg_limit;
616
617 s8 n_preamble_override;
618 u8 antswitch;
619 u8 aa2g, aa5g;
620
621 s8 idle_tssi[CH_5G_GROUP];
622 s8 target_idle_tssi;
623 s8 txpwr_est_Pout;
624 u8 tx_power_min;
625 u8 txpwr_limit[TXP_NUM_RATES];
626 u8 txpwr_env_limit[TXP_NUM_RATES];
627 u8 adj_pwr_tbl_nphy[ADJ_PWR_TBL_LEN];
628
629 bool channel_14_wide_filter;
630
631 bool txpwroverride;
632 bool txpwridx_override_aphy;
633 s16 radiopwr_override;
634 u16 hwpwr_txcur;
635 u8 saved_txpwr_idx;
636
637 bool edcrs_threshold_lock;
638
639 u32 tr_R_gain_val;
640 u32 tr_T_gain_val;
641
642 s16 ofdm_analog_filt_bw_override;
643 s16 cck_analog_filt_bw_override;
644 s16 ofdm_rccal_override;
645 s16 cck_rccal_override;
646 u16 extlna_type;
647
648 uint interference_mode_crs_time;
649 u16 crsglitch_prev;
650 bool interference_mode_crs;
651
652 u32 phy_tx_tone_freq;
653 uint phy_lastcal;
654 bool phy_forcecal;
655 bool phy_fixed_noise;
656 u32 xtalfreq;
657 u8 pdiv;
658 s8 carrier_suppr_disable;
659
660 bool phy_bphy_evm;
661 bool phy_bphy_rfcs;
662 s8 phy_scraminit;
663 u8 phy_gpiosel;
664
665 s16 phy_txcore_disable_temp;
666 s16 phy_txcore_enable_temp;
667 s8 phy_tempsense_offset;
668 bool phy_txcore_heatedup;
669
670 u16 radiopwr;
671 u16 bb_atten;
672 u16 txctl1;
673
674 u16 mintxbias;
675 u16 mintxmag;
676 struct lo_complex_abgphy_info gphy_locomp_iq
677 [STATIC_NUM_RF][STATIC_NUM_BB];
678 s8 stats_11b_txpower[STATIC_NUM_RF][STATIC_NUM_BB];
679 u16 gain_table[TX_GAIN_TABLE_LENGTH];
680 bool loopback_gain;
681 s16 max_lpback_gain_hdB;
682 s16 trsw_rx_gain_hdB;
683 u8 power_vec[8];
684
685 u16 rc_cal;
686 int nrssi_table_delta;
687 int nrssi_slope_scale;
688 int nrssi_slope_offset;
689 int min_rssi;
690 int max_rssi;
691
692 s8 txpwridx;
693 u8 min_txpower;
694
695 u8 a_band_high_disable;
696
697 u16 tx_vos;
698 u16 global_tx_bb_dc_bias_loft;
699
700 int rf_max;
701 int bb_max;
702 int rf_list_size;
703 int bb_list_size;
704 u16 *rf_attn_list;
705 u16 *bb_attn_list;
706 u16 padmix_mask;
707 u16 padmix_reg;
708 u16 *txmag_list;
709 uint txmag_len;
710 bool txmag_enable;
711
712 s8 *a_tssi_to_dbm;
713 s8 *m_tssi_to_dbm;
714 s8 *l_tssi_to_dbm;
715 s8 *h_tssi_to_dbm;
716 u8 *hwtxpwr;
717
718 u16 freqtrack_saved_regs[2];
719 int cur_interference_mode;
720 bool hwpwrctrl_capable;
721 bool temppwrctrl_capable;
722
723 uint phycal_nslope;
724 uint phycal_noffset;
725 uint phycal_mlo;
726 uint phycal_txpower;
727
728 u8 phy_aa2g;
729
730 bool nphy_tableloaded;
731 s8 nphy_rssisel;
732 u32 nphy_bb_mult_save;
733 u16 nphy_txiqlocal_bestc[11];
734 bool nphy_txiqlocal_coeffsvalid;
735 struct nphy_txpwrindex nphy_txpwrindex[PHY_CORE_NUM_2];
736 struct nphy_pwrctrl nphy_pwrctrl_info[PHY_CORE_NUM_2];
737 u16 cck2gpo;
738 u32 ofdm2gpo;
739 u32 ofdm5gpo;
740 u32 ofdm5glpo;
741 u32 ofdm5ghpo;
742 u8 bw402gpo;
743 u8 bw405gpo;
744 u8 bw405glpo;
745 u8 bw405ghpo;
746 u8 cdd2gpo;
747 u8 cdd5gpo;
748 u8 cdd5glpo;
749 u8 cdd5ghpo;
750 u8 stbc2gpo;
751 u8 stbc5gpo;
752 u8 stbc5glpo;
753 u8 stbc5ghpo;
754 u8 bwdup2gpo;
755 u8 bwdup5gpo;
756 u8 bwdup5glpo;
757 u8 bwdup5ghpo;
758 u16 mcs2gpo[8];
759 u16 mcs5gpo[8];
760 u16 mcs5glpo[8];
761 u16 mcs5ghpo[8];
762 u32 nphy_rxcalparams;
763
764 u8 phy_spuravoid;
765 bool phy_isspuravoid;
766
767 u8 phy_pabias;
768 u8 nphy_papd_skip;
769 u8 nphy_tssi_slope;
770
771 s16 nphy_noise_win[PHY_CORE_MAX][PHY_NOISE_WINDOW_SZ];
772 u8 nphy_noise_index;
773
774 bool nphy_gain_boost;
775 bool nphy_elna_gain_config;
776 u16 old_bphy_test;
777 u16 old_bphy_testcontrol;
778
779 bool phyhang_avoid;
780
781 bool rssical_nphy;
782 u8 nphy_perical;
783 uint nphy_perical_last;
784 u8 cal_type_override;
785 u8 mphase_cal_phase_id;
786 u8 mphase_txcal_cmdidx;
787 u8 mphase_txcal_numcmds;
788 u16 mphase_txcal_bestcoeffs[11];
789 u16 nphy_txiqlocal_chanspec;
790 u16 nphy_iqcal_chanspec_2G;
791 u16 nphy_iqcal_chanspec_5G;
792 u16 nphy_rssical_chanspec_2G;
793 u16 nphy_rssical_chanspec_5G;
794 struct wlapi_timer *phycal_timer;
795 bool use_int_tx_iqlo_cal_nphy;
796 bool internal_tx_iqlo_cal_tapoff_intpa_nphy;
797 s16 nphy_lastcal_temp;
798
799 struct txiqcal_cache calibration_cache;
800 struct rssical_cache rssical_cache;
801
802 u8 nphy_txpwr_idx[2];
803 u8 nphy_papd_cal_type;
804 uint nphy_papd_last_cal;
805 u16 nphy_papd_tx_gain_at_last_cal[2];
806 u8 nphy_papd_cal_gain_index[2];
807 s16 nphy_papd_epsilon_offset[2];
808 bool nphy_papd_recal_enable;
809 u32 nphy_papd_recal_counter;
810 bool nphy_force_papd_cal;
811 bool nphy_papdcomp;
812 bool ipa2g_on;
813 bool ipa5g_on;
814
815 u16 classifier_state;
816 u16 clip_state[2];
817 uint nphy_deaf_count;
818 u8 rxiq_samps;
819 u8 rxiq_antsel;
820
821 u16 rfctrlIntc1_save;
822 u16 rfctrlIntc2_save;
823 bool first_cal_after_assoc;
824 u16 tx_rx_cal_radio_saveregs[22];
825 u16 tx_rx_cal_phy_saveregs[15];
826
827 u8 nphy_cal_orig_pwr_idx[2];
828 u8 nphy_txcal_pwr_idx[2];
829 u8 nphy_rxcal_pwr_idx[2];
830 u16 nphy_cal_orig_tx_gain[2];
831 struct nphy_txgains nphy_cal_target_gain;
832 u16 nphy_txcal_bbmult;
833 u16 nphy_gmval;
834
835 u16 nphy_saved_bbconf;
836
837 bool nphy_gband_spurwar_en;
838 bool nphy_gband_spurwar2_en;
839 bool nphy_aband_spurwar_en;
840 u16 nphy_rccal_value;
841 u16 nphy_crsminpwr[3];
842 struct nphy_noisevar_buf nphy_saved_noisevars;
843 bool nphy_anarxlpf_adjusted;
844 bool nphy_crsminpwr_adjusted;
845 bool nphy_noisevars_adjusted;
846
847 bool nphy_rxcal_active;
848 u16 radar_percal_mask;
849 bool dfs_lp_buffer_nphy;
850
851 u16 nphy_fineclockgatecontrol;
852
853 s8 rx2tx_biasentry;
854
855 u16 crsminpwr0;
856 u16 crsminpwrl0;
857 u16 crsminpwru0;
858 s16 noise_crsminpwr_index;
859 u16 init_gain_core1;
860 u16 init_gain_core2;
861 u16 init_gainb_core1;
862 u16 init_gainb_core2;
863 u8 aci_noise_curr_channel;
864 u16 init_gain_rfseq[4];
865
866 bool radio_is_on;
867
868 bool nphy_sample_play_lpf_bw_ctl_ovr;
869
870 u16 tbl_data_hi;
871 u16 tbl_data_lo;
872 u16 tbl_addr;
873
874 uint tbl_save_id;
875 uint tbl_save_offset;
876
877 u8 txpwrctrl;
878 s8 txpwrindex[PHY_CORE_MAX];
879
880 u8 phycal_tempdelta;
881 u32 mcs20_po;
882 u32 mcs40_po;
883 struct wiphy *wiphy;
884};
885
886struct cs32 {
887 s32 q;
888 s32 i;
889};
890
891struct radio_regs {
892 u16 address;
893 u32 init_a;
894 u32 init_g;
895 u8 do_init_a;
896 u8 do_init_g;
897};
898
899struct radio_20xx_regs {
900 u16 address;
901 u8 init;
902 u8 do_init;
903};
904
905struct lcnphy_radio_regs {
906 u16 address;
907 u8 init_a;
908 u8 init_g;
909 u8 do_init_a;
910 u8 do_init_g;
911};
912
913extern u16 read_phy_reg(struct brcms_phy *pi, u16 addr);
914extern void write_phy_reg(struct brcms_phy *pi, u16 addr, u16 val);
915extern void and_phy_reg(struct brcms_phy *pi, u16 addr, u16 val);
916extern void or_phy_reg(struct brcms_phy *pi, u16 addr, u16 val);
917extern void mod_phy_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val);
918
919extern u16 read_radio_reg(struct brcms_phy *pi, u16 addr);
920extern void or_radio_reg(struct brcms_phy *pi, u16 addr, u16 val);
921extern void and_radio_reg(struct brcms_phy *pi, u16 addr, u16 val);
922extern void mod_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask,
923 u16 val);
924extern void xor_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask);
925
926extern void write_radio_reg(struct brcms_phy *pi, u16 addr, u16 val);
927
928extern void wlc_phyreg_enter(struct brcms_phy_pub *pih);
929extern void wlc_phyreg_exit(struct brcms_phy_pub *pih);
930extern void wlc_radioreg_enter(struct brcms_phy_pub *pih);
931extern void wlc_radioreg_exit(struct brcms_phy_pub *pih);
932
933extern void wlc_phy_read_table(struct brcms_phy *pi,
934 const struct phytbl_info *ptbl_info,
935 u16 tblAddr, u16 tblDataHi,
936 u16 tblDatalo);
937extern void wlc_phy_write_table(struct brcms_phy *pi,
938 const struct phytbl_info *ptbl_info,
939 u16 tblAddr, u16 tblDataHi, u16 tblDatalo);
940extern void wlc_phy_table_addr(struct brcms_phy *pi, uint tbl_id,
941 uint tbl_offset, u16 tblAddr, u16 tblDataHi,
942 u16 tblDataLo);
943extern void wlc_phy_table_data_write(struct brcms_phy *pi, uint width, u32 val);
944
945extern void write_phy_channel_reg(struct brcms_phy *pi, uint val);
946extern void wlc_phy_txpower_update_shm(struct brcms_phy *pi);
947
948extern u8 wlc_phy_nbits(s32 value);
949extern void wlc_phy_compute_dB(u32 *cmplx_pwr, s8 *p_dB, u8 core);
950
951extern uint wlc_phy_init_radio_regs_allbands(struct brcms_phy *pi,
952 struct radio_20xx_regs *radioregs);
953extern uint wlc_phy_init_radio_regs(struct brcms_phy *pi,
954 const struct radio_regs *radioregs,
955 u16 core_offset);
956
957extern void wlc_phy_txpower_ipa_upd(struct brcms_phy *pi);
958
959extern void wlc_phy_do_dummy_tx(struct brcms_phy *pi, bool ofdm, bool pa_on);
960extern void wlc_phy_papd_decode_epsilon(u32 epsilon, s32 *eps_real,
961 s32 *eps_imag);
962
963extern void wlc_phy_cal_perical_mphase_reset(struct brcms_phy *pi);
964extern void wlc_phy_cal_perical_mphase_restart(struct brcms_phy *pi);
965
966extern bool wlc_phy_attach_nphy(struct brcms_phy *pi);
967extern bool wlc_phy_attach_lcnphy(struct brcms_phy *pi);
968
969extern void wlc_phy_detach_lcnphy(struct brcms_phy *pi);
970
971extern void wlc_phy_init_nphy(struct brcms_phy *pi);
972extern void wlc_phy_init_lcnphy(struct brcms_phy *pi);
973
974extern void wlc_phy_cal_init_nphy(struct brcms_phy *pi);
975extern void wlc_phy_cal_init_lcnphy(struct brcms_phy *pi);
976
977extern void wlc_phy_chanspec_set_nphy(struct brcms_phy *pi,
978 u16 chanspec);
979extern void wlc_phy_chanspec_set_lcnphy(struct brcms_phy *pi,
980 u16 chanspec);
981extern void wlc_phy_chanspec_set_fixup_lcnphy(struct brcms_phy *pi,
982 u16 chanspec);
983extern int wlc_phy_channel2freq(uint channel);
984extern int wlc_phy_chanspec_freq2bandrange_lpssn(uint);
985extern int wlc_phy_chanspec_bandrange_get(struct brcms_phy *, u16 chanspec);
986
987extern void wlc_lcnphy_set_tx_pwr_ctrl(struct brcms_phy *pi, u16 mode);
988extern s8 wlc_lcnphy_get_current_tx_pwr_idx(struct brcms_phy *pi);
989
990extern void wlc_phy_txpower_recalc_target_nphy(struct brcms_phy *pi);
991extern void wlc_lcnphy_txpower_recalc_target(struct brcms_phy *pi);
992extern void wlc_phy_txpower_recalc_target_lcnphy(struct brcms_phy *pi);
993
994extern void wlc_lcnphy_set_tx_pwr_by_index(struct brcms_phy *pi, int index);
995extern void wlc_lcnphy_tx_pu(struct brcms_phy *pi, bool bEnable);
996extern void wlc_lcnphy_stop_tx_tone(struct brcms_phy *pi);
997extern void wlc_lcnphy_start_tx_tone(struct brcms_phy *pi, s32 f_kHz,
998 u16 max_val, bool iqcalmode);
999
1000extern void wlc_phy_txpower_sromlimit_get_nphy(struct brcms_phy *pi, uint chan,
1001 u8 *max_pwr, u8 rate_id);
1002extern void wlc_phy_ofdm_to_mcs_powers_nphy(u8 *power, u8 rate_mcs_start,
1003 u8 rate_mcs_end,
1004 u8 rate_ofdm_start);
1005extern void wlc_phy_mcs_to_ofdm_powers_nphy(u8 *power,
1006 u8 rate_ofdm_start,
1007 u8 rate_ofdm_end,
1008 u8 rate_mcs_start);
1009
1010extern u16 wlc_lcnphy_tempsense(struct brcms_phy *pi, bool mode);
1011extern s16 wlc_lcnphy_tempsense_new(struct brcms_phy *pi, bool mode);
1012extern s8 wlc_lcnphy_tempsense_degree(struct brcms_phy *pi, bool mode);
1013extern s8 wlc_lcnphy_vbatsense(struct brcms_phy *pi, bool mode);
1014extern void wlc_phy_carrier_suppress_lcnphy(struct brcms_phy *pi);
1015extern void wlc_lcnphy_crsuprs(struct brcms_phy *pi, int channel);
1016extern void wlc_lcnphy_epa_switch(struct brcms_phy *pi, bool mode);
1017extern void wlc_2064_vco_cal(struct brcms_phy *pi);
1018
1019extern void wlc_phy_txpower_recalc_target(struct brcms_phy *pi);
1020
1021#define LCNPHY_TBL_ID_PAPDCOMPDELTATBL 0x18
1022#define LCNPHY_TX_POWER_TABLE_SIZE 128
1023#define LCNPHY_MAX_TX_POWER_INDEX (LCNPHY_TX_POWER_TABLE_SIZE - 1)
1024#define LCNPHY_TBL_ID_TXPWRCTL 0x07
1025#define LCNPHY_TX_PWR_CTRL_OFF 0
1026#define LCNPHY_TX_PWR_CTRL_SW (0x1 << 15)
1027#define LCNPHY_TX_PWR_CTRL_HW ((0x1 << 15) | \
1028 (0x1 << 14) | \
1029 (0x1 << 13))
1030
1031#define LCNPHY_TX_PWR_CTRL_TEMPBASED 0xE001
1032
1033extern void wlc_lcnphy_write_table(struct brcms_phy *pi,
1034 const struct phytbl_info *pti);
1035extern void wlc_lcnphy_read_table(struct brcms_phy *pi,
1036 struct phytbl_info *pti);
1037extern void wlc_lcnphy_set_tx_iqcc(struct brcms_phy *pi, u16 a, u16 b);
1038extern void wlc_lcnphy_set_tx_locc(struct brcms_phy *pi, u16 didq);
1039extern void wlc_lcnphy_get_tx_iqcc(struct brcms_phy *pi, u16 *a, u16 *b);
1040extern u16 wlc_lcnphy_get_tx_locc(struct brcms_phy *pi);
1041extern void wlc_lcnphy_get_radio_loft(struct brcms_phy *pi, u8 *ei0,
1042 u8 *eq0, u8 *fi0, u8 *fq0);
1043extern void wlc_lcnphy_calib_modes(struct brcms_phy *pi, uint mode);
1044extern void wlc_lcnphy_deaf_mode(struct brcms_phy *pi, bool mode);
1045extern bool wlc_phy_tpc_isenabled_lcnphy(struct brcms_phy *pi);
1046extern void wlc_lcnphy_tx_pwr_update_npt(struct brcms_phy *pi);
1047extern s32 wlc_lcnphy_tssi2dbm(s32 tssi, s32 a1, s32 b0, s32 b1);
1048extern void wlc_lcnphy_get_tssi(struct brcms_phy *pi, s8 *ofdm_pwr,
1049 s8 *cck_pwr);
1050extern void wlc_lcnphy_tx_power_adjustment(struct brcms_phy_pub *ppi);
1051
1052extern s32 wlc_lcnphy_rx_signal_power(struct brcms_phy *pi, s32 gain_index);
1053
1054#define NPHY_MAX_HPVGA1_INDEX 10
1055#define NPHY_DEF_HPVGA1_INDEXLIMIT 7
1056
1057struct phy_iq_est {
1058 s32 iq_prod;
1059 u32 i_pwr;
1060 u32 q_pwr;
1061};
1062
1063extern void wlc_phy_stay_in_carriersearch_nphy(struct brcms_phy *pi,
1064 bool enable);
1065extern void wlc_nphy_deaf_mode(struct brcms_phy *pi, bool mode);
1066
1067#define wlc_phy_write_table_nphy(pi, pti) \
1068 wlc_phy_write_table(pi, pti, 0x72, 0x74, 0x73)
1069
1070#define wlc_phy_read_table_nphy(pi, pti) \
1071 wlc_phy_read_table(pi, pti, 0x72, 0x74, 0x73)
1072
1073#define wlc_nphy_table_addr(pi, id, off) \
1074 wlc_phy_table_addr((pi), (id), (off), 0x72, 0x74, 0x73)
1075
1076#define wlc_nphy_table_data_write(pi, w, v) \
1077 wlc_phy_table_data_write((pi), (w), (v))
1078
1079extern void wlc_phy_table_read_nphy(struct brcms_phy *pi, u32, u32 l, u32 o,
1080 u32 w, void *d);
1081extern void wlc_phy_table_write_nphy(struct brcms_phy *pi, u32, u32, u32,
1082 u32, const void *);
1083
1084#define PHY_IPA(pi) \
1085 ((pi->ipa2g_on && CHSPEC_IS2G(pi->radio_chanspec)) || \
1086 (pi->ipa5g_on && CHSPEC_IS5G(pi->radio_chanspec)))
1087
1088#define BRCMS_PHY_WAR_PR51571(pi) \
1089 if (NREV_LT((pi)->pubpi.phy_rev, 3)) \
1090 (void)bcma_read32(pi->d11core, D11REGOFFS(maccontrol))
1091
1092extern void wlc_phy_cal_perical_nphy_run(struct brcms_phy *pi, u8 caltype);
1093extern void wlc_phy_aci_reset_nphy(struct brcms_phy *pi);
1094extern void wlc_phy_pa_override_nphy(struct brcms_phy *pi, bool en);
1095
1096extern u8 wlc_phy_get_chan_freq_range_nphy(struct brcms_phy *pi, uint chan);
1097extern void wlc_phy_switch_radio_nphy(struct brcms_phy *pi, bool on);
1098
1099extern void wlc_phy_stf_chain_upd_nphy(struct brcms_phy *pi);
1100
1101extern void wlc_phy_force_rfseq_nphy(struct brcms_phy *pi, u8 cmd);
1102extern s16 wlc_phy_tempsense_nphy(struct brcms_phy *pi);
1103
1104extern u16 wlc_phy_classifier_nphy(struct brcms_phy *pi, u16 mask, u16 val);
1105
1106extern void wlc_phy_rx_iq_est_nphy(struct brcms_phy *pi, struct phy_iq_est *est,
1107 u16 num_samps, u8 wait_time,
1108 u8 wait_for_crs);
1109
1110extern void wlc_phy_rx_iq_coeffs_nphy(struct brcms_phy *pi, u8 write,
1111 struct nphy_iq_comp *comp);
1112extern void wlc_phy_aci_and_noise_reduction_nphy(struct brcms_phy *pi);
1113
1114extern void wlc_phy_rxcore_setstate_nphy(struct brcms_phy_pub *pih,
1115 u8 rxcore_bitmask);
1116extern u8 wlc_phy_rxcore_getstate_nphy(struct brcms_phy_pub *pih);
1117
1118extern void wlc_phy_txpwrctrl_enable_nphy(struct brcms_phy *pi, u8 ctrl_type);
1119extern void wlc_phy_txpwr_fixpower_nphy(struct brcms_phy *pi);
1120extern void wlc_phy_txpwr_apply_nphy(struct brcms_phy *pi);
1121extern void wlc_phy_txpwr_papd_cal_nphy(struct brcms_phy *pi);
1122extern u16 wlc_phy_txpwr_idx_get_nphy(struct brcms_phy *pi);
1123
1124extern struct nphy_txgains wlc_phy_get_tx_gain_nphy(struct brcms_phy *pi);
1125extern int wlc_phy_cal_txiqlo_nphy(struct brcms_phy *pi,
1126 struct nphy_txgains target_gain,
1127 bool full, bool m);
1128extern int wlc_phy_cal_rxiq_nphy(struct brcms_phy *pi,
1129 struct nphy_txgains target_gain,
1130 u8 type, bool d);
1131extern void wlc_phy_txpwr_index_nphy(struct brcms_phy *pi, u8 core_mask,
1132 s8 txpwrindex, bool res);
1133extern void wlc_phy_rssisel_nphy(struct brcms_phy *pi, u8 core, u8 rssi_type);
1134extern int wlc_phy_poll_rssi_nphy(struct brcms_phy *pi, u8 rssi_type,
1135 s32 *rssi_buf, u8 nsamps);
1136extern void wlc_phy_rssi_cal_nphy(struct brcms_phy *pi);
1137extern int wlc_phy_aci_scan_nphy(struct brcms_phy *pi);
1138extern void wlc_phy_cal_txgainctrl_nphy(struct brcms_phy *pi,
1139 s32 dBm_targetpower, bool debug);
1140extern int wlc_phy_tx_tone_nphy(struct brcms_phy *pi, u32 f_kHz, u16 max_val,
1141 u8 mode, u8, bool);
1142extern void wlc_phy_stopplayback_nphy(struct brcms_phy *pi);
1143extern void wlc_phy_est_tonepwr_nphy(struct brcms_phy *pi, s32 *qdBm_pwrbuf,
1144 u8 num_samps);
1145extern void wlc_phy_radio205x_vcocal_nphy(struct brcms_phy *pi);
1146
1147extern int wlc_phy_rssi_compute_nphy(struct brcms_phy *pi,
1148 struct d11rxhdr *rxh);
1149
1150#define NPHY_TESTPATTERN_BPHY_EVM 0
1151#define NPHY_TESTPATTERN_BPHY_RFCS 1
1152
1153extern void wlc_phy_nphy_tkip_rifs_war(struct brcms_phy *pi, u8 rifs);
1154
1155void wlc_phy_get_pwrdet_offsets(struct brcms_phy *pi, s8 *cckoffset,
1156 s8 *ofdmoffset);
1157extern s8 wlc_phy_upd_rssi_offset(struct brcms_phy *pi, s8 rssi,
1158 u16 chanspec);
1159
1160extern bool wlc_phy_n_txpower_ipa_ison(struct brcms_phy *pih);
1161#endif
1162
