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69#ifndef __iwl_commands_h__
70#define __iwl_commands_h__
71
72#include <linux/ieee80211.h>
73#include <linux/types.h>
74
75
76enum {
77 REPLY_ALIVE = 0x1,
78 REPLY_ERROR = 0x2,
79 REPLY_ECHO = 0x3,
80
81
82 REPLY_RXON = 0x10,
83 REPLY_RXON_ASSOC = 0x11,
84 REPLY_QOS_PARAM = 0x13,
85 REPLY_RXON_TIMING = 0x14,
86
87
88 REPLY_ADD_STA = 0x18,
89 REPLY_REMOVE_STA = 0x19,
90 REPLY_REMOVE_ALL_STA = 0x1a,
91 REPLY_TXFIFO_FLUSH = 0x1e,
92
93
94 REPLY_WEPKEY = 0x20,
95
96
97 REPLY_TX = 0x1c,
98 REPLY_LEDS_CMD = 0x48,
99 REPLY_TX_LINK_QUALITY_CMD = 0x4e,
100
101
102 COEX_PRIORITY_TABLE_CMD = 0x5a,
103 COEX_MEDIUM_NOTIFICATION = 0x5b,
104 COEX_EVENT_CMD = 0x5c,
105
106
107 TEMPERATURE_NOTIFICATION = 0x62,
108 CALIBRATION_CFG_CMD = 0x65,
109 CALIBRATION_RES_NOTIFICATION = 0x66,
110 CALIBRATION_COMPLETE_NOTIFICATION = 0x67,
111
112
113 REPLY_QUIET_CMD = 0x71,
114 REPLY_CHANNEL_SWITCH = 0x72,
115 CHANNEL_SWITCH_NOTIFICATION = 0x73,
116 REPLY_SPECTRUM_MEASUREMENT_CMD = 0x74,
117 SPECTRUM_MEASURE_NOTIFICATION = 0x75,
118
119
120 POWER_TABLE_CMD = 0x77,
121 PM_SLEEP_NOTIFICATION = 0x7A,
122 PM_DEBUG_STATISTIC_NOTIFIC = 0x7B,
123
124
125 REPLY_SCAN_CMD = 0x80,
126 REPLY_SCAN_ABORT_CMD = 0x81,
127 SCAN_START_NOTIFICATION = 0x82,
128 SCAN_RESULTS_NOTIFICATION = 0x83,
129 SCAN_COMPLETE_NOTIFICATION = 0x84,
130
131
132 BEACON_NOTIFICATION = 0x90,
133 REPLY_TX_BEACON = 0x91,
134 WHO_IS_AWAKE_NOTIFICATION = 0x94,
135
136
137 REPLY_TX_POWER_DBM_CMD = 0x95,
138 QUIET_NOTIFICATION = 0x96,
139 REPLY_TX_PWR_TABLE_CMD = 0x97,
140 REPLY_TX_POWER_DBM_CMD_V1 = 0x98,
141 TX_ANT_CONFIGURATION_CMD = 0x98,
142 MEASURE_ABORT_NOTIFICATION = 0x99,
143
144
145 REPLY_BT_CONFIG = 0x9b,
146
147
148 REPLY_STATISTICS_CMD = 0x9c,
149 STATISTICS_NOTIFICATION = 0x9d,
150
151
152 REPLY_CARD_STATE_CMD = 0xa0,
153 CARD_STATE_NOTIFICATION = 0xa1,
154
155
156 MISSED_BEACONS_NOTIFICATION = 0xa2,
157
158 REPLY_CT_KILL_CONFIG_CMD = 0xa4,
159 SENSITIVITY_CMD = 0xa8,
160 REPLY_PHY_CALIBRATION_CMD = 0xb0,
161 REPLY_RX_PHY_CMD = 0xc0,
162 REPLY_RX_MPDU_CMD = 0xc1,
163 REPLY_RX = 0xc3,
164 REPLY_COMPRESSED_BA = 0xc5,
165
166
167 REPLY_BT_COEX_PRIO_TABLE = 0xcc,
168 REPLY_BT_COEX_PROT_ENV = 0xcd,
169 REPLY_BT_COEX_PROFILE_NOTIF = 0xce,
170
171
172 REPLY_WIPAN_PARAMS = 0xb2,
173 REPLY_WIPAN_RXON = 0xb3,
174 REPLY_WIPAN_RXON_TIMING = 0xb4,
175 REPLY_WIPAN_RXON_ASSOC = 0xb6,
176 REPLY_WIPAN_QOS_PARAM = 0xb7,
177 REPLY_WIPAN_WEPKEY = 0xb8,
178 REPLY_WIPAN_P2P_CHANNEL_SWITCH = 0xb9,
179 REPLY_WIPAN_NOA_NOTIFICATION = 0xbc,
180 REPLY_WIPAN_DEACTIVATION_COMPLETE = 0xbd,
181
182 REPLY_WOWLAN_PATTERNS = 0xe0,
183 REPLY_WOWLAN_WAKEUP_FILTER = 0xe1,
184 REPLY_WOWLAN_TSC_RSC_PARAMS = 0xe2,
185 REPLY_WOWLAN_TKIP_PARAMS = 0xe3,
186 REPLY_WOWLAN_KEK_KCK_MATERIAL = 0xe4,
187 REPLY_WOWLAN_GET_STATUS = 0xe5,
188 REPLY_D3_CONFIG = 0xd3,
189
190 REPLY_MAX = 0xff
191};
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200
201
202#define IWL_MIN_NUM_QUEUES 11
203
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206
207#define IWL_DEFAULT_CMD_QUEUE_NUM 4
208#define IWL_IPAN_CMD_QUEUE_NUM 9
209
210#define IWL_TX_FIFO_BK 0
211#define IWL_TX_FIFO_BE 1
212#define IWL_TX_FIFO_VI 2
213#define IWL_TX_FIFO_VO 3
214#define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK
215#define IWL_TX_FIFO_BE_IPAN 4
216#define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI
217#define IWL_TX_FIFO_VO_IPAN 5
218
219#define IWL_TX_FIFO_AUX 5
220#define IWL_TX_FIFO_UNUSED 255
221
222#define IWLAGN_CMD_FIFO_NUM 7
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228
229#define IWL_IPAN_MCAST_QUEUE 8
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279#define RATE_MCS_CODE_MSK 0x7
280#define RATE_MCS_SPATIAL_POS 3
281#define RATE_MCS_SPATIAL_MSK 0x18
282#define RATE_MCS_HT_DUP_POS 5
283#define RATE_MCS_HT_DUP_MSK 0x20
284
285#define RATE_MCS_RATE_MSK 0xff
286
287
288#define RATE_MCS_FLAGS_POS 8
289#define RATE_MCS_HT_POS 8
290#define RATE_MCS_HT_MSK 0x100
291
292
293#define RATE_MCS_CCK_POS 9
294#define RATE_MCS_CCK_MSK 0x200
295
296
297#define RATE_MCS_GF_POS 10
298#define RATE_MCS_GF_MSK 0x400
299
300
301#define RATE_MCS_HT40_POS 11
302#define RATE_MCS_HT40_MSK 0x800
303
304
305#define RATE_MCS_DUP_POS 12
306#define RATE_MCS_DUP_MSK 0x1000
307
308
309#define RATE_MCS_SGI_POS 13
310#define RATE_MCS_SGI_MSK 0x2000
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321#define RATE_MCS_ANT_POS 14
322#define RATE_MCS_ANT_A_MSK 0x04000
323#define RATE_MCS_ANT_B_MSK 0x08000
324#define RATE_MCS_ANT_C_MSK 0x10000
325#define RATE_MCS_ANT_AB_MSK (RATE_MCS_ANT_A_MSK | RATE_MCS_ANT_B_MSK)
326#define RATE_MCS_ANT_ABC_MSK (RATE_MCS_ANT_AB_MSK | RATE_MCS_ANT_C_MSK)
327#define RATE_ANT_NUM 3
328
329#define POWER_TABLE_NUM_ENTRIES 33
330#define POWER_TABLE_NUM_HT_OFDM_ENTRIES 32
331#define POWER_TABLE_CCK_ENTRY 32
332
333#define IWL_PWR_NUM_HT_OFDM_ENTRIES 24
334#define IWL_PWR_CCK_ENTRIES 2
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342
343struct tx_power_dual_stream {
344 __le32 dw;
345} __packed;
346
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349
350
351#define IWLAGN_TX_POWER_AUTO 0x7f
352#define IWLAGN_TX_POWER_NO_CLOSED (0x1 << 6)
353
354struct iwlagn_tx_power_dbm_cmd {
355 s8 global_lmt;
356 u8 flags;
357 s8 srv_chan_lmt;
358 u8 reserved;
359} __packed;
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367struct iwl_tx_ant_config_cmd {
368 __le32 valid;
369} __packed;
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376
377#define UCODE_VALID_OK cpu_to_le32(0x1)
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425struct iwl_error_event_table {
426 u32 valid;
427 u32 error_id;
428 u32 pc;
429 u32 blink1;
430 u32 blink2;
431 u32 ilink1;
432 u32 ilink2;
433 u32 data1;
434 u32 data2;
435 u32 line;
436 u32 bcon_time;
437 u32 tsf_low;
438 u32 tsf_hi;
439 u32 gp1;
440 u32 gp2;
441 u32 gp3;
442 u32 ucode_ver;
443 u32 hw_ver;
444 u32 brd_ver;
445 u32 log_pc;
446 u32 frame_ptr;
447 u32 stack_ptr;
448 u32 hcmd;
449 u32 isr0;
450
451 u32 isr1;
452
453 u32 isr2;
454
455 u32 isr3;
456
457 u32 isr4;
458
459 u32 isr_pref;
460 u32 wait_event;
461 u32 l2p_control;
462 u32 l2p_duration;
463 u32 l2p_mhvalid;
464 u32 l2p_addr_match;
465 u32 lmpm_pmg_sel;
466
467 u32 u_timestamp;
468
469 u32 flow_handler;
470} __packed;
471
472struct iwl_alive_resp {
473 u8 ucode_minor;
474 u8 ucode_major;
475 __le16 reserved1;
476 u8 sw_rev[8];
477 u8 ver_type;
478 u8 ver_subtype;
479 __le16 reserved2;
480 __le32 log_event_table_ptr;
481 __le32 error_event_table_ptr;
482 __le32 timestamp;
483 __le32 is_valid;
484} __packed;
485
486
487
488
489struct iwl_error_resp {
490 __le32 error_type;
491 u8 cmd_id;
492 u8 reserved1;
493 __le16 bad_cmd_seq_num;
494 __le32 error_info;
495 __le64 timestamp;
496} __packed;
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507
508enum {
509 RXON_DEV_TYPE_AP = 1,
510 RXON_DEV_TYPE_ESS = 3,
511 RXON_DEV_TYPE_IBSS = 4,
512 RXON_DEV_TYPE_SNIFFER = 6,
513 RXON_DEV_TYPE_CP = 7,
514 RXON_DEV_TYPE_2STA = 8,
515 RXON_DEV_TYPE_P2P = 9,
516};
517
518
519#define RXON_RX_CHAIN_DRIVER_FORCE_MSK cpu_to_le16(0x1 << 0)
520#define RXON_RX_CHAIN_DRIVER_FORCE_POS (0)
521#define RXON_RX_CHAIN_VALID_MSK cpu_to_le16(0x7 << 1)
522#define RXON_RX_CHAIN_VALID_POS (1)
523#define RXON_RX_CHAIN_FORCE_SEL_MSK cpu_to_le16(0x7 << 4)
524#define RXON_RX_CHAIN_FORCE_SEL_POS (4)
525#define RXON_RX_CHAIN_FORCE_MIMO_SEL_MSK cpu_to_le16(0x7 << 7)
526#define RXON_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
527#define RXON_RX_CHAIN_CNT_MSK cpu_to_le16(0x3 << 10)
528#define RXON_RX_CHAIN_CNT_POS (10)
529#define RXON_RX_CHAIN_MIMO_CNT_MSK cpu_to_le16(0x3 << 12)
530#define RXON_RX_CHAIN_MIMO_CNT_POS (12)
531#define RXON_RX_CHAIN_MIMO_FORCE_MSK cpu_to_le16(0x1 << 14)
532#define RXON_RX_CHAIN_MIMO_FORCE_POS (14)
533
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535
536#define RXON_FLG_BAND_24G_MSK cpu_to_le32(1 << 0)
537#define RXON_FLG_CCK_MSK cpu_to_le32(1 << 1)
538
539#define RXON_FLG_AUTO_DETECT_MSK cpu_to_le32(1 << 2)
540
541#define RXON_FLG_TGG_PROTECT_MSK cpu_to_le32(1 << 3)
542
543#define RXON_FLG_SHORT_SLOT_MSK cpu_to_le32(1 << 4)
544#define RXON_FLG_SHORT_PREAMBLE_MSK cpu_to_le32(1 << 5)
545
546#define RXON_FLG_DIS_DIV_MSK cpu_to_le32(1 << 7)
547#define RXON_FLG_ANT_SEL_MSK cpu_to_le32(0x0f00)
548#define RXON_FLG_ANT_A_MSK cpu_to_le32(1 << 8)
549#define RXON_FLG_ANT_B_MSK cpu_to_le32(1 << 9)
550
551#define RXON_FLG_RADAR_DETECT_MSK cpu_to_le32(1 << 12)
552#define RXON_FLG_TGJ_NARROW_BAND_MSK cpu_to_le32(1 << 13)
553
554
555#define RXON_FLG_TSF2HOST_MSK cpu_to_le32(1 << 15)
556
557
558
559#define RXON_FLG_CTRL_CHANNEL_LOC_POS (22)
560#define RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK cpu_to_le32(0x1 << 22)
561
562#define RXON_FLG_HT_OPERATING_MODE_POS (23)
563
564#define RXON_FLG_HT_PROT_MSK cpu_to_le32(0x1 << 23)
565#define RXON_FLG_HT40_PROT_MSK cpu_to_le32(0x2 << 23)
566
567#define RXON_FLG_CHANNEL_MODE_POS (25)
568#define RXON_FLG_CHANNEL_MODE_MSK cpu_to_le32(0x3 << 25)
569
570
571enum {
572 CHANNEL_MODE_LEGACY = 0,
573 CHANNEL_MODE_PURE_40 = 1,
574 CHANNEL_MODE_MIXED = 2,
575 CHANNEL_MODE_RESERVED = 3,
576};
577#define RXON_FLG_CHANNEL_MODE_LEGACY cpu_to_le32(CHANNEL_MODE_LEGACY << RXON_FLG_CHANNEL_MODE_POS)
578#define RXON_FLG_CHANNEL_MODE_PURE_40 cpu_to_le32(CHANNEL_MODE_PURE_40 << RXON_FLG_CHANNEL_MODE_POS)
579#define RXON_FLG_CHANNEL_MODE_MIXED cpu_to_le32(CHANNEL_MODE_MIXED << RXON_FLG_CHANNEL_MODE_POS)
580
581
582#define RXON_FLG_SELF_CTS_EN cpu_to_le32(0x1<<30)
583
584
585
586#define RXON_FILTER_PROMISC_MSK cpu_to_le32(1 << 0)
587
588#define RXON_FILTER_CTL2HOST_MSK cpu_to_le32(1 << 1)
589
590#define RXON_FILTER_ACCEPT_GRP_MSK cpu_to_le32(1 << 2)
591
592#define RXON_FILTER_DIS_DECRYPT_MSK cpu_to_le32(1 << 3)
593
594#define RXON_FILTER_DIS_GRP_DECRYPT_MSK cpu_to_le32(1 << 4)
595
596#define RXON_FILTER_ASSOC_MSK cpu_to_le32(1 << 5)
597
598#define RXON_FILTER_BCON_AWARE_MSK cpu_to_le32(1 << 6)
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618struct iwl_rxon_cmd {
619 u8 node_addr[6];
620 __le16 reserved1;
621 u8 bssid_addr[6];
622 __le16 reserved2;
623 u8 wlap_bssid_addr[6];
624 __le16 reserved3;
625 u8 dev_type;
626 u8 air_propagation;
627 __le16 rx_chain;
628 u8 ofdm_basic_rates;
629 u8 cck_basic_rates;
630 __le16 assoc_id;
631 __le32 flags;
632 __le32 filter_flags;
633 __le16 channel;
634 u8 ofdm_ht_single_stream_basic_rates;
635 u8 ofdm_ht_dual_stream_basic_rates;
636 u8 ofdm_ht_triple_stream_basic_rates;
637 u8 reserved5;
638 __le16 acquisition_data;
639 __le16 reserved6;
640} __packed;
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642
643
644
645struct iwl_rxon_assoc_cmd {
646 __le32 flags;
647 __le32 filter_flags;
648 u8 ofdm_basic_rates;
649 u8 cck_basic_rates;
650 __le16 reserved1;
651 u8 ofdm_ht_single_stream_basic_rates;
652 u8 ofdm_ht_dual_stream_basic_rates;
653 u8 ofdm_ht_triple_stream_basic_rates;
654 u8 reserved2;
655 __le16 rx_chain_select_flags;
656 __le16 acquisition_data;
657 __le32 reserved3;
658} __packed;
659
660#define IWL_CONN_MAX_LISTEN_INTERVAL 10
661#define IWL_MAX_UCODE_BEACON_INTERVAL 4
662
663
664
665
666struct iwl_rxon_time_cmd {
667 __le64 timestamp;
668 __le16 beacon_interval;
669 __le16 atim_window;
670 __le32 beacon_init_val;
671 __le16 listen_interval;
672 u8 dtim_period;
673 u8 delta_cp_bss_tbtts;
674} __packed;
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690struct iwl5000_channel_switch_cmd {
691 u8 band;
692 u8 expect_beacon;
693 __le16 channel;
694 __le32 rxon_flags;
695 __le32 rxon_filter_flags;
696 __le32 switch_time;
697 __le32 reserved[2][IWL_PWR_NUM_HT_OFDM_ENTRIES + IWL_PWR_CCK_ENTRIES];
698} __packed;
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711struct iwl6000_channel_switch_cmd {
712 u8 band;
713 u8 expect_beacon;
714 __le16 channel;
715 __le32 rxon_flags;
716 __le32 rxon_filter_flags;
717 __le32 switch_time;
718 __le32 reserved[3][IWL_PWR_NUM_HT_OFDM_ENTRIES + IWL_PWR_CCK_ENTRIES];
719} __packed;
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724struct iwl_csa_notification {
725 __le16 band;
726 __le16 channel;
727 __le32 status;
728} __packed;
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752struct iwl_ac_qos {
753 __le16 cw_min;
754 __le16 cw_max;
755 u8 aifsn;
756 u8 reserved1;
757 __le16 edca_txop;
758} __packed;
759
760
761#define QOS_PARAM_FLG_UPDATE_EDCA_MSK cpu_to_le32(0x01)
762#define QOS_PARAM_FLG_TGN_MSK cpu_to_le32(0x02)
763#define QOS_PARAM_FLG_TXOP_TYPE_MSK cpu_to_le32(0x10)
764
765
766#define AC_NUM 4
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774struct iwl_qosparam_cmd {
775 __le32 qos_flags;
776 struct iwl_ac_qos ac[AC_NUM];
777} __packed;
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789#define IWL_AP_ID 0
790#define IWL_AP_ID_PAN 1
791#define IWL_STA_ID 2
792#define IWLAGN_PAN_BCAST_ID 14
793#define IWLAGN_BROADCAST_ID 15
794#define IWLAGN_STATION_COUNT 16
795
796#define IWL_TID_NON_QOS IWL_MAX_TID_COUNT
797
798#define STA_FLG_TX_RATE_MSK cpu_to_le32(1 << 2)
799#define STA_FLG_PWR_SAVE_MSK cpu_to_le32(1 << 8)
800#define STA_FLG_PAN_STATION cpu_to_le32(1 << 13)
801#define STA_FLG_RTS_MIMO_PROT_MSK cpu_to_le32(1 << 17)
802#define STA_FLG_AGG_MPDU_8US_MSK cpu_to_le32(1 << 18)
803#define STA_FLG_MAX_AGG_SIZE_POS (19)
804#define STA_FLG_MAX_AGG_SIZE_MSK cpu_to_le32(3 << 19)
805#define STA_FLG_HT40_EN_MSK cpu_to_le32(1 << 21)
806#define STA_FLG_MIMO_DIS_MSK cpu_to_le32(1 << 22)
807#define STA_FLG_AGG_MPDU_DENSITY_POS (23)
808#define STA_FLG_AGG_MPDU_DENSITY_MSK cpu_to_le32(7 << 23)
809
810
811#define STA_CONTROL_MODIFY_MSK 0x01
812
813
814#define STA_KEY_FLG_ENCRYPT_MSK cpu_to_le16(0x0007)
815#define STA_KEY_FLG_NO_ENC cpu_to_le16(0x0000)
816#define STA_KEY_FLG_WEP cpu_to_le16(0x0001)
817#define STA_KEY_FLG_CCMP cpu_to_le16(0x0002)
818#define STA_KEY_FLG_TKIP cpu_to_le16(0x0003)
819
820#define STA_KEY_FLG_KEYID_POS 8
821#define STA_KEY_FLG_INVALID cpu_to_le16(0x0800)
822
823#define STA_KEY_FLG_MAP_KEY_MSK cpu_to_le16(0x0008)
824
825
826#define STA_KEY_FLG_KEY_SIZE_MSK cpu_to_le16(0x1000)
827#define STA_KEY_MULTICAST_MSK cpu_to_le16(0x4000)
828#define STA_KEY_MAX_NUM 8
829#define STA_KEY_MAX_NUM_PAN 16
830
831#define IWLAGN_HW_KEY_DEFAULT 0xfe
832
833
834#define STA_MODIFY_KEY_MASK 0x01
835#define STA_MODIFY_TID_DISABLE_TX 0x02
836#define STA_MODIFY_TX_RATE_MSK 0x04
837#define STA_MODIFY_ADDBA_TID_MSK 0x08
838#define STA_MODIFY_DELBA_TID_MSK 0x10
839#define STA_MODIFY_SLEEP_TX_COUNT_MSK 0x20
840
841
842
843#define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
844
845
846struct iwl_keyinfo {
847 __le16 key_flags;
848 u8 tkip_rx_tsc_byte2;
849 u8 reserved1;
850 __le16 tkip_rx_ttak[5];
851 u8 key_offset;
852 u8 reserved2;
853 u8 key[16];
854 __le64 tx_secur_seq_cnt;
855 __le64 hw_tkip_mic_rx_key;
856 __le64 hw_tkip_mic_tx_key;
857} __packed;
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871struct sta_id_modify {
872 u8 addr[ETH_ALEN];
873 __le16 reserved1;
874 u8 sta_id;
875 u8 modify_mask;
876 __le16 reserved2;
877} __packed;
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905struct iwl_addsta_cmd {
906 u8 mode;
907 u8 reserved[3];
908 struct sta_id_modify sta;
909 struct iwl_keyinfo key;
910 __le32 station_flags;
911 __le32 station_flags_msk;
912
913
914
915
916 __le16 tid_disable_tx;
917 __le16 legacy_reserved;
918
919
920
921 u8 add_immediate_ba_tid;
922
923
924
925 u8 remove_immediate_ba_tid;
926
927
928
929 __le16 add_immediate_ba_ssn;
930
931
932
933
934
935
936 __le16 sleep_tx_count;
937
938 __le16 reserved2;
939} __packed;
940
941
942#define ADD_STA_SUCCESS_MSK 0x1
943#define ADD_STA_NO_ROOM_IN_TABLE 0x2
944#define ADD_STA_NO_BLOCK_ACK_RESOURCE 0x4
945#define ADD_STA_MODIFY_NON_EXIST_STA 0x8
946
947
948
949struct iwl_add_sta_resp {
950 u8 status;
951} __packed;
952
953#define REM_STA_SUCCESS_MSK 0x1
954
955
956
957struct iwl_rem_sta_resp {
958 u8 status;
959} __packed;
960
961
962
963
964struct iwl_rem_sta_cmd {
965 u8 num_sta;
966 u8 reserved[3];
967 u8 addr[ETH_ALEN];
968 u8 reserved2[2];
969} __packed;
970
971
972
973#define IWL_SCD_BK_MSK cpu_to_le32(BIT(0))
974#define IWL_SCD_BE_MSK cpu_to_le32(BIT(1))
975#define IWL_SCD_VI_MSK cpu_to_le32(BIT(2))
976#define IWL_SCD_VO_MSK cpu_to_le32(BIT(3))
977#define IWL_SCD_MGMT_MSK cpu_to_le32(BIT(3))
978
979
980#define IWL_PAN_SCD_BK_MSK cpu_to_le32(BIT(4))
981#define IWL_PAN_SCD_BE_MSK cpu_to_le32(BIT(5))
982#define IWL_PAN_SCD_VI_MSK cpu_to_le32(BIT(6))
983#define IWL_PAN_SCD_VO_MSK cpu_to_le32(BIT(7))
984#define IWL_PAN_SCD_MGMT_MSK cpu_to_le32(BIT(7))
985#define IWL_PAN_SCD_MULTICAST_MSK cpu_to_le32(BIT(8))
986
987#define IWL_AGG_TX_QUEUE_MSK cpu_to_le32(0xffc00)
988
989#define IWL_DROP_ALL BIT(1)
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
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1011
1012struct iwl_txfifo_flush_cmd {
1013 __le32 queue_control;
1014 __le16 flush_control;
1015 __le16 reserved;
1016} __packed;
1017
1018
1019
1020
1021struct iwl_wep_key {
1022 u8 key_index;
1023 u8 key_offset;
1024 u8 reserved1[2];
1025 u8 key_size;
1026 u8 reserved2[3];
1027 u8 key[16];
1028} __packed;
1029
1030struct iwl_wep_cmd {
1031 u8 num_keys;
1032 u8 global_key_type;
1033 u8 flags;
1034 u8 reserved;
1035 struct iwl_wep_key key[0];
1036} __packed;
1037
1038#define WEP_KEY_WEP_TYPE 1
1039#define WEP_KEYS_MAX 4
1040#define WEP_INVALID_OFFSET 0xff
1041#define WEP_KEY_LEN_64 5
1042#define WEP_KEY_LEN_128 13
1043
1044
1045
1046
1047
1048
1049
1050#define RX_RES_STATUS_NO_CRC32_ERROR cpu_to_le32(1 << 0)
1051#define RX_RES_STATUS_NO_RXE_OVERFLOW cpu_to_le32(1 << 1)
1052
1053#define RX_RES_PHY_FLAGS_BAND_24_MSK cpu_to_le16(1 << 0)
1054#define RX_RES_PHY_FLAGS_MOD_CCK_MSK cpu_to_le16(1 << 1)
1055#define RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK cpu_to_le16(1 << 2)
1056#define RX_RES_PHY_FLAGS_NARROW_BAND_MSK cpu_to_le16(1 << 3)
1057#define RX_RES_PHY_FLAGS_ANTENNA_MSK 0x70
1058#define RX_RES_PHY_FLAGS_ANTENNA_POS 4
1059#define RX_RES_PHY_FLAGS_AGG_MSK cpu_to_le16(1 << 7)
1060
1061#define RX_RES_STATUS_SEC_TYPE_MSK (0x7 << 8)
1062#define RX_RES_STATUS_SEC_TYPE_NONE (0x0 << 8)
1063#define RX_RES_STATUS_SEC_TYPE_WEP (0x1 << 8)
1064#define RX_RES_STATUS_SEC_TYPE_CCMP (0x2 << 8)
1065#define RX_RES_STATUS_SEC_TYPE_TKIP (0x3 << 8)
1066#define RX_RES_STATUS_SEC_TYPE_ERR (0x7 << 8)
1067
1068#define RX_RES_STATUS_STATION_FOUND (1<<6)
1069#define RX_RES_STATUS_NO_STATION_INFO_MISMATCH (1<<7)
1070
1071#define RX_RES_STATUS_DECRYPT_TYPE_MSK (0x3 << 11)
1072#define RX_RES_STATUS_NOT_DECRYPT (0x0 << 11)
1073#define RX_RES_STATUS_DECRYPT_OK (0x3 << 11)
1074#define RX_RES_STATUS_BAD_ICV_MIC (0x1 << 11)
1075#define RX_RES_STATUS_BAD_KEY_TTAK (0x2 << 11)
1076
1077#define RX_MPDU_RES_STATUS_ICV_OK (0x20)
1078#define RX_MPDU_RES_STATUS_MIC_OK (0x40)
1079#define RX_MPDU_RES_STATUS_TTAK_OK (1 << 7)
1080#define RX_MPDU_RES_STATUS_DEC_DONE_MSK (0x800)
1081
1082
1083#define IWLAGN_RX_RES_PHY_CNT 8
1084#define IWLAGN_RX_RES_AGC_IDX 1
1085#define IWLAGN_RX_RES_RSSI_AB_IDX 2
1086#define IWLAGN_RX_RES_RSSI_C_IDX 3
1087#define IWLAGN_OFDM_AGC_MSK 0xfe00
1088#define IWLAGN_OFDM_AGC_BIT_POS 9
1089#define IWLAGN_OFDM_RSSI_INBAND_A_BITMSK 0x00ff
1090#define IWLAGN_OFDM_RSSI_ALLBAND_A_BITMSK 0xff00
1091#define IWLAGN_OFDM_RSSI_A_BIT_POS 0
1092#define IWLAGN_OFDM_RSSI_INBAND_B_BITMSK 0xff0000
1093#define IWLAGN_OFDM_RSSI_ALLBAND_B_BITMSK 0xff000000
1094#define IWLAGN_OFDM_RSSI_B_BIT_POS 16
1095#define IWLAGN_OFDM_RSSI_INBAND_C_BITMSK 0x00ff
1096#define IWLAGN_OFDM_RSSI_ALLBAND_C_BITMSK 0xff00
1097#define IWLAGN_OFDM_RSSI_C_BIT_POS 0
1098
1099struct iwlagn_non_cfg_phy {
1100 __le32 non_cfg_phy[IWLAGN_RX_RES_PHY_CNT];
1101} __packed;
1102
1103
1104
1105
1106
1107
1108struct iwl_rx_phy_res {
1109 u8 non_cfg_phy_cnt;
1110 u8 cfg_phy_cnt;
1111 u8 stat_id;
1112 u8 reserved1;
1113 __le64 timestamp;
1114 __le32 beacon_time_stamp;
1115 __le16 phy_flags;
1116 __le16 channel;
1117 u8 non_cfg_phy_buf[32];
1118 __le32 rate_n_flags;
1119 __le16 byte_count;
1120 __le16 frame_time;
1121} __packed;
1122
1123struct iwl_rx_mpdu_res_start {
1124 __le16 byte_count;
1125 __le16 reserved;
1126} __packed;
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
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1142
1143
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1145
1146
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1148
1149
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1156
1157
1158
1159
1160#define TX_CMD_FLG_PROT_REQUIRE_MSK cpu_to_le32(1 << 0)
1161
1162
1163
1164
1165#define TX_CMD_FLG_ACK_MSK cpu_to_le32(1 << 3)
1166
1167
1168
1169
1170
1171
1172
1173#define TX_CMD_FLG_STA_RATE_MSK cpu_to_le32(1 << 4)
1174
1175
1176
1177#define TX_CMD_FLG_IMM_BA_RSP_MASK cpu_to_le32(1 << 6)
1178
1179
1180#define TX_CMD_FLG_ANT_SEL_MSK cpu_to_le32(0xf00)
1181
1182
1183
1184#define TX_CMD_FLG_IGNORE_BT cpu_to_le32(1 << 12)
1185
1186
1187
1188
1189
1190#define TX_CMD_FLG_SEQ_CTL_MSK cpu_to_le32(1 << 13)
1191
1192
1193
1194#define TX_CMD_FLG_MORE_FRAG_MSK cpu_to_le32(1 << 14)
1195
1196
1197
1198
1199#define TX_CMD_FLG_TSF_MSK cpu_to_le32(1 << 16)
1200
1201
1202
1203
1204
1205
1206
1207#define TX_CMD_FLG_MH_PAD_MSK cpu_to_le32(1 << 20)
1208
1209
1210
1211#define TX_CMD_FLG_AGG_CCMP_MSK cpu_to_le32(1 << 22)
1212
1213
1214#define TX_CMD_FLG_DUR_MSK cpu_to_le32(1 << 25)
1215
1216
1217
1218
1219
1220#define TX_CMD_SEC_WEP 0x01
1221#define TX_CMD_SEC_CCM 0x02
1222#define TX_CMD_SEC_TKIP 0x03
1223#define TX_CMD_SEC_MSK 0x03
1224#define TX_CMD_SEC_SHIFT 6
1225#define TX_CMD_SEC_KEY128 0x08
1226
1227
1228
1229
1230#define WEP_IV_LEN 4
1231#define WEP_ICV_LEN 4
1232#define CCMP_MIC_LEN 8
1233#define TKIP_ICV_LEN 4
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244struct iwl_dram_scratch {
1245 u8 try_cnt;
1246 u8 bt_kill_cnt;
1247 __le16 reserved;
1248} __packed;
1249
1250struct iwl_tx_cmd {
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261 __le16 len;
1262
1263
1264
1265
1266
1267
1268 __le16 next_frame_len;
1269
1270 __le32 tx_flags;
1271
1272
1273
1274 struct iwl_dram_scratch scratch;
1275
1276
1277 __le32 rate_n_flags;
1278
1279
1280 u8 sta_id;
1281
1282
1283 u8 sec_ctl;
1284
1285
1286
1287
1288
1289
1290
1291
1292 u8 initial_rate_index;
1293 u8 reserved;
1294 u8 key[16];
1295 __le16 next_frame_flags;
1296 __le16 reserved2;
1297 union {
1298 __le32 life_time;
1299 __le32 attempt;
1300 } stop_time;
1301
1302
1303
1304 __le32 dram_lsb_ptr;
1305 u8 dram_msb_ptr;
1306
1307 u8 rts_retry_limit;
1308 u8 data_retry_limit;
1309 u8 tid_tspec;
1310 union {
1311 __le16 pm_frame_timeout;
1312 __le16 attempt_duration;
1313 } timeout;
1314
1315
1316
1317
1318
1319 __le16 driver_txop;
1320
1321
1322
1323
1324
1325 u8 payload[0];
1326 struct ieee80211_hdr hdr[0];
1327} __packed;
1328
1329
1330
1331
1332
1333
1334
1335
1336enum {
1337 TX_STATUS_SUCCESS = 0x01,
1338 TX_STATUS_DIRECT_DONE = 0x02,
1339
1340 TX_STATUS_POSTPONE_DELAY = 0x40,
1341 TX_STATUS_POSTPONE_FEW_BYTES = 0x41,
1342 TX_STATUS_POSTPONE_BT_PRIO = 0x42,
1343 TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43,
1344 TX_STATUS_POSTPONE_CALC_TTAK = 0x44,
1345
1346 TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81,
1347 TX_STATUS_FAIL_SHORT_LIMIT = 0x82,
1348 TX_STATUS_FAIL_LONG_LIMIT = 0x83,
1349 TX_STATUS_FAIL_FIFO_UNDERRUN = 0x84,
1350 TX_STATUS_FAIL_DRAIN_FLOW = 0x85,
1351 TX_STATUS_FAIL_RFKILL_FLUSH = 0x86,
1352 TX_STATUS_FAIL_LIFE_EXPIRE = 0x87,
1353 TX_STATUS_FAIL_DEST_PS = 0x88,
1354 TX_STATUS_FAIL_HOST_ABORTED = 0x89,
1355 TX_STATUS_FAIL_BT_RETRY = 0x8a,
1356 TX_STATUS_FAIL_STA_INVALID = 0x8b,
1357 TX_STATUS_FAIL_FRAG_DROPPED = 0x8c,
1358 TX_STATUS_FAIL_TID_DISABLE = 0x8d,
1359 TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e,
1360 TX_STATUS_FAIL_INSUFFICIENT_CF_POLL = 0x8f,
1361 TX_STATUS_FAIL_PASSIVE_NO_RX = 0x90,
1362 TX_STATUS_FAIL_NO_BEACON_ON_RADAR = 0x91,
1363};
1364
1365#define TX_PACKET_MODE_REGULAR 0x0000
1366#define TX_PACKET_MODE_BURST_SEQ 0x0100
1367#define TX_PACKET_MODE_BURST_FIRST 0x0200
1368
1369enum {
1370 TX_POWER_PA_NOT_ACTIVE = 0x0,
1371};
1372
1373enum {
1374 TX_STATUS_MSK = 0x000000ff,
1375 TX_STATUS_DELAY_MSK = 0x00000040,
1376 TX_STATUS_ABORT_MSK = 0x00000080,
1377 TX_PACKET_MODE_MSK = 0x0000ff00,
1378 TX_FIFO_NUMBER_MSK = 0x00070000,
1379 TX_RESERVED = 0x00780000,
1380 TX_POWER_PA_DETECT_MSK = 0x7f800000,
1381 TX_ABORT_REQUIRED_MSK = 0x80000000,
1382};
1383
1384
1385
1386
1387
1388enum {
1389 AGG_TX_STATE_TRANSMITTED = 0x00,
1390 AGG_TX_STATE_UNDERRUN_MSK = 0x01,
1391 AGG_TX_STATE_BT_PRIO_MSK = 0x02,
1392 AGG_TX_STATE_FEW_BYTES_MSK = 0x04,
1393 AGG_TX_STATE_ABORT_MSK = 0x08,
1394 AGG_TX_STATE_LAST_SENT_TTL_MSK = 0x10,
1395 AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK = 0x20,
1396 AGG_TX_STATE_LAST_SENT_BT_KILL_MSK = 0x40,
1397 AGG_TX_STATE_SCD_QUERY_MSK = 0x80,
1398 AGG_TX_STATE_TEST_BAD_CRC32_MSK = 0x100,
1399 AGG_TX_STATE_RESPONSE_MSK = 0x1ff,
1400 AGG_TX_STATE_DUMP_TX_MSK = 0x200,
1401 AGG_TX_STATE_DELAY_TX_MSK = 0x400
1402};
1403
1404#define AGG_TX_STATUS_MSK 0x00000fff
1405#define AGG_TX_TRY_MSK 0x0000f000
1406#define AGG_TX_TRY_POS 12
1407
1408#define AGG_TX_STATE_LAST_SENT_MSK (AGG_TX_STATE_LAST_SENT_TTL_MSK | \
1409 AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK | \
1410 AGG_TX_STATE_LAST_SENT_BT_KILL_MSK)
1411
1412
1413#define AGG_TX_STATE_TRY_CNT_POS 12
1414#define AGG_TX_STATE_TRY_CNT_MSK 0xf000
1415
1416
1417#define AGG_TX_STATE_SEQ_NUM_POS 16
1418#define AGG_TX_STATE_SEQ_NUM_MSK 0xffff0000
1419
1420
1421
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1440
1441
1442struct agg_tx_status {
1443 __le16 status;
1444 __le16 sequence;
1445} __packed;
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457#define IWL50_TX_RES_INIT_RATE_INDEX_POS 0
1458#define IWL50_TX_RES_INIT_RATE_INDEX_MSK 0x0f
1459#define IWL50_TX_RES_RATE_TABLE_COLOR_POS 4
1460#define IWL50_TX_RES_RATE_TABLE_COLOR_MSK 0x70
1461#define IWL50_TX_RES_INV_RATE_INDEX_MSK 0x80
1462
1463
1464#define IWLAGN_TX_RES_TID_POS 0
1465#define IWLAGN_TX_RES_TID_MSK 0x0f
1466#define IWLAGN_TX_RES_RA_POS 4
1467#define IWLAGN_TX_RES_RA_MSK 0xf0
1468
1469struct iwlagn_tx_resp {
1470 u8 frame_count;
1471 u8 bt_kill_count;
1472 u8 failure_rts;
1473 u8 failure_frame;
1474
1475
1476
1477 __le32 rate_n_flags;
1478
1479
1480
1481 __le16 wireless_media_time;
1482
1483 u8 pa_status;
1484 u8 pa_integ_res_a[3];
1485 u8 pa_integ_res_b[3];
1486 u8 pa_integ_res_C[3];
1487
1488 __le32 tfd_info;
1489 __le16 seq_ctl;
1490 __le16 byte_cnt;
1491 u8 tlc_info;
1492 u8 ra_tid;
1493 __le16 frame_ctrl;
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507 struct agg_tx_status status;
1508
1509} __packed;
1510
1511
1512
1513
1514
1515struct iwl_compressed_ba_resp {
1516 __le32 sta_addr_lo32;
1517 __le16 sta_addr_hi16;
1518 __le16 reserved;
1519
1520
1521 u8 sta_id;
1522 u8 tid;
1523 __le16 seq_ctl;
1524 __le64 bitmap;
1525 __le16 scd_flow;
1526 __le16 scd_ssn;
1527 u8 txed;
1528 u8 txed_2_done;
1529 __le16 reserved1;
1530} __packed;
1531
1532
1533
1534
1535
1536
1537
1538#define LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK (1 << 0)
1539
1540
1541#define LINK_QUAL_AC_NUM AC_NUM
1542
1543
1544#define LINK_QUAL_MAX_RETRY_NUM 16
1545
1546
1547#define LINK_QUAL_ANT_A_MSK (1 << 0)
1548#define LINK_QUAL_ANT_B_MSK (1 << 1)
1549#define LINK_QUAL_ANT_MSK (LINK_QUAL_ANT_A_MSK|LINK_QUAL_ANT_B_MSK)
1550
1551
1552
1553
1554
1555
1556
1557struct iwl_link_qual_general_params {
1558 u8 flags;
1559
1560
1561 u8 mimo_delimiter;
1562
1563
1564 u8 single_stream_ant_msk;
1565
1566
1567 u8 dual_stream_ant_msk;
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580 u8 start_rate_index[LINK_QUAL_AC_NUM];
1581} __packed;
1582
1583#define LINK_QUAL_AGG_TIME_LIMIT_DEF (4000)
1584#define LINK_QUAL_AGG_TIME_LIMIT_MAX (8000)
1585#define LINK_QUAL_AGG_TIME_LIMIT_MIN (100)
1586
1587#define LINK_QUAL_AGG_DISABLE_START_DEF (3)
1588#define LINK_QUAL_AGG_DISABLE_START_MAX (255)
1589#define LINK_QUAL_AGG_DISABLE_START_MIN (0)
1590
1591#define LINK_QUAL_AGG_FRAME_LIMIT_DEF (63)
1592#define LINK_QUAL_AGG_FRAME_LIMIT_MAX (63)
1593#define LINK_QUAL_AGG_FRAME_LIMIT_MIN (0)
1594
1595
1596
1597
1598
1599
1600struct iwl_link_qual_agg_params {
1601
1602
1603
1604
1605
1606 __le16 agg_time_limit;
1607
1608
1609
1610
1611
1612
1613
1614 u8 agg_dis_start_th;
1615
1616
1617
1618
1619
1620
1621 u8 agg_frame_cnt_limit;
1622
1623 __le32 reserved;
1624} __packed;
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1811
1812
1813
1814struct iwl_link_quality_cmd {
1815
1816
1817 u8 sta_id;
1818 u8 reserved1;
1819 __le16 control;
1820 struct iwl_link_qual_general_params general_params;
1821 struct iwl_link_qual_agg_params agg_params;
1822
1823
1824
1825
1826
1827
1828 struct {
1829 __le32 rate_n_flags;
1830 } rs_table[LINK_QUAL_MAX_RETRY_NUM];
1831 __le32 reserved2;
1832} __packed;
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843#define BT_COEX_DISABLE (0x0)
1844#define BT_ENABLE_CHANNEL_ANNOUNCE BIT(0)
1845#define BT_ENABLE_PRIORITY BIT(1)
1846#define BT_ENABLE_2_WIRE BIT(2)
1847
1848#define BT_COEX_DISABLE (0x0)
1849#define BT_COEX_ENABLE (BT_ENABLE_CHANNEL_ANNOUNCE | BT_ENABLE_PRIORITY)
1850
1851#define BT_LEAD_TIME_MIN (0x0)
1852#define BT_LEAD_TIME_DEF (0x1E)
1853#define BT_LEAD_TIME_MAX (0xFF)
1854
1855#define BT_MAX_KILL_MIN (0x1)
1856#define BT_MAX_KILL_DEF (0x5)
1857#define BT_MAX_KILL_MAX (0xFF)
1858
1859#define BT_DURATION_LIMIT_DEF 625
1860#define BT_DURATION_LIMIT_MAX 1250
1861#define BT_DURATION_LIMIT_MIN 625
1862
1863#define BT_ON_THRESHOLD_DEF 4
1864#define BT_ON_THRESHOLD_MAX 1000
1865#define BT_ON_THRESHOLD_MIN 1
1866
1867#define BT_FRAG_THRESHOLD_DEF 0
1868#define BT_FRAG_THRESHOLD_MAX 0
1869#define BT_FRAG_THRESHOLD_MIN 0
1870
1871#define BT_AGG_THRESHOLD_DEF 1200
1872#define BT_AGG_THRESHOLD_MAX 8000
1873#define BT_AGG_THRESHOLD_MIN 400
1874
1875
1876
1877
1878
1879
1880
1881
1882struct iwl_bt_cmd {
1883 u8 flags;
1884 u8 lead_time;
1885 u8 max_kill;
1886 u8 reserved;
1887 __le32 kill_ack_mask;
1888 __le32 kill_cts_mask;
1889} __packed;
1890
1891#define IWLAGN_BT_FLAG_CHANNEL_INHIBITION BIT(0)
1892
1893#define IWLAGN_BT_FLAG_COEX_MODE_MASK (BIT(3)|BIT(4)|BIT(5))
1894#define IWLAGN_BT_FLAG_COEX_MODE_SHIFT 3
1895#define IWLAGN_BT_FLAG_COEX_MODE_DISABLED 0
1896#define IWLAGN_BT_FLAG_COEX_MODE_LEGACY_2W 1
1897#define IWLAGN_BT_FLAG_COEX_MODE_3W 2
1898#define IWLAGN_BT_FLAG_COEX_MODE_4W 3
1899
1900#define IWLAGN_BT_FLAG_UCODE_DEFAULT BIT(6)
1901
1902#define IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE BIT(7)
1903
1904#define IWLAGN_BT_PSP_MIN_RSSI_THRESHOLD -75
1905#define IWLAGN_BT_PSP_MAX_RSSI_THRESHOLD -65
1906
1907#define IWLAGN_BT_PRIO_BOOST_MAX 0xFF
1908#define IWLAGN_BT_PRIO_BOOST_MIN 0x00
1909#define IWLAGN_BT_PRIO_BOOST_DEFAULT 0xF0
1910#define IWLAGN_BT_PRIO_BOOST_DEFAULT32 0xF0F0F0F0
1911
1912#define IWLAGN_BT_MAX_KILL_DEFAULT 5
1913
1914#define IWLAGN_BT3_T7_DEFAULT 1
1915
1916enum iwl_bt_kill_idx {
1917 IWL_BT_KILL_DEFAULT = 0,
1918 IWL_BT_KILL_OVERRIDE = 1,
1919 IWL_BT_KILL_REDUCE = 2,
1920};
1921
1922#define IWLAGN_BT_KILL_ACK_MASK_DEFAULT cpu_to_le32(0xffff0000)
1923#define IWLAGN_BT_KILL_CTS_MASK_DEFAULT cpu_to_le32(0xffff0000)
1924#define IWLAGN_BT_KILL_ACK_CTS_MASK_SCO cpu_to_le32(0xffffffff)
1925#define IWLAGN_BT_KILL_ACK_CTS_MASK_REDUCE cpu_to_le32(0)
1926
1927#define IWLAGN_BT3_PRIO_SAMPLE_DEFAULT 2
1928
1929#define IWLAGN_BT3_T2_DEFAULT 0xc
1930
1931#define IWLAGN_BT_VALID_ENABLE_FLAGS cpu_to_le16(BIT(0))
1932#define IWLAGN_BT_VALID_BOOST cpu_to_le16(BIT(1))
1933#define IWLAGN_BT_VALID_MAX_KILL cpu_to_le16(BIT(2))
1934#define IWLAGN_BT_VALID_3W_TIMERS cpu_to_le16(BIT(3))
1935#define IWLAGN_BT_VALID_KILL_ACK_MASK cpu_to_le16(BIT(4))
1936#define IWLAGN_BT_VALID_KILL_CTS_MASK cpu_to_le16(BIT(5))
1937#define IWLAGN_BT_VALID_REDUCED_TX_PWR cpu_to_le16(BIT(6))
1938#define IWLAGN_BT_VALID_3W_LUT cpu_to_le16(BIT(7))
1939
1940#define IWLAGN_BT_ALL_VALID_MSK (IWLAGN_BT_VALID_ENABLE_FLAGS | \
1941 IWLAGN_BT_VALID_BOOST | \
1942 IWLAGN_BT_VALID_MAX_KILL | \
1943 IWLAGN_BT_VALID_3W_TIMERS | \
1944 IWLAGN_BT_VALID_KILL_ACK_MASK | \
1945 IWLAGN_BT_VALID_KILL_CTS_MASK | \
1946 IWLAGN_BT_VALID_REDUCED_TX_PWR | \
1947 IWLAGN_BT_VALID_3W_LUT)
1948
1949#define IWLAGN_BT_REDUCED_TX_PWR BIT(0)
1950
1951#define IWLAGN_BT_DECISION_LUT_SIZE 12
1952
1953struct iwl_basic_bt_cmd {
1954 u8 flags;
1955 u8 ledtime;
1956 u8 max_kill;
1957 u8 bt3_timer_t7_value;
1958 __le32 kill_ack_mask;
1959 __le32 kill_cts_mask;
1960 u8 bt3_prio_sample_time;
1961 u8 bt3_timer_t2_value;
1962 __le16 bt4_reaction_time;
1963 __le32 bt3_lookup_table[IWLAGN_BT_DECISION_LUT_SIZE];
1964
1965
1966
1967
1968 u8 reduce_txpower;
1969 u8 reserved;
1970 __le16 valid;
1971};
1972
1973struct iwl_bt_cmd_v1 {
1974 struct iwl_basic_bt_cmd basic;
1975 u8 prio_boost;
1976
1977
1978
1979
1980 u8 tx_prio_boost;
1981 __le16 rx_prio_boost;
1982};
1983
1984struct iwl_bt_cmd_v2 {
1985 struct iwl_basic_bt_cmd basic;
1986 __le32 prio_boost;
1987
1988
1989
1990
1991 u8 reserved;
1992 u8 tx_prio_boost;
1993 __le16 rx_prio_boost;
1994};
1995
1996#define IWLAGN_BT_SCO_ACTIVE cpu_to_le32(BIT(0))
1997
1998struct iwlagn_bt_sco_cmd {
1999 __le32 flags;
2000};
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011#define MEASUREMENT_FILTER_FLAG (RXON_FILTER_PROMISC_MSK | \
2012 RXON_FILTER_CTL2HOST_MSK | \
2013 RXON_FILTER_ACCEPT_GRP_MSK | \
2014 RXON_FILTER_DIS_DECRYPT_MSK | \
2015 RXON_FILTER_DIS_GRP_DECRYPT_MSK | \
2016 RXON_FILTER_ASSOC_MSK | \
2017 RXON_FILTER_BCON_AWARE_MSK)
2018
2019struct iwl_measure_channel {
2020 __le32 duration;
2021
2022 u8 channel;
2023 u8 type;
2024 __le16 reserved;
2025} __packed;
2026
2027
2028
2029
2030struct iwl_spectrum_cmd {
2031 __le16 len;
2032 u8 token;
2033 u8 id;
2034 u8 origin;
2035 u8 periodic;
2036 __le16 path_loss_timeout;
2037 __le32 start_time;
2038 __le32 reserved2;
2039 __le32 flags;
2040 __le32 filter_flags;
2041 __le16 channel_count;
2042 __le16 reserved3;
2043 struct iwl_measure_channel channels[10];
2044} __packed;
2045
2046
2047
2048
2049struct iwl_spectrum_resp {
2050 u8 token;
2051 u8 id;
2052 __le16 status;
2053
2054
2055} __packed;
2056
2057enum iwl_measurement_state {
2058 IWL_MEASUREMENT_START = 0,
2059 IWL_MEASUREMENT_STOP = 1,
2060};
2061
2062enum iwl_measurement_status {
2063 IWL_MEASUREMENT_OK = 0,
2064 IWL_MEASUREMENT_CONCURRENT = 1,
2065 IWL_MEASUREMENT_CSA_CONFLICT = 2,
2066 IWL_MEASUREMENT_TGH_CONFLICT = 3,
2067
2068 IWL_MEASUREMENT_STOPPED = 6,
2069 IWL_MEASUREMENT_TIMEOUT = 7,
2070 IWL_MEASUREMENT_PERIODIC_FAILED = 8,
2071};
2072
2073#define NUM_ELEMENTS_IN_HISTOGRAM 8
2074
2075struct iwl_measurement_histogram {
2076 __le32 ofdm[NUM_ELEMENTS_IN_HISTOGRAM];
2077 __le32 cck[NUM_ELEMENTS_IN_HISTOGRAM];
2078} __packed;
2079
2080
2081struct iwl_measurement_cca_counters {
2082 __le32 ofdm;
2083 __le32 cck;
2084} __packed;
2085
2086enum iwl_measure_type {
2087 IWL_MEASURE_BASIC = (1 << 0),
2088 IWL_MEASURE_CHANNEL_LOAD = (1 << 1),
2089 IWL_MEASURE_HISTOGRAM_RPI = (1 << 2),
2090 IWL_MEASURE_HISTOGRAM_NOISE = (1 << 3),
2091 IWL_MEASURE_FRAME = (1 << 4),
2092
2093 IWL_MEASURE_IDLE = (1 << 7),
2094};
2095
2096
2097
2098
2099struct iwl_spectrum_notification {
2100 u8 id;
2101 u8 token;
2102 u8 channel_index;
2103 u8 state;
2104 __le32 start_time;
2105 u8 band;
2106 u8 channel;
2107 u8 type;
2108 u8 reserved1;
2109
2110
2111 __le32 cca_ofdm;
2112 __le32 cca_cck;
2113 __le32 cca_time;
2114 u8 basic_type;
2115
2116 u8 reserved2[3];
2117 struct iwl_measurement_histogram histogram;
2118 __le32 stop_time;
2119 __le32 status;
2120} __packed;
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
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2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163#define IWL_POWER_VEC_SIZE 5
2164
2165#define IWL_POWER_DRIVER_ALLOW_SLEEP_MSK cpu_to_le16(BIT(0))
2166#define IWL_POWER_POWER_SAVE_ENA_MSK cpu_to_le16(BIT(0))
2167#define IWL_POWER_POWER_MANAGEMENT_ENA_MSK cpu_to_le16(BIT(1))
2168#define IWL_POWER_SLEEP_OVER_DTIM_MSK cpu_to_le16(BIT(2))
2169#define IWL_POWER_PCI_PM_MSK cpu_to_le16(BIT(3))
2170#define IWL_POWER_FAST_PD cpu_to_le16(BIT(4))
2171#define IWL_POWER_BEACON_FILTERING cpu_to_le16(BIT(5))
2172#define IWL_POWER_SHADOW_REG_ENA cpu_to_le16(BIT(6))
2173#define IWL_POWER_CT_KILL_SET cpu_to_le16(BIT(7))
2174#define IWL_POWER_BT_SCO_ENA cpu_to_le16(BIT(8))
2175#define IWL_POWER_ADVANCE_PM_ENA_MSK cpu_to_le16(BIT(9))
2176
2177struct iwl_powertable_cmd {
2178 __le16 flags;
2179 u8 keep_alive_seconds;
2180 u8 debug_flags;
2181 __le32 rx_data_timeout;
2182 __le32 tx_data_timeout;
2183 __le32 sleep_interval[IWL_POWER_VEC_SIZE];
2184 __le32 keep_alive_beacons;
2185} __packed;
2186
2187
2188
2189
2190
2191struct iwl_sleep_notification {
2192 u8 pm_sleep_mode;
2193 u8 pm_wakeup_src;
2194 __le16 reserved;
2195 __le32 sleep_time;
2196 __le32 tsf_low;
2197 __le32 bcon_timer;
2198} __packed;
2199
2200
2201enum {
2202 IWL_PM_NO_SLEEP = 0,
2203 IWL_PM_SLP_MAC = 1,
2204 IWL_PM_SLP_FULL_MAC_UNASSOCIATE = 2,
2205 IWL_PM_SLP_FULL_MAC_CARD_STATE = 3,
2206 IWL_PM_SLP_PHY = 4,
2207 IWL_PM_SLP_REPENT = 5,
2208 IWL_PM_WAKEUP_BY_TIMER = 6,
2209 IWL_PM_WAKEUP_BY_DRIVER = 7,
2210 IWL_PM_WAKEUP_BY_RFKILL = 8,
2211
2212 IWL_PM_NUM_OF_MODES = 12,
2213};
2214
2215
2216
2217
2218#define CARD_STATE_CMD_DISABLE 0x00
2219#define CARD_STATE_CMD_ENABLE 0x01
2220#define CARD_STATE_CMD_HALT 0x02
2221struct iwl_card_state_cmd {
2222 __le32 status;
2223} __packed;
2224
2225
2226
2227
2228struct iwl_card_state_notif {
2229 __le32 flags;
2230} __packed;
2231
2232#define HW_CARD_DISABLED 0x01
2233#define SW_CARD_DISABLED 0x02
2234#define CT_CARD_DISABLED 0x04
2235#define RXON_CARD_DISABLED 0x10
2236
2237struct iwl_ct_kill_config {
2238 __le32 reserved;
2239 __le32 critical_temperature_M;
2240 __le32 critical_temperature_R;
2241} __packed;
2242
2243
2244struct iwl_ct_kill_throttling_config {
2245 __le32 critical_temperature_exit;
2246 __le32 reserved;
2247 __le32 critical_temperature_enter;
2248} __packed;
2249
2250
2251
2252
2253
2254
2255
2256#define SCAN_CHANNEL_TYPE_PASSIVE cpu_to_le32(0)
2257#define SCAN_CHANNEL_TYPE_ACTIVE cpu_to_le32(1)
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279struct iwl_scan_channel {
2280
2281
2282
2283
2284
2285
2286
2287 __le32 type;
2288 __le16 channel;
2289 u8 tx_gain;
2290 u8 dsp_atten;
2291 __le16 active_dwell;
2292 __le16 passive_dwell;
2293} __packed;
2294
2295
2296#define IWL_SCAN_PROBE_MASK(n) cpu_to_le32((BIT(n) | (BIT(n) - BIT(1))))
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306struct iwl_ssid_ie {
2307 u8 id;
2308 u8 len;
2309 u8 ssid[32];
2310} __packed;
2311
2312#define PROBE_OPTION_MAX 20
2313#define TX_CMD_LIFE_TIME_INFINITE cpu_to_le32(0xFFFFFFFF)
2314#define IWL_GOOD_CRC_TH_DISABLED 0
2315#define IWL_GOOD_CRC_TH_DEFAULT cpu_to_le16(1)
2316#define IWL_GOOD_CRC_TH_NEVER cpu_to_le16(0xffff)
2317#define IWL_MAX_CMD_SIZE 4096
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372enum iwl_scan_flags {
2373
2374 IWL_SCAN_FLAGS_ACTION_FRAME_TX = BIT(1),
2375
2376};
2377
2378struct iwl_scan_cmd {
2379 __le16 len;
2380 u8 scan_flags;
2381 u8 channel_count;
2382 __le16 quiet_time;
2383
2384 __le16 quiet_plcp_th;
2385 __le16 good_CRC_th;
2386 __le16 rx_chain;
2387 __le32 max_out_time;
2388
2389 __le32 suspend_time;
2390
2391
2392 __le32 flags;
2393 __le32 filter_flags;
2394
2395
2396
2397 struct iwl_tx_cmd tx_cmd;
2398
2399
2400 struct iwl_ssid_ie direct_scan[PROBE_OPTION_MAX];
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417 u8 data[0];
2418} __packed;
2419
2420
2421#define CAN_ABORT_STATUS cpu_to_le32(0x1)
2422
2423#define ABORT_STATUS 0x2
2424
2425
2426
2427
2428struct iwl_scanreq_notification {
2429 __le32 status;
2430} __packed;
2431
2432
2433
2434
2435struct iwl_scanstart_notification {
2436 __le32 tsf_low;
2437 __le32 tsf_high;
2438 __le32 beacon_timer;
2439 u8 channel;
2440 u8 band;
2441 u8 reserved[2];
2442 __le32 status;
2443} __packed;
2444
2445#define SCAN_OWNER_STATUS 0x1
2446#define MEASURE_OWNER_STATUS 0x2
2447
2448#define IWL_PROBE_STATUS_OK 0
2449#define IWL_PROBE_STATUS_TX_FAILED BIT(0)
2450
2451#define IWL_PROBE_STATUS_FAIL_TTL BIT(1)
2452#define IWL_PROBE_STATUS_FAIL_BT BIT(2)
2453
2454#define NUMBER_OF_STATISTICS 1
2455
2456
2457
2458struct iwl_scanresults_notification {
2459 u8 channel;
2460 u8 band;
2461 u8 probe_status;
2462 u8 num_probe_not_sent;
2463 __le32 tsf_low;
2464 __le32 tsf_high;
2465 __le32 statistics[NUMBER_OF_STATISTICS];
2466} __packed;
2467
2468
2469
2470
2471struct iwl_scancomplete_notification {
2472 u8 scanned_channels;
2473 u8 status;
2474 u8 bt_status;
2475 u8 last_channel;
2476 __le32 tsf_low;
2477 __le32 tsf_high;
2478} __packed;
2479
2480
2481
2482
2483
2484
2485
2486
2487enum iwl_ibss_manager {
2488 IWL_NOT_IBSS_MANAGER = 0,
2489 IWL_IBSS_MANAGER = 1,
2490};
2491
2492
2493
2494
2495
2496struct iwlagn_beacon_notif {
2497 struct iwlagn_tx_resp beacon_notify_hdr;
2498 __le32 low_tsf;
2499 __le32 high_tsf;
2500 __le32 ibss_mgr_status;
2501} __packed;
2502
2503
2504
2505
2506
2507struct iwl_tx_beacon_cmd {
2508 struct iwl_tx_cmd tx;
2509 __le16 tim_idx;
2510 u8 tim_size;
2511 u8 reserved1;
2512 struct ieee80211_hdr frame[0];
2513} __packed;
2514
2515
2516
2517
2518
2519
2520
2521#define IWL_TEMP_CONVERT 260
2522
2523#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
2524#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
2525#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
2526
2527
2528struct rate_histogram {
2529 union {
2530 __le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
2531 __le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
2532 __le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
2533 } success;
2534 union {
2535 __le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
2536 __le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
2537 __le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
2538 } failed;
2539} __packed;
2540
2541
2542
2543struct statistics_dbg {
2544 __le32 burst_check;
2545 __le32 burst_count;
2546 __le32 wait_for_silence_timeout_cnt;
2547 __le32 reserved[3];
2548} __packed;
2549
2550struct statistics_rx_phy {
2551 __le32 ina_cnt;
2552 __le32 fina_cnt;
2553 __le32 plcp_err;
2554 __le32 crc32_err;
2555 __le32 overrun_err;
2556 __le32 early_overrun_err;
2557 __le32 crc32_good;
2558 __le32 false_alarm_cnt;
2559 __le32 fina_sync_err_cnt;
2560 __le32 sfd_timeout;
2561 __le32 fina_timeout;
2562 __le32 unresponded_rts;
2563 __le32 rxe_frame_limit_overrun;
2564 __le32 sent_ack_cnt;
2565 __le32 sent_cts_cnt;
2566 __le32 sent_ba_rsp_cnt;
2567 __le32 dsp_self_kill;
2568 __le32 mh_format_err;
2569 __le32 re_acq_main_rssi_sum;
2570 __le32 reserved3;
2571} __packed;
2572
2573struct statistics_rx_ht_phy {
2574 __le32 plcp_err;
2575 __le32 overrun_err;
2576 __le32 early_overrun_err;
2577 __le32 crc32_good;
2578 __le32 crc32_err;
2579 __le32 mh_format_err;
2580 __le32 agg_crc32_good;
2581 __le32 agg_mpdu_cnt;
2582 __le32 agg_cnt;
2583 __le32 unsupport_mcs;
2584} __packed;
2585
2586#define INTERFERENCE_DATA_AVAILABLE cpu_to_le32(1)
2587
2588struct statistics_rx_non_phy {
2589 __le32 bogus_cts;
2590 __le32 bogus_ack;
2591 __le32 non_bssid_frames;
2592
2593 __le32 filtered_frames;
2594
2595 __le32 non_channel_beacons;
2596
2597 __le32 channel_beacons;
2598
2599 __le32 num_missed_bcon;
2600 __le32 adc_rx_saturation_time;
2601
2602 __le32 ina_detection_search_time;
2603
2604 __le32 beacon_silence_rssi_a;
2605 __le32 beacon_silence_rssi_b;
2606 __le32 beacon_silence_rssi_c;
2607 __le32 interference_data_flag;
2608
2609
2610 __le32 channel_load;
2611 __le32 dsp_false_alarms;
2612
2613 __le32 beacon_rssi_a;
2614 __le32 beacon_rssi_b;
2615 __le32 beacon_rssi_c;
2616 __le32 beacon_energy_a;
2617 __le32 beacon_energy_b;
2618 __le32 beacon_energy_c;
2619} __packed;
2620
2621struct statistics_rx_non_phy_bt {
2622 struct statistics_rx_non_phy common;
2623
2624 __le32 num_bt_kills;
2625 __le32 reserved[2];
2626} __packed;
2627
2628struct statistics_rx {
2629 struct statistics_rx_phy ofdm;
2630 struct statistics_rx_phy cck;
2631 struct statistics_rx_non_phy general;
2632 struct statistics_rx_ht_phy ofdm_ht;
2633} __packed;
2634
2635struct statistics_rx_bt {
2636 struct statistics_rx_phy ofdm;
2637 struct statistics_rx_phy cck;
2638 struct statistics_rx_non_phy_bt general;
2639 struct statistics_rx_ht_phy ofdm_ht;
2640} __packed;
2641
2642
2643
2644
2645
2646
2647
2648
2649struct statistics_tx_power {
2650 u8 ant_a;
2651 u8 ant_b;
2652 u8 ant_c;
2653 u8 reserved;
2654} __packed;
2655
2656struct statistics_tx_non_phy_agg {
2657 __le32 ba_timeout;
2658 __le32 ba_reschedule_frames;
2659 __le32 scd_query_agg_frame_cnt;
2660 __le32 scd_query_no_agg;
2661 __le32 scd_query_agg;
2662 __le32 scd_query_mismatch;
2663 __le32 frame_not_ready;
2664 __le32 underrun;
2665 __le32 bt_prio_kill;
2666 __le32 rx_ba_rsp_cnt;
2667} __packed;
2668
2669struct statistics_tx {
2670 __le32 preamble_cnt;
2671 __le32 rx_detected_cnt;
2672 __le32 bt_prio_defer_cnt;
2673 __le32 bt_prio_kill_cnt;
2674 __le32 few_bytes_cnt;
2675 __le32 cts_timeout;
2676 __le32 ack_timeout;
2677 __le32 expected_ack_cnt;
2678 __le32 actual_ack_cnt;
2679 __le32 dump_msdu_cnt;
2680 __le32 burst_abort_next_frame_mismatch_cnt;
2681 __le32 burst_abort_missing_next_frame_cnt;
2682 __le32 cts_timeout_collision;
2683 __le32 ack_or_ba_timeout_collision;
2684 struct statistics_tx_non_phy_agg agg;
2685
2686
2687
2688
2689
2690 struct statistics_tx_power tx_power;
2691 __le32 reserved1;
2692} __packed;
2693
2694
2695struct statistics_div {
2696 __le32 tx_on_a;
2697 __le32 tx_on_b;
2698 __le32 exec_time;
2699 __le32 probe_time;
2700 __le32 reserved1;
2701 __le32 reserved2;
2702} __packed;
2703
2704struct statistics_general_common {
2705 __le32 temperature;
2706 __le32 temperature_m;
2707 struct statistics_dbg dbg;
2708 __le32 sleep_time;
2709 __le32 slots_out;
2710 __le32 slots_idle;
2711 __le32 ttl_timestamp;
2712 struct statistics_div div;
2713 __le32 rx_enable_counter;
2714
2715
2716
2717
2718
2719 __le32 num_of_sos_states;
2720} __packed;
2721
2722struct statistics_bt_activity {
2723
2724 __le32 hi_priority_tx_req_cnt;
2725 __le32 hi_priority_tx_denied_cnt;
2726 __le32 lo_priority_tx_req_cnt;
2727 __le32 lo_priority_tx_denied_cnt;
2728
2729 __le32 hi_priority_rx_req_cnt;
2730 __le32 hi_priority_rx_denied_cnt;
2731 __le32 lo_priority_rx_req_cnt;
2732 __le32 lo_priority_rx_denied_cnt;
2733} __packed;
2734
2735struct statistics_general {
2736 struct statistics_general_common common;
2737 __le32 reserved2;
2738 __le32 reserved3;
2739} __packed;
2740
2741struct statistics_general_bt {
2742 struct statistics_general_common common;
2743 struct statistics_bt_activity activity;
2744 __le32 reserved2;
2745 __le32 reserved3;
2746} __packed;
2747
2748#define UCODE_STATISTICS_CLEAR_MSK (0x1 << 0)
2749#define UCODE_STATISTICS_FREQUENCY_MSK (0x1 << 1)
2750#define UCODE_STATISTICS_NARROW_BAND_MSK (0x1 << 2)
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767#define IWL_STATS_CONF_CLEAR_STATS cpu_to_le32(0x1)
2768#define IWL_STATS_CONF_DISABLE_NOTIF cpu_to_le32(0x2)
2769struct iwl_statistics_cmd {
2770 __le32 configuration_flags;
2771} __packed;
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788#define STATISTICS_REPLY_FLG_BAND_24G_MSK cpu_to_le32(0x2)
2789#define STATISTICS_REPLY_FLG_HT40_MODE_MSK cpu_to_le32(0x8)
2790
2791struct iwl_notif_statistics {
2792 __le32 flag;
2793 struct statistics_rx rx;
2794 struct statistics_tx tx;
2795 struct statistics_general general;
2796} __packed;
2797
2798struct iwl_bt_notif_statistics {
2799 __le32 flag;
2800 struct statistics_rx_bt rx;
2801 struct statistics_tx tx;
2802 struct statistics_general_bt general;
2803} __packed;
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825#define IWL_MISSED_BEACON_THRESHOLD_MIN (1)
2826#define IWL_MISSED_BEACON_THRESHOLD_DEF (5)
2827#define IWL_MISSED_BEACON_THRESHOLD_MAX IWL_MISSED_BEACON_THRESHOLD_DEF
2828
2829struct iwl_missed_beacon_notif {
2830 __le32 consecutive_missed_beacons;
2831 __le32 total_missed_becons;
2832 __le32 num_expected_beacons;
2833 __le32 num_recvd_beacons;
2834} __packed;
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
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2862
2863
2864
2865
2866
2867
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2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009#define HD_TABLE_SIZE (11)
3010#define HD_MIN_ENERGY_CCK_DET_INDEX (0)
3011#define HD_MIN_ENERGY_OFDM_DET_INDEX (1)
3012#define HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX (2)
3013#define HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX (3)
3014#define HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX (4)
3015#define HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX (5)
3016#define HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX (6)
3017#define HD_BARKER_CORR_TH_ADD_MIN_INDEX (7)
3018#define HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX (8)
3019#define HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX (9)
3020#define HD_OFDM_ENERGY_TH_IN_INDEX (10)
3021
3022
3023
3024
3025#define HD_INA_NON_SQUARE_DET_OFDM_INDEX (11)
3026#define HD_INA_NON_SQUARE_DET_CCK_INDEX (12)
3027#define HD_CORR_11_INSTEAD_OF_CORR_9_EN_INDEX (13)
3028#define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_INDEX (14)
3029#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_INDEX (15)
3030#define HD_OFDM_NON_SQUARE_DET_SLOPE_INDEX (16)
3031#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_INDEX (17)
3032#define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_INDEX (18)
3033#define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_INDEX (19)
3034#define HD_CCK_NON_SQUARE_DET_SLOPE_INDEX (20)
3035#define HD_CCK_NON_SQUARE_DET_INTERCEPT_INDEX (21)
3036#define HD_RESERVED (22)
3037
3038
3039#define ENHANCE_HD_TABLE_SIZE (23)
3040
3041
3042#define ENHANCE_HD_TABLE_ENTRIES (ENHANCE_HD_TABLE_SIZE - HD_TABLE_SIZE)
3043
3044#define HD_INA_NON_SQUARE_DET_OFDM_DATA_V1 cpu_to_le16(0)
3045#define HD_INA_NON_SQUARE_DET_CCK_DATA_V1 cpu_to_le16(0)
3046#define HD_CORR_11_INSTEAD_OF_CORR_9_EN_DATA_V1 cpu_to_le16(0)
3047#define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_DATA_V1 cpu_to_le16(668)
3048#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V1 cpu_to_le16(4)
3049#define HD_OFDM_NON_SQUARE_DET_SLOPE_DATA_V1 cpu_to_le16(486)
3050#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_DATA_V1 cpu_to_le16(37)
3051#define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_DATA_V1 cpu_to_le16(853)
3052#define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V1 cpu_to_le16(4)
3053#define HD_CCK_NON_SQUARE_DET_SLOPE_DATA_V1 cpu_to_le16(476)
3054#define HD_CCK_NON_SQUARE_DET_INTERCEPT_DATA_V1 cpu_to_le16(99)
3055
3056#define HD_INA_NON_SQUARE_DET_OFDM_DATA_V2 cpu_to_le16(1)
3057#define HD_INA_NON_SQUARE_DET_CCK_DATA_V2 cpu_to_le16(1)
3058#define HD_CORR_11_INSTEAD_OF_CORR_9_EN_DATA_V2 cpu_to_le16(1)
3059#define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_DATA_V2 cpu_to_le16(600)
3060#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V2 cpu_to_le16(40)
3061#define HD_OFDM_NON_SQUARE_DET_SLOPE_DATA_V2 cpu_to_le16(486)
3062#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_DATA_V2 cpu_to_le16(45)
3063#define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_DATA_V2 cpu_to_le16(853)
3064#define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V2 cpu_to_le16(60)
3065#define HD_CCK_NON_SQUARE_DET_SLOPE_DATA_V2 cpu_to_le16(476)
3066#define HD_CCK_NON_SQUARE_DET_INTERCEPT_DATA_V2 cpu_to_le16(99)
3067
3068
3069
3070#define SENSITIVITY_CMD_CONTROL_DEFAULT_TABLE cpu_to_le16(0)
3071#define SENSITIVITY_CMD_CONTROL_WORK_TABLE cpu_to_le16(1)
3072
3073
3074
3075
3076
3077
3078
3079
3080struct iwl_sensitivity_cmd {
3081 __le16 control;
3082 __le16 table[HD_TABLE_SIZE];
3083} __packed;
3084
3085
3086
3087
3088struct iwl_enhance_sensitivity_cmd {
3089 __le16 control;
3090 __le16 enhance_table[ENHANCE_HD_TABLE_SIZE];
3091} __packed;
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150enum {
3151 IWL_PHY_CALIBRATE_DC_CMD = 8,
3152 IWL_PHY_CALIBRATE_LO_CMD = 9,
3153 IWL_PHY_CALIBRATE_TX_IQ_CMD = 11,
3154 IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD = 15,
3155 IWL_PHY_CALIBRATE_BASE_BAND_CMD = 16,
3156 IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD = 17,
3157 IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD = 18,
3158};
3159
3160
3161
3162
3163enum iwl_ucode_calib_cfg {
3164 IWL_CALIB_CFG_RX_BB_IDX = BIT(0),
3165 IWL_CALIB_CFG_DC_IDX = BIT(1),
3166 IWL_CALIB_CFG_LO_IDX = BIT(2),
3167 IWL_CALIB_CFG_TX_IQ_IDX = BIT(3),
3168 IWL_CALIB_CFG_RX_IQ_IDX = BIT(4),
3169 IWL_CALIB_CFG_NOISE_IDX = BIT(5),
3170 IWL_CALIB_CFG_CRYSTAL_IDX = BIT(6),
3171 IWL_CALIB_CFG_TEMPERATURE_IDX = BIT(7),
3172 IWL_CALIB_CFG_PAPD_IDX = BIT(8),
3173 IWL_CALIB_CFG_SENSITIVITY_IDX = BIT(9),
3174 IWL_CALIB_CFG_TX_PWR_IDX = BIT(10),
3175};
3176
3177#define IWL_CALIB_INIT_CFG_ALL cpu_to_le32(IWL_CALIB_CFG_RX_BB_IDX | \
3178 IWL_CALIB_CFG_DC_IDX | \
3179 IWL_CALIB_CFG_LO_IDX | \
3180 IWL_CALIB_CFG_TX_IQ_IDX | \
3181 IWL_CALIB_CFG_RX_IQ_IDX | \
3182 IWL_CALIB_CFG_CRYSTAL_IDX)
3183
3184#define IWL_CALIB_RT_CFG_ALL cpu_to_le32(IWL_CALIB_CFG_RX_BB_IDX | \
3185 IWL_CALIB_CFG_DC_IDX | \
3186 IWL_CALIB_CFG_LO_IDX | \
3187 IWL_CALIB_CFG_TX_IQ_IDX | \
3188 IWL_CALIB_CFG_RX_IQ_IDX | \
3189 IWL_CALIB_CFG_TEMPERATURE_IDX | \
3190 IWL_CALIB_CFG_PAPD_IDX | \
3191 IWL_CALIB_CFG_TX_PWR_IDX | \
3192 IWL_CALIB_CFG_CRYSTAL_IDX)
3193
3194#define IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK cpu_to_le32(BIT(0))
3195
3196struct iwl_calib_cfg_elmnt_s {
3197 __le32 is_enable;
3198 __le32 start;
3199 __le32 send_res;
3200 __le32 apply_res;
3201 __le32 reserved;
3202} __packed;
3203
3204struct iwl_calib_cfg_status_s {
3205 struct iwl_calib_cfg_elmnt_s once;
3206 struct iwl_calib_cfg_elmnt_s perd;
3207 __le32 flags;
3208} __packed;
3209
3210struct iwl_calib_cfg_cmd {
3211 struct iwl_calib_cfg_status_s ucd_calib_cfg;
3212 struct iwl_calib_cfg_status_s drv_calib_cfg;
3213 __le32 reserved1;
3214} __packed;
3215
3216struct iwl_calib_hdr {
3217 u8 op_code;
3218 u8 first_group;
3219 u8 groups_num;
3220 u8 data_valid;
3221} __packed;
3222
3223struct iwl_calib_cmd {
3224 struct iwl_calib_hdr hdr;
3225 u8 data[0];
3226} __packed;
3227
3228struct iwl_calib_xtal_freq_cmd {
3229 struct iwl_calib_hdr hdr;
3230 u8 cap_pin1;
3231 u8 cap_pin2;
3232 u8 pad[2];
3233} __packed;
3234
3235#define DEFAULT_RADIO_SENSOR_OFFSET cpu_to_le16(2700)
3236struct iwl_calib_temperature_offset_cmd {
3237 struct iwl_calib_hdr hdr;
3238 __le16 radio_sensor_offset;
3239 __le16 reserved;
3240} __packed;
3241
3242struct iwl_calib_temperature_offset_v2_cmd {
3243 struct iwl_calib_hdr hdr;
3244 __le16 radio_sensor_offset_high;
3245 __le16 radio_sensor_offset_low;
3246 __le16 burntVoltageRef;
3247 __le16 reserved;
3248} __packed;
3249
3250
3251struct iwl_calib_chain_noise_reset_cmd {
3252 struct iwl_calib_hdr hdr;
3253 u8 data[0];
3254};
3255
3256
3257struct iwl_calib_chain_noise_gain_cmd {
3258 struct iwl_calib_hdr hdr;
3259 u8 delta_gain_1;
3260 u8 delta_gain_2;
3261 u8 pad[2];
3262} __packed;
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277struct iwl_led_cmd {
3278 __le32 interval;
3279 u8 id;
3280 u8 off;
3281
3282 u8 on;
3283
3284 u8 reserved;
3285} __packed;
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298#define COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG (0x1)
3299#define COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG (0x2)
3300#define COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG (0x4)
3301
3302#define COEX_CU_UNASSOC_IDLE_RP 4
3303#define COEX_CU_UNASSOC_MANUAL_SCAN_RP 4
3304#define COEX_CU_UNASSOC_AUTO_SCAN_RP 4
3305#define COEX_CU_CALIBRATION_RP 4
3306#define COEX_CU_PERIODIC_CALIBRATION_RP 4
3307#define COEX_CU_CONNECTION_ESTAB_RP 4
3308#define COEX_CU_ASSOCIATED_IDLE_RP 4
3309#define COEX_CU_ASSOC_MANUAL_SCAN_RP 4
3310#define COEX_CU_ASSOC_AUTO_SCAN_RP 4
3311#define COEX_CU_ASSOC_ACTIVE_LEVEL_RP 4
3312#define COEX_CU_RF_ON_RP 6
3313#define COEX_CU_RF_OFF_RP 4
3314#define COEX_CU_STAND_ALONE_DEBUG_RP 6
3315#define COEX_CU_IPAN_ASSOC_LEVEL_RP 4
3316#define COEX_CU_RSRVD1_RP 4
3317#define COEX_CU_RSRVD2_RP 4
3318
3319#define COEX_CU_UNASSOC_IDLE_WP 3
3320#define COEX_CU_UNASSOC_MANUAL_SCAN_WP 3
3321#define COEX_CU_UNASSOC_AUTO_SCAN_WP 3
3322#define COEX_CU_CALIBRATION_WP 3
3323#define COEX_CU_PERIODIC_CALIBRATION_WP 3
3324#define COEX_CU_CONNECTION_ESTAB_WP 3
3325#define COEX_CU_ASSOCIATED_IDLE_WP 3
3326#define COEX_CU_ASSOC_MANUAL_SCAN_WP 3
3327#define COEX_CU_ASSOC_AUTO_SCAN_WP 3
3328#define COEX_CU_ASSOC_ACTIVE_LEVEL_WP 3
3329#define COEX_CU_RF_ON_WP 3
3330#define COEX_CU_RF_OFF_WP 3
3331#define COEX_CU_STAND_ALONE_DEBUG_WP 6
3332#define COEX_CU_IPAN_ASSOC_LEVEL_WP 3
3333#define COEX_CU_RSRVD1_WP 3
3334#define COEX_CU_RSRVD2_WP 3
3335
3336#define COEX_UNASSOC_IDLE_FLAGS 0
3337#define COEX_UNASSOC_MANUAL_SCAN_FLAGS \
3338 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3339 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3340#define COEX_UNASSOC_AUTO_SCAN_FLAGS \
3341 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3342 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3343#define COEX_CALIBRATION_FLAGS \
3344 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3345 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3346#define COEX_PERIODIC_CALIBRATION_FLAGS 0
3347
3348
3349
3350
3351#define COEX_CONNECTION_ESTAB_FLAGS \
3352 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3353 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG | \
3354 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG)
3355#define COEX_ASSOCIATED_IDLE_FLAGS 0
3356#define COEX_ASSOC_MANUAL_SCAN_FLAGS \
3357 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3358 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3359#define COEX_ASSOC_AUTO_SCAN_FLAGS \
3360 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3361 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3362#define COEX_ASSOC_ACTIVE_LEVEL_FLAGS 0
3363#define COEX_RF_ON_FLAGS 0
3364#define COEX_RF_OFF_FLAGS 0
3365#define COEX_STAND_ALONE_DEBUG_FLAGS \
3366 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3367 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3368#define COEX_IPAN_ASSOC_LEVEL_FLAGS \
3369 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3370 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG | \
3371 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG)
3372#define COEX_RSRVD1_FLAGS 0
3373#define COEX_RSRVD2_FLAGS 0
3374
3375
3376
3377
3378#define COEX_CU_RF_ON_FLAGS \
3379 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3380 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG | \
3381 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG)
3382
3383
3384enum {
3385
3386 COEX_UNASSOC_IDLE = 0,
3387 COEX_UNASSOC_MANUAL_SCAN = 1,
3388 COEX_UNASSOC_AUTO_SCAN = 2,
3389
3390 COEX_CALIBRATION = 3,
3391 COEX_PERIODIC_CALIBRATION = 4,
3392
3393 COEX_CONNECTION_ESTAB = 5,
3394
3395 COEX_ASSOCIATED_IDLE = 6,
3396 COEX_ASSOC_MANUAL_SCAN = 7,
3397 COEX_ASSOC_AUTO_SCAN = 8,
3398 COEX_ASSOC_ACTIVE_LEVEL = 9,
3399
3400 COEX_RF_ON = 10,
3401 COEX_RF_OFF = 11,
3402 COEX_STAND_ALONE_DEBUG = 12,
3403
3404 COEX_IPAN_ASSOC_LEVEL = 13,
3405
3406 COEX_RSRVD1 = 14,
3407 COEX_RSRVD2 = 15,
3408 COEX_NUM_OF_EVENTS = 16
3409};
3410
3411
3412
3413
3414
3415
3416struct iwl_wimax_coex_event_entry {
3417 u8 request_prio;
3418 u8 win_medium_prio;
3419 u8 reserved;
3420 u8 flags;
3421} __packed;
3422
3423
3424
3425
3426#define COEX_FLAGS_STA_TABLE_VALID_MSK (0x1)
3427
3428#define COEX_FLAGS_UNASSOC_WA_UNMASK_MSK (0x4)
3429
3430#define COEX_FLAGS_ASSOC_WA_UNMASK_MSK (0x8)
3431
3432#define COEX_FLAGS_COEX_ENABLE_MSK (0x80)
3433
3434struct iwl_wimax_coex_cmd {
3435 u8 flags;
3436 u8 reserved[3];
3437 struct iwl_wimax_coex_event_entry sta_prio[COEX_NUM_OF_EVENTS];
3438} __packed;
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454#define COEX_MEDIUM_BUSY (0x0)
3455#define COEX_MEDIUM_ACTIVE (0x1)
3456#define COEX_MEDIUM_PRE_RELEASE (0x2)
3457#define COEX_MEDIUM_MSK (0x7)
3458
3459
3460#define COEX_MEDIUM_CHANGED (0x8)
3461#define COEX_MEDIUM_CHANGED_MSK (0x8)
3462#define COEX_MEDIUM_SHIFT (3)
3463
3464struct iwl_coex_medium_notification {
3465 __le32 status;
3466 __le32 events;
3467} __packed;
3468
3469
3470
3471
3472
3473
3474
3475
3476#define COEX_EVENT_REQUEST_MSK (0x1)
3477
3478struct iwl_coex_event_cmd {
3479 u8 flags;
3480 u8 event;
3481 __le16 reserved;
3482} __packed;
3483
3484struct iwl_coex_event_resp {
3485 __le32 status;
3486} __packed;
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498enum iwl_bt_coex_profile_traffic_load {
3499 IWL_BT_COEX_TRAFFIC_LOAD_NONE = 0,
3500 IWL_BT_COEX_TRAFFIC_LOAD_LOW = 1,
3501 IWL_BT_COEX_TRAFFIC_LOAD_HIGH = 2,
3502 IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS = 3,
3503
3504
3505
3506
3507};
3508
3509#define BT_SESSION_ACTIVITY_1_UART_MSG 0x1
3510#define BT_SESSION_ACTIVITY_2_UART_MSG 0x2
3511
3512
3513#define BT_UART_MSG_FRAME1MSGTYPE_POS (0)
3514#define BT_UART_MSG_FRAME1MSGTYPE_MSK \
3515 (0x7 << BT_UART_MSG_FRAME1MSGTYPE_POS)
3516#define BT_UART_MSG_FRAME1SSN_POS (3)
3517#define BT_UART_MSG_FRAME1SSN_MSK \
3518 (0x3 << BT_UART_MSG_FRAME1SSN_POS)
3519#define BT_UART_MSG_FRAME1UPDATEREQ_POS (5)
3520#define BT_UART_MSG_FRAME1UPDATEREQ_MSK \
3521 (0x1 << BT_UART_MSG_FRAME1UPDATEREQ_POS)
3522#define BT_UART_MSG_FRAME1RESERVED_POS (6)
3523#define BT_UART_MSG_FRAME1RESERVED_MSK \
3524 (0x3 << BT_UART_MSG_FRAME1RESERVED_POS)
3525
3526#define BT_UART_MSG_FRAME2OPENCONNECTIONS_POS (0)
3527#define BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK \
3528 (0x3 << BT_UART_MSG_FRAME2OPENCONNECTIONS_POS)
3529#define BT_UART_MSG_FRAME2TRAFFICLOAD_POS (2)
3530#define BT_UART_MSG_FRAME2TRAFFICLOAD_MSK \
3531 (0x3 << BT_UART_MSG_FRAME2TRAFFICLOAD_POS)
3532#define BT_UART_MSG_FRAME2CHLSEQN_POS (4)
3533#define BT_UART_MSG_FRAME2CHLSEQN_MSK \
3534 (0x1 << BT_UART_MSG_FRAME2CHLSEQN_POS)
3535#define BT_UART_MSG_FRAME2INBAND_POS (5)
3536#define BT_UART_MSG_FRAME2INBAND_MSK \
3537 (0x1 << BT_UART_MSG_FRAME2INBAND_POS)
3538#define BT_UART_MSG_FRAME2RESERVED_POS (6)
3539#define BT_UART_MSG_FRAME2RESERVED_MSK \
3540 (0x3 << BT_UART_MSG_FRAME2RESERVED_POS)
3541
3542#define BT_UART_MSG_FRAME3SCOESCO_POS (0)
3543#define BT_UART_MSG_FRAME3SCOESCO_MSK \
3544 (0x1 << BT_UART_MSG_FRAME3SCOESCO_POS)
3545#define BT_UART_MSG_FRAME3SNIFF_POS (1)
3546#define BT_UART_MSG_FRAME3SNIFF_MSK \
3547 (0x1 << BT_UART_MSG_FRAME3SNIFF_POS)
3548#define BT_UART_MSG_FRAME3A2DP_POS (2)
3549#define BT_UART_MSG_FRAME3A2DP_MSK \
3550 (0x1 << BT_UART_MSG_FRAME3A2DP_POS)
3551#define BT_UART_MSG_FRAME3ACL_POS (3)
3552#define BT_UART_MSG_FRAME3ACL_MSK \
3553 (0x1 << BT_UART_MSG_FRAME3ACL_POS)
3554#define BT_UART_MSG_FRAME3MASTER_POS (4)
3555#define BT_UART_MSG_FRAME3MASTER_MSK \
3556 (0x1 << BT_UART_MSG_FRAME3MASTER_POS)
3557#define BT_UART_MSG_FRAME3OBEX_POS (5)
3558#define BT_UART_MSG_FRAME3OBEX_MSK \
3559 (0x1 << BT_UART_MSG_FRAME3OBEX_POS)
3560#define BT_UART_MSG_FRAME3RESERVED_POS (6)
3561#define BT_UART_MSG_FRAME3RESERVED_MSK \
3562 (0x3 << BT_UART_MSG_FRAME3RESERVED_POS)
3563
3564#define BT_UART_MSG_FRAME4IDLEDURATION_POS (0)
3565#define BT_UART_MSG_FRAME4IDLEDURATION_MSK \
3566 (0x3F << BT_UART_MSG_FRAME4IDLEDURATION_POS)
3567#define BT_UART_MSG_FRAME4RESERVED_POS (6)
3568#define BT_UART_MSG_FRAME4RESERVED_MSK \
3569 (0x3 << BT_UART_MSG_FRAME4RESERVED_POS)
3570
3571#define BT_UART_MSG_FRAME5TXACTIVITY_POS (0)
3572#define BT_UART_MSG_FRAME5TXACTIVITY_MSK \
3573 (0x3 << BT_UART_MSG_FRAME5TXACTIVITY_POS)
3574#define BT_UART_MSG_FRAME5RXACTIVITY_POS (2)
3575#define BT_UART_MSG_FRAME5RXACTIVITY_MSK \
3576 (0x3 << BT_UART_MSG_FRAME5RXACTIVITY_POS)
3577#define BT_UART_MSG_FRAME5ESCORETRANSMIT_POS (4)
3578#define BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK \
3579 (0x3 << BT_UART_MSG_FRAME5ESCORETRANSMIT_POS)
3580#define BT_UART_MSG_FRAME5RESERVED_POS (6)
3581#define BT_UART_MSG_FRAME5RESERVED_MSK \
3582 (0x3 << BT_UART_MSG_FRAME5RESERVED_POS)
3583
3584#define BT_UART_MSG_FRAME6SNIFFINTERVAL_POS (0)
3585#define BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK \
3586 (0x1F << BT_UART_MSG_FRAME6SNIFFINTERVAL_POS)
3587#define BT_UART_MSG_FRAME6DISCOVERABLE_POS (5)
3588#define BT_UART_MSG_FRAME6DISCOVERABLE_MSK \
3589 (0x1 << BT_UART_MSG_FRAME6DISCOVERABLE_POS)
3590#define BT_UART_MSG_FRAME6RESERVED_POS (6)
3591#define BT_UART_MSG_FRAME6RESERVED_MSK \
3592 (0x3 << BT_UART_MSG_FRAME6RESERVED_POS)
3593
3594#define BT_UART_MSG_FRAME7SNIFFACTIVITY_POS (0)
3595#define BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK \
3596 (0x7 << BT_UART_MSG_FRAME7SNIFFACTIVITY_POS)
3597#define BT_UART_MSG_FRAME7PAGE_POS (3)
3598#define BT_UART_MSG_FRAME7PAGE_MSK \
3599 (0x1 << BT_UART_MSG_FRAME7PAGE_POS)
3600#define BT_UART_MSG_FRAME7INQUIRY_POS (4)
3601#define BT_UART_MSG_FRAME7INQUIRY_MSK \
3602 (0x1 << BT_UART_MSG_FRAME7INQUIRY_POS)
3603#define BT_UART_MSG_FRAME7CONNECTABLE_POS (5)
3604#define BT_UART_MSG_FRAME7CONNECTABLE_MSK \
3605 (0x1 << BT_UART_MSG_FRAME7CONNECTABLE_POS)
3606#define BT_UART_MSG_FRAME7RESERVED_POS (6)
3607#define BT_UART_MSG_FRAME7RESERVED_MSK \
3608 (0x3 << BT_UART_MSG_FRAME7RESERVED_POS)
3609
3610
3611#define BT_UART_MSG_2_FRAME1RESERVED1_POS (5)
3612#define BT_UART_MSG_2_FRAME1RESERVED1_MSK \
3613 (0x1<<BT_UART_MSG_2_FRAME1RESERVED1_POS)
3614#define BT_UART_MSG_2_FRAME1RESERVED2_POS (6)
3615#define BT_UART_MSG_2_FRAME1RESERVED2_MSK \
3616 (0x3<<BT_UART_MSG_2_FRAME1RESERVED2_POS)
3617
3618#define BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_POS (0)
3619#define BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_MSK \
3620 (0x3F<<BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_POS)
3621#define BT_UART_MSG_2_FRAME2RESERVED_POS (6)
3622#define BT_UART_MSG_2_FRAME2RESERVED_MSK \
3623 (0x3<<BT_UART_MSG_2_FRAME2RESERVED_POS)
3624
3625#define BT_UART_MSG_2_FRAME3BRLASTTXPOWER_POS (0)
3626#define BT_UART_MSG_2_FRAME3BRLASTTXPOWER_MSK \
3627 (0xF<<BT_UART_MSG_2_FRAME3BRLASTTXPOWER_POS)
3628#define BT_UART_MSG_2_FRAME3INQPAGESRMODE_POS (4)
3629#define BT_UART_MSG_2_FRAME3INQPAGESRMODE_MSK \
3630 (0x1<<BT_UART_MSG_2_FRAME3INQPAGESRMODE_POS)
3631#define BT_UART_MSG_2_FRAME3LEMASTER_POS (5)
3632#define BT_UART_MSG_2_FRAME3LEMASTER_MSK \
3633 (0x1<<BT_UART_MSG_2_FRAME3LEMASTER_POS)
3634#define BT_UART_MSG_2_FRAME3RESERVED_POS (6)
3635#define BT_UART_MSG_2_FRAME3RESERVED_MSK \
3636 (0x3<<BT_UART_MSG_2_FRAME3RESERVED_POS)
3637
3638#define BT_UART_MSG_2_FRAME4LELASTTXPOWER_POS (0)
3639#define BT_UART_MSG_2_FRAME4LELASTTXPOWER_MSK \
3640 (0xF<<BT_UART_MSG_2_FRAME4LELASTTXPOWER_POS)
3641#define BT_UART_MSG_2_FRAME4NUMLECONN_POS (4)
3642#define BT_UART_MSG_2_FRAME4NUMLECONN_MSK \
3643 (0x3<<BT_UART_MSG_2_FRAME4NUMLECONN_POS)
3644#define BT_UART_MSG_2_FRAME4RESERVED_POS (6)
3645#define BT_UART_MSG_2_FRAME4RESERVED_MSK \
3646 (0x3<<BT_UART_MSG_2_FRAME4RESERVED_POS)
3647
3648#define BT_UART_MSG_2_FRAME5BTMINRSSI_POS (0)
3649#define BT_UART_MSG_2_FRAME5BTMINRSSI_MSK \
3650 (0xF<<BT_UART_MSG_2_FRAME5BTMINRSSI_POS)
3651#define BT_UART_MSG_2_FRAME5LESCANINITMODE_POS (4)
3652#define BT_UART_MSG_2_FRAME5LESCANINITMODE_MSK \
3653 (0x1<<BT_UART_MSG_2_FRAME5LESCANINITMODE_POS)
3654#define BT_UART_MSG_2_FRAME5LEADVERMODE_POS (5)
3655#define BT_UART_MSG_2_FRAME5LEADVERMODE_MSK \
3656 (0x1<<BT_UART_MSG_2_FRAME5LEADVERMODE_POS)
3657#define BT_UART_MSG_2_FRAME5RESERVED_POS (6)
3658#define BT_UART_MSG_2_FRAME5RESERVED_MSK \
3659 (0x3<<BT_UART_MSG_2_FRAME5RESERVED_POS)
3660
3661#define BT_UART_MSG_2_FRAME6LECONNINTERVAL_POS (0)
3662#define BT_UART_MSG_2_FRAME6LECONNINTERVAL_MSK \
3663 (0x1F<<BT_UART_MSG_2_FRAME6LECONNINTERVAL_POS)
3664#define BT_UART_MSG_2_FRAME6RFU_POS (5)
3665#define BT_UART_MSG_2_FRAME6RFU_MSK \
3666 (0x1<<BT_UART_MSG_2_FRAME6RFU_POS)
3667#define BT_UART_MSG_2_FRAME6RESERVED_POS (6)
3668#define BT_UART_MSG_2_FRAME6RESERVED_MSK \
3669 (0x3<<BT_UART_MSG_2_FRAME6RESERVED_POS)
3670
3671#define BT_UART_MSG_2_FRAME7LECONNSLAVELAT_POS (0)
3672#define BT_UART_MSG_2_FRAME7LECONNSLAVELAT_MSK \
3673 (0x7<<BT_UART_MSG_2_FRAME7LECONNSLAVELAT_POS)
3674#define BT_UART_MSG_2_FRAME7LEPROFILE1_POS (3)
3675#define BT_UART_MSG_2_FRAME7LEPROFILE1_MSK \
3676 (0x1<<BT_UART_MSG_2_FRAME7LEPROFILE1_POS)
3677#define BT_UART_MSG_2_FRAME7LEPROFILE2_POS (4)
3678#define BT_UART_MSG_2_FRAME7LEPROFILE2_MSK \
3679 (0x1<<BT_UART_MSG_2_FRAME7LEPROFILE2_POS)
3680#define BT_UART_MSG_2_FRAME7LEPROFILEOTHER_POS (5)
3681#define BT_UART_MSG_2_FRAME7LEPROFILEOTHER_MSK \
3682 (0x1<<BT_UART_MSG_2_FRAME7LEPROFILEOTHER_POS)
3683#define BT_UART_MSG_2_FRAME7RESERVED_POS (6)
3684#define BT_UART_MSG_2_FRAME7RESERVED_MSK \
3685 (0x3<<BT_UART_MSG_2_FRAME7RESERVED_POS)
3686
3687
3688#define BT_ENABLE_REDUCED_TXPOWER_THRESHOLD (-62)
3689#define BT_DISABLE_REDUCED_TXPOWER_THRESHOLD (-65)
3690
3691struct iwl_bt_uart_msg {
3692 u8 header;
3693 u8 frame1;
3694 u8 frame2;
3695 u8 frame3;
3696 u8 frame4;
3697 u8 frame5;
3698 u8 frame6;
3699 u8 frame7;
3700} __packed;
3701
3702struct iwl_bt_coex_profile_notif {
3703 struct iwl_bt_uart_msg last_bt_uart_msg;
3704 u8 bt_status;
3705 u8 bt_traffic_load;
3706 u8 bt_ci_compliance;
3707 u8 reserved;
3708} __packed;
3709
3710#define IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS 0
3711#define IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_MSK 0x1
3712#define IWL_BT_COEX_PRIO_TBL_PRIO_POS 1
3713#define IWL_BT_COEX_PRIO_TBL_PRIO_MASK 0x0e
3714#define IWL_BT_COEX_PRIO_TBL_RESERVED_POS 4
3715#define IWL_BT_COEX_PRIO_TBL_RESERVED_MASK 0xf0
3716#define IWL_BT_COEX_PRIO_TBL_PRIO_SHIFT 1
3717
3718
3719
3720
3721
3722enum bt_coex_prio_table_events {
3723 BT_COEX_PRIO_TBL_EVT_INIT_CALIB1 = 0,
3724 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2 = 1,
3725 BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_LOW1 = 2,
3726 BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_LOW2 = 3,
3727 BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_HIGH1 = 4,
3728 BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_HIGH2 = 5,
3729 BT_COEX_PRIO_TBL_EVT_DTIM = 6,
3730 BT_COEX_PRIO_TBL_EVT_SCAN52 = 7,
3731 BT_COEX_PRIO_TBL_EVT_SCAN24 = 8,
3732 BT_COEX_PRIO_TBL_EVT_RESERVED0 = 9,
3733 BT_COEX_PRIO_TBL_EVT_RESERVED1 = 10,
3734 BT_COEX_PRIO_TBL_EVT_RESERVED2 = 11,
3735 BT_COEX_PRIO_TBL_EVT_RESERVED3 = 12,
3736 BT_COEX_PRIO_TBL_EVT_RESERVED4 = 13,
3737 BT_COEX_PRIO_TBL_EVT_RESERVED5 = 14,
3738 BT_COEX_PRIO_TBL_EVT_RESERVED6 = 15,
3739
3740 BT_COEX_PRIO_TBL_EVT_MAX,
3741};
3742
3743enum bt_coex_prio_table_priorities {
3744 BT_COEX_PRIO_TBL_DISABLED = 0,
3745 BT_COEX_PRIO_TBL_PRIO_LOW = 1,
3746 BT_COEX_PRIO_TBL_PRIO_HIGH = 2,
3747 BT_COEX_PRIO_TBL_PRIO_BYPASS = 3,
3748 BT_COEX_PRIO_TBL_PRIO_COEX_OFF = 4,
3749 BT_COEX_PRIO_TBL_PRIO_COEX_ON = 5,
3750 BT_COEX_PRIO_TBL_PRIO_RSRVD1 = 6,
3751 BT_COEX_PRIO_TBL_PRIO_RSRVD2 = 7,
3752 BT_COEX_PRIO_TBL_MAX,
3753};
3754
3755struct iwl_bt_coex_prio_table_cmd {
3756 u8 prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX];
3757} __packed;
3758
3759#define IWL_BT_COEX_ENV_CLOSE 0
3760#define IWL_BT_COEX_ENV_OPEN 1
3761
3762
3763
3764
3765struct iwl_bt_coex_prot_env_cmd {
3766 u8 action;
3767 u8 type;
3768 u8 reserved[2];
3769} __packed;
3770
3771
3772
3773
3774enum iwlagn_d3_wakeup_filters {
3775 IWLAGN_D3_WAKEUP_RFKILL = BIT(0),
3776 IWLAGN_D3_WAKEUP_SYSASSERT = BIT(1),
3777};
3778
3779struct iwlagn_d3_config_cmd {
3780 __le32 min_sleep_time;
3781 __le32 wakeup_flags;
3782} __packed;
3783
3784
3785
3786
3787#define IWLAGN_WOWLAN_MIN_PATTERN_LEN 16
3788#define IWLAGN_WOWLAN_MAX_PATTERN_LEN 128
3789
3790struct iwlagn_wowlan_pattern {
3791 u8 mask[IWLAGN_WOWLAN_MAX_PATTERN_LEN / 8];
3792 u8 pattern[IWLAGN_WOWLAN_MAX_PATTERN_LEN];
3793 u8 mask_size;
3794 u8 pattern_size;
3795 __le16 reserved;
3796} __packed;
3797
3798#define IWLAGN_WOWLAN_MAX_PATTERNS 20
3799
3800struct iwlagn_wowlan_patterns_cmd {
3801 __le32 n_patterns;
3802 struct iwlagn_wowlan_pattern patterns[];
3803} __packed;
3804
3805
3806
3807
3808enum iwlagn_wowlan_wakeup_filters {
3809 IWLAGN_WOWLAN_WAKEUP_MAGIC_PACKET = BIT(0),
3810 IWLAGN_WOWLAN_WAKEUP_PATTERN_MATCH = BIT(1),
3811 IWLAGN_WOWLAN_WAKEUP_BEACON_MISS = BIT(2),
3812 IWLAGN_WOWLAN_WAKEUP_LINK_CHANGE = BIT(3),
3813 IWLAGN_WOWLAN_WAKEUP_GTK_REKEY_FAIL = BIT(4),
3814 IWLAGN_WOWLAN_WAKEUP_EAP_IDENT_REQ = BIT(5),
3815 IWLAGN_WOWLAN_WAKEUP_4WAY_HANDSHAKE = BIT(6),
3816 IWLAGN_WOWLAN_WAKEUP_ALWAYS = BIT(7),
3817 IWLAGN_WOWLAN_WAKEUP_ENABLE_NET_DETECT = BIT(8),
3818};
3819
3820struct iwlagn_wowlan_wakeup_filter_cmd {
3821 __le32 enabled;
3822 __le16 non_qos_seq;
3823 __le16 reserved;
3824 __le16 qos_seq[8];
3825};
3826
3827
3828
3829
3830#define IWLAGN_NUM_RSC 16
3831
3832struct tkip_sc {
3833 __le16 iv16;
3834 __le16 pad;
3835 __le32 iv32;
3836} __packed;
3837
3838struct iwlagn_tkip_rsc_tsc {
3839 struct tkip_sc unicast_rsc[IWLAGN_NUM_RSC];
3840 struct tkip_sc multicast_rsc[IWLAGN_NUM_RSC];
3841 struct tkip_sc tsc;
3842} __packed;
3843
3844struct aes_sc {
3845 __le64 pn;
3846} __packed;
3847
3848struct iwlagn_aes_rsc_tsc {
3849 struct aes_sc unicast_rsc[IWLAGN_NUM_RSC];
3850 struct aes_sc multicast_rsc[IWLAGN_NUM_RSC];
3851 struct aes_sc tsc;
3852} __packed;
3853
3854union iwlagn_all_tsc_rsc {
3855 struct iwlagn_tkip_rsc_tsc tkip;
3856 struct iwlagn_aes_rsc_tsc aes;
3857};
3858
3859struct iwlagn_wowlan_rsc_tsc_params_cmd {
3860 union iwlagn_all_tsc_rsc all_tsc_rsc;
3861} __packed;
3862
3863
3864
3865
3866#define IWLAGN_MIC_KEY_SIZE 8
3867#define IWLAGN_P1K_SIZE 5
3868struct iwlagn_mic_keys {
3869 u8 tx[IWLAGN_MIC_KEY_SIZE];
3870 u8 rx_unicast[IWLAGN_MIC_KEY_SIZE];
3871 u8 rx_mcast[IWLAGN_MIC_KEY_SIZE];
3872} __packed;
3873
3874struct iwlagn_p1k_cache {
3875 __le16 p1k[IWLAGN_P1K_SIZE];
3876} __packed;
3877
3878#define IWLAGN_NUM_RX_P1K_CACHE 2
3879
3880struct iwlagn_wowlan_tkip_params_cmd {
3881 struct iwlagn_mic_keys mic_keys;
3882 struct iwlagn_p1k_cache tx;
3883 struct iwlagn_p1k_cache rx_uni[IWLAGN_NUM_RX_P1K_CACHE];
3884 struct iwlagn_p1k_cache rx_multi[IWLAGN_NUM_RX_P1K_CACHE];
3885} __packed;
3886
3887
3888
3889
3890
3891#define IWLAGN_KCK_MAX_SIZE 32
3892#define IWLAGN_KEK_MAX_SIZE 32
3893
3894struct iwlagn_wowlan_kek_kck_material_cmd {
3895 u8 kck[IWLAGN_KCK_MAX_SIZE];
3896 u8 kek[IWLAGN_KEK_MAX_SIZE];
3897 __le16 kck_len;
3898 __le16 kek_len;
3899 __le64 replay_ctr;
3900} __packed;
3901
3902#define RF_KILL_INDICATOR_FOR_WOWLAN 0x87
3903
3904
3905
3906
3907struct iwlagn_wowlan_status {
3908 __le64 replay_ctr;
3909 __le32 rekey_status;
3910 __le32 wakeup_reason;
3911 u8 pattern_number;
3912 u8 reserved1;
3913 __le16 qos_seq_ctr[8];
3914 __le16 non_qos_seq_ctr;
3915 __le16 reserved2;
3916 union iwlagn_all_tsc_rsc tsc_rsc;
3917 __le16 reserved3;
3918} __packed;
3919
3920
3921
3922
3923
3924
3925
3926
3927#define IWL_MIN_SLOT_TIME 20
3928
3929
3930
3931
3932
3933
3934
3935
3936struct iwl_wipan_slot {
3937 __le16 width;
3938 u8 type;
3939 u8 reserved;
3940} __packed;
3941
3942#define IWL_WIPAN_PARAMS_FLG_LEAVE_CHANNEL_CTS BIT(1)
3943#define IWL_WIPAN_PARAMS_FLG_LEAVE_CHANNEL_QUIET BIT(2)
3944#define IWL_WIPAN_PARAMS_FLG_SLOTTED_MODE BIT(3)
3945#define IWL_WIPAN_PARAMS_FLG_FILTER_BEACON_NOTIF BIT(4)
3946#define IWL_WIPAN_PARAMS_FLG_FULL_SLOTTED_MODE BIT(5)
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963struct iwl_wipan_params_cmd {
3964 __le16 flags;
3965 u8 reserved;
3966 u8 num_slots;
3967 struct iwl_wipan_slot slots[10];
3968} __packed;
3969
3970
3971
3972
3973
3974
3975
3976
3977
3978struct iwl_wipan_p2p_channel_switch_cmd {
3979 __le16 channel;
3980 __le16 reserved;
3981};
3982
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994struct iwl_wipan_noa_descriptor {
3995 u8 count;
3996 __le32 duration;
3997 __le32 interval;
3998 __le32 starttime;
3999} __packed;
4000
4001struct iwl_wipan_noa_attribute {
4002 u8 id;
4003 __le16 length;
4004 u8 index;
4005 u8 ct_window;
4006 struct iwl_wipan_noa_descriptor descr0, descr1;
4007 u8 reserved;
4008} __packed;
4009
4010struct iwl_wipan_noa_notification {
4011 u32 noa_active;
4012 struct iwl_wipan_noa_attribute noa_attribute;
4013} __packed;
4014
4015#endif
4016