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22#ifndef __REG_H__
23#define __REG_H__
24
25#define WL18XX_REGISTERS_BASE 0x00800000
26#define WL18XX_CODE_BASE 0x00000000
27#define WL18XX_DATA_BASE 0x00400000
28#define WL18XX_DOUBLE_BUFFER_BASE 0x00600000
29#define WL18XX_MCU_KEY_SEARCH_BASE 0x00700000
30#define WL18XX_PHY_BASE 0x00900000
31#define WL18XX_TOP_OCP_BASE 0x00A00000
32#define WL18XX_PACKET_RAM_BASE 0x00B00000
33#define WL18XX_HOST_BASE 0x00C00000
34
35#define WL18XX_REGISTERS_DOWN_SIZE 0x0000B000
36
37#define WL18XX_REG_BOOT_PART_START 0x00802000
38#define WL18XX_REG_BOOT_PART_SIZE 0x00014578
39
40#define WL18XX_PHY_INIT_MEM_ADDR 0x80926000
41
42#define WL18XX_SDIO_WSPI_BASE (WL18XX_REGISTERS_BASE)
43#define WL18XX_REG_CONFIG_BASE (WL18XX_REGISTERS_BASE + 0x02000)
44#define WL18XX_WGCM_REGS_BASE (WL18XX_REGISTERS_BASE + 0x03000)
45#define WL18XX_ENC_BASE (WL18XX_REGISTERS_BASE + 0x04000)
46#define WL18XX_INTERRUPT_BASE (WL18XX_REGISTERS_BASE + 0x05000)
47#define WL18XX_UART_BASE (WL18XX_REGISTERS_BASE + 0x06000)
48#define WL18XX_WELP_BASE (WL18XX_REGISTERS_BASE + 0x07000)
49#define WL18XX_TCP_CKSM_BASE (WL18XX_REGISTERS_BASE + 0x08000)
50#define WL18XX_FIFO_BASE (WL18XX_REGISTERS_BASE + 0x09000)
51#define WL18XX_OCP_BRIDGE_BASE (WL18XX_REGISTERS_BASE + 0x0A000)
52#define WL18XX_PMAC_RX_BASE (WL18XX_REGISTERS_BASE + 0x14800)
53#define WL18XX_PMAC_ACM_BASE (WL18XX_REGISTERS_BASE + 0x14C00)
54#define WL18XX_PMAC_TX_BASE (WL18XX_REGISTERS_BASE + 0x15000)
55#define WL18XX_PMAC_CSR_BASE (WL18XX_REGISTERS_BASE + 0x15400)
56
57#define WL18XX_REG_ECPU_CONTROL (WL18XX_REGISTERS_BASE + 0x02004)
58#define WL18XX_REG_INTERRUPT_NO_CLEAR (WL18XX_REGISTERS_BASE + 0x050E8)
59#define WL18XX_REG_INTERRUPT_ACK (WL18XX_REGISTERS_BASE + 0x050F0)
60#define WL18XX_REG_INTERRUPT_TRIG (WL18XX_REGISTERS_BASE + 0x5074)
61#define WL18XX_REG_INTERRUPT_TRIG_H (WL18XX_REGISTERS_BASE + 0x5078)
62#define WL18XX_REG_INTERRUPT_MASK (WL18XX_REGISTERS_BASE + 0x0050DC)
63
64#define WL18XX_REG_CHIP_ID_B (WL18XX_REGISTERS_BASE + 0x01542C)
65
66#define WL18XX_SLV_MEM_DATA (WL18XX_HOST_BASE + 0x0018)
67#define WL18XX_SLV_REG_DATA (WL18XX_HOST_BASE + 0x0008)
68
69
70#define WL18XX_SCR_PAD0 (WL18XX_REGISTERS_BASE + 0x0154EC)
71#define WL18XX_SCR_PAD1 (WL18XX_REGISTERS_BASE + 0x0154F0)
72#define WL18XX_SCR_PAD2 (WL18XX_REGISTERS_BASE + 0x0154F4)
73#define WL18XX_SCR_PAD3 (WL18XX_REGISTERS_BASE + 0x0154F8)
74#define WL18XX_SCR_PAD4 (WL18XX_REGISTERS_BASE + 0x0154FC)
75#define WL18XX_SCR_PAD4_SET (WL18XX_REGISTERS_BASE + 0x015504)
76#define WL18XX_SCR_PAD4_CLR (WL18XX_REGISTERS_BASE + 0x015500)
77#define WL18XX_SCR_PAD5 (WL18XX_REGISTERS_BASE + 0x015508)
78#define WL18XX_SCR_PAD5_SET (WL18XX_REGISTERS_BASE + 0x015510)
79#define WL18XX_SCR_PAD5_CLR (WL18XX_REGISTERS_BASE + 0x01550C)
80#define WL18XX_SCR_PAD6 (WL18XX_REGISTERS_BASE + 0x015514)
81#define WL18XX_SCR_PAD7 (WL18XX_REGISTERS_BASE + 0x015518)
82#define WL18XX_SCR_PAD8 (WL18XX_REGISTERS_BASE + 0x01551C)
83#define WL18XX_SCR_PAD9 (WL18XX_REGISTERS_BASE + 0x015520)
84
85
86#define WL18XX_SPARE_A1 (WL18XX_REGISTERS_BASE + 0x002194)
87#define WL18XX_SPARE_A2 (WL18XX_REGISTERS_BASE + 0x002198)
88#define WL18XX_SPARE_A3 (WL18XX_REGISTERS_BASE + 0x00219C)
89#define WL18XX_SPARE_A4 (WL18XX_REGISTERS_BASE + 0x0021A0)
90#define WL18XX_SPARE_A5 (WL18XX_REGISTERS_BASE + 0x0021A4)
91#define WL18XX_SPARE_A6 (WL18XX_REGISTERS_BASE + 0x0021A8)
92#define WL18XX_SPARE_A7 (WL18XX_REGISTERS_BASE + 0x0021AC)
93#define WL18XX_SPARE_A8 (WL18XX_REGISTERS_BASE + 0x0021B0)
94#define WL18XX_SPARE_B1 (WL18XX_REGISTERS_BASE + 0x015524)
95#define WL18XX_SPARE_B2 (WL18XX_REGISTERS_BASE + 0x015528)
96#define WL18XX_SPARE_B3 (WL18XX_REGISTERS_BASE + 0x01552C)
97#define WL18XX_SPARE_B4 (WL18XX_REGISTERS_BASE + 0x015530)
98#define WL18XX_SPARE_B5 (WL18XX_REGISTERS_BASE + 0x015534)
99#define WL18XX_SPARE_B6 (WL18XX_REGISTERS_BASE + 0x015538)
100#define WL18XX_SPARE_B7 (WL18XX_REGISTERS_BASE + 0x01553C)
101#define WL18XX_SPARE_B8 (WL18XX_REGISTERS_BASE + 0x015540)
102
103#define WL18XX_REG_COMMAND_MAILBOX_PTR (WL18XX_SCR_PAD0)
104#define WL18XX_REG_EVENT_MAILBOX_PTR (WL18XX_SCR_PAD1)
105#define WL18XX_EEPROMLESS_IND (WL18XX_SCR_PAD4)
106
107#define WL18XX_WELP_ARM_COMMAND (WL18XX_REGISTERS_BASE + 0x7100)
108#define WL18XX_ENABLE (WL18XX_REGISTERS_BASE + 0x01543C)
109
110
111#define PLATFORM_DETECTION 0xA0E3E0
112#define OCS_EN 0xA02080
113#define PRIMARY_CLK_DETECT 0xA020A6
114#define PLLSH_WCS_PLL_N 0xA02362
115#define PLLSH_WCS_PLL_M 0xA02360
116#define PLLSH_WCS_PLL_Q_FACTOR_CFG_1 0xA02364
117#define PLLSH_WCS_PLL_Q_FACTOR_CFG_2 0xA02366
118#define PLLSH_WCS_PLL_P_FACTOR_CFG_1 0xA02368
119#define PLLSH_WCS_PLL_P_FACTOR_CFG_2 0xA0236A
120#define PLLSH_WCS_PLL_SWALLOW_EN 0xA0236C
121#define PLLSH_WL_PLL_EN 0xA02392
122
123#define PLLSH_WCS_PLL_Q_FACTOR_CFG_1_MASK 0xFFFF
124#define PLLSH_WCS_PLL_Q_FACTOR_CFG_2_MASK 0x007F
125#define PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK 0xFFFF
126#define PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK 0x000F
127
128#define PLLSH_WCS_PLL_SWALLOW_EN_VAL1 0x1
129#define PLLSH_WCS_PLL_SWALLOW_EN_VAL2 0x12
130
131#define WL18XX_REG_FUSE_DATA_1_3 0xA0260C
132#define WL18XX_PG_VER_MASK 0x70
133#define WL18XX_PG_VER_OFFSET 4
134#define WL18XX_ROM_VER_MASK 0x3
135#define WL18XX_ROM_VER_OFFSET 0
136#define WL18XX_METAL_VER_MASK 0xC
137#define WL18XX_METAL_VER_OFFSET 2
138#define WL18XX_NEW_METAL_VER_MASK 0x180
139#define WL18XX_NEW_METAL_VER_OFFSET 7
140
141#define WL18XX_REG_FUSE_DATA_2_3 0xA02614
142#define WL18XX_RDL_VER_MASK 0x1f00
143#define WL18XX_RDL_VER_OFFSET 8
144
145#define WL18XX_REG_FUSE_BD_ADDR_1 0xA02602
146#define WL18XX_REG_FUSE_BD_ADDR_2 0xA02606
147
148#define WL18XX_CMD_MBOX_ADDRESS 0xB007B4
149
150#define WL18XX_FW_STATUS_ADDR 0x50F8
151
152#define CHIP_ID_185x_PG10 (0x06030101)
153#define CHIP_ID_185x_PG20 (0x06030111)
154
155
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159
160
161#define WL18XX_INTR_TRIG_CMD BIT(28)
162
163
164
165
166
167
168
169#define WL18XX_INTR_TRIG_EVENT_ACK BIT(29)
170
171
172
173
174
175#define WL18XX_SCR_PAD8_PLT 0xBABABEBE
176
177enum {
178 COMPONENT_NO_SWITCH = 0x0,
179 COMPONENT_2_WAY_SWITCH = 0x1,
180 COMPONENT_3_WAY_SWITCH = 0x2,
181 COMPONENT_MATCHING = 0x3,
182};
183
184enum {
185 FEM_NONE = 0x0,
186 FEM_VENDOR_1 = 0x1,
187 FEM_VENDOR_2 = 0x2,
188 FEM_VENDOR_3 = 0x3,
189};
190
191enum {
192 BOARD_TYPE_EVB_18XX = 0,
193 BOARD_TYPE_DVP_18XX = 1,
194 BOARD_TYPE_HDK_18XX = 2,
195 BOARD_TYPE_FPGA_18XX = 3,
196 BOARD_TYPE_COM8_18XX = 4,
197
198 NUM_BOARD_TYPES,
199};
200
201enum {
202 RDL_NONE = 0,
203 RDL_1_HP = 1,
204 RDL_2_SP = 2,
205 RDL_3_HP = 3,
206 RDL_4_SP = 4,
207
208 _RDL_LAST,
209 RDL_MAX = _RDL_LAST - 1,
210};
211
212static const char * const rdl_names[] = {
213 [RDL_NONE] = "",
214 [RDL_1_HP] = "1853 SISO",
215 [RDL_2_SP] = "1857 MIMO",
216 [RDL_3_HP] = "1893 SISO",
217 [RDL_4_SP] = "1897 MIMO",
218};
219
220#endif
221
