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30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/signal.h>
34#include <linux/jiffies.h>
35#include <linux/timer.h>
36#include <linux/pci.h>
37#include <linux/interrupt.h>
38#include <linux/time.h>
39#include <linux/slab.h>
40
41#include "../pci.h"
42#include "pciehp.h"
43
44static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
45{
46 struct pci_dev *dev = ctrl->pcie->port;
47 return pcie_capability_read_word(dev, reg, value);
48}
49
50static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
51{
52 struct pci_dev *dev = ctrl->pcie->port;
53 return pcie_capability_read_dword(dev, reg, value);
54}
55
56static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
57{
58 struct pci_dev *dev = ctrl->pcie->port;
59 return pcie_capability_write_word(dev, reg, value);
60}
61
62static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
63{
64 struct pci_dev *dev = ctrl->pcie->port;
65 return pcie_capability_write_dword(dev, reg, value);
66}
67
68
69#define POWER_ON 0
70#define POWER_OFF PCI_EXP_SLTCTL_PCC
71
72static irqreturn_t pcie_isr(int irq, void *dev_id);
73static void start_int_poll_timer(struct controller *ctrl, int sec);
74
75
76static void int_poll_timeout(unsigned long data)
77{
78 struct controller *ctrl = (struct controller *)data;
79
80
81 pcie_isr(0, ctrl);
82
83 init_timer(&ctrl->poll_timer);
84 if (!pciehp_poll_time)
85 pciehp_poll_time = 2;
86
87 start_int_poll_timer(ctrl, pciehp_poll_time);
88}
89
90
91static void start_int_poll_timer(struct controller *ctrl, int sec)
92{
93
94 if ((sec <= 0) || (sec > 60))
95 sec = 2;
96
97 ctrl->poll_timer.function = &int_poll_timeout;
98 ctrl->poll_timer.data = (unsigned long)ctrl;
99 ctrl->poll_timer.expires = jiffies + sec * HZ;
100 add_timer(&ctrl->poll_timer);
101}
102
103static inline int pciehp_request_irq(struct controller *ctrl)
104{
105 int retval, irq = ctrl->pcie->irq;
106
107
108 if (pciehp_poll_mode) {
109 init_timer(&ctrl->poll_timer);
110 start_int_poll_timer(ctrl, 10);
111 return 0;
112 }
113
114
115 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
116 if (retval)
117 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
118 irq);
119 return retval;
120}
121
122static inline void pciehp_free_irq(struct controller *ctrl)
123{
124 if (pciehp_poll_mode)
125 del_timer_sync(&ctrl->poll_timer);
126 else
127 free_irq(ctrl->pcie->irq, ctrl);
128}
129
130static int pcie_poll_cmd(struct controller *ctrl)
131{
132 u16 slot_status;
133 int err, timeout = 1000;
134
135 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
136 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
137 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
138 return 1;
139 }
140 while (timeout > 0) {
141 msleep(10);
142 timeout -= 10;
143 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
144 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
145 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
146 return 1;
147 }
148 }
149 return 0;
150}
151
152static void pcie_wait_cmd(struct controller *ctrl, int poll)
153{
154 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
155 unsigned long timeout = msecs_to_jiffies(msecs);
156 int rc;
157
158 if (poll)
159 rc = pcie_poll_cmd(ctrl);
160 else
161 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
162 if (!rc)
163 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
164}
165
166
167
168
169
170
171
172static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
173{
174 int retval = 0;
175 u16 slot_status;
176 u16 slot_ctrl;
177
178 mutex_lock(&ctrl->ctrl_lock);
179
180 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
181 if (retval) {
182 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
183 __func__);
184 goto out;
185 }
186
187 if (slot_status & PCI_EXP_SLTSTA_CC) {
188 if (!ctrl->no_cmd_complete) {
189
190
191
192
193
194 ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
195 } else if (!NO_CMD_CMPL(ctrl)) {
196
197
198
199
200
201 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to "
202 "wait for command completed event.\n");
203 ctrl->no_cmd_complete = 0;
204 } else {
205 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe "
206 "the controller is broken.\n");
207 }
208 }
209
210 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
211 if (retval) {
212 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
213 goto out;
214 }
215
216 slot_ctrl &= ~mask;
217 slot_ctrl |= (cmd & mask);
218 ctrl->cmd_busy = 1;
219 smp_mb();
220 retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl);
221 if (retval)
222 ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n");
223
224
225
226
227 if (!retval && !ctrl->no_cmd_complete) {
228 int poll = 0;
229
230
231
232
233
234 if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) ||
235 !(slot_ctrl & PCI_EXP_SLTCTL_CCIE))
236 poll = 1;
237 pcie_wait_cmd(ctrl, poll);
238 }
239 out:
240 mutex_unlock(&ctrl->ctrl_lock);
241 return retval;
242}
243
244static bool check_link_active(struct controller *ctrl)
245{
246 bool ret = false;
247 u16 lnk_status;
248
249 if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status))
250 return ret;
251
252 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
253
254 if (ret)
255 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
256
257 return ret;
258}
259
260static void __pcie_wait_link_active(struct controller *ctrl, bool active)
261{
262 int timeout = 1000;
263
264 if (check_link_active(ctrl) == active)
265 return;
266 while (timeout > 0) {
267 msleep(10);
268 timeout -= 10;
269 if (check_link_active(ctrl) == active)
270 return;
271 }
272 ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n",
273 active ? "set" : "cleared");
274}
275
276static void pcie_wait_link_active(struct controller *ctrl)
277{
278 __pcie_wait_link_active(ctrl, true);
279}
280
281static void pcie_wait_link_not_active(struct controller *ctrl)
282{
283 __pcie_wait_link_active(ctrl, false);
284}
285
286static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
287{
288 u32 l;
289 int count = 0;
290 int delay = 1000, step = 20;
291 bool found = false;
292
293 do {
294 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
295 count++;
296
297 if (found)
298 break;
299
300 msleep(step);
301 delay -= step;
302 } while (delay > 0);
303
304 if (count > 1 && pciehp_debug)
305 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
306 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
307 PCI_FUNC(devfn), count, step, l);
308
309 return found;
310}
311
312int pciehp_check_link_status(struct controller *ctrl)
313{
314 u16 lnk_status;
315 int retval = 0;
316 bool found = false;
317
318
319
320
321
322
323 if (ctrl->link_active_reporting)
324 pcie_wait_link_active(ctrl);
325 else
326 msleep(1000);
327
328
329 msleep(100);
330 found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
331 PCI_DEVFN(0, 0));
332
333 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
334 if (retval) {
335 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");
336 return retval;
337 }
338
339 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
340 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
341 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
342 ctrl_err(ctrl, "Link Training Error occurs \n");
343 retval = -1;
344 return retval;
345 }
346
347 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
348
349 if (!found && !retval)
350 retval = -1;
351
352 return retval;
353}
354
355static int __pciehp_link_set(struct controller *ctrl, bool enable)
356{
357 u16 lnk_ctrl;
358 int retval = 0;
359
360 retval = pciehp_readw(ctrl, PCI_EXP_LNKCTL, &lnk_ctrl);
361 if (retval) {
362 ctrl_err(ctrl, "Cannot read LNKCTRL register\n");
363 return retval;
364 }
365
366 if (enable)
367 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
368 else
369 lnk_ctrl |= PCI_EXP_LNKCTL_LD;
370
371 retval = pciehp_writew(ctrl, PCI_EXP_LNKCTL, lnk_ctrl);
372 if (retval) {
373 ctrl_err(ctrl, "Cannot write LNKCTRL register\n");
374 return retval;
375 }
376 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
377
378 return retval;
379}
380
381static int pciehp_link_enable(struct controller *ctrl)
382{
383 return __pciehp_link_set(ctrl, true);
384}
385
386static int pciehp_link_disable(struct controller *ctrl)
387{
388 return __pciehp_link_set(ctrl, false);
389}
390
391int pciehp_get_attention_status(struct slot *slot, u8 *status)
392{
393 struct controller *ctrl = slot->ctrl;
394 u16 slot_ctrl;
395 u8 atten_led_state;
396 int retval = 0;
397
398 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
399 if (retval) {
400 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
401 return retval;
402 }
403
404 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
405 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
406
407 atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6;
408
409 switch (atten_led_state) {
410 case 0:
411 *status = 0xFF;
412 break;
413 case 1:
414 *status = 1;
415 break;
416 case 2:
417 *status = 2;
418 break;
419 case 3:
420 *status = 0;
421 break;
422 default:
423 *status = 0xFF;
424 break;
425 }
426
427 return 0;
428}
429
430int pciehp_get_power_status(struct slot *slot, u8 *status)
431{
432 struct controller *ctrl = slot->ctrl;
433 u16 slot_ctrl;
434 u8 pwr_state;
435 int retval = 0;
436
437 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
438 if (retval) {
439 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
440 return retval;
441 }
442 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
443 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
444
445 pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10;
446
447 switch (pwr_state) {
448 case 0:
449 *status = 1;
450 break;
451 case 1:
452 *status = 0;
453 break;
454 default:
455 *status = 0xFF;
456 break;
457 }
458
459 return retval;
460}
461
462int pciehp_get_latch_status(struct slot *slot, u8 *status)
463{
464 struct controller *ctrl = slot->ctrl;
465 u16 slot_status;
466 int retval;
467
468 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
469 if (retval) {
470 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
471 __func__);
472 return retval;
473 }
474 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
475 return 0;
476}
477
478int pciehp_get_adapter_status(struct slot *slot, u8 *status)
479{
480 struct controller *ctrl = slot->ctrl;
481 u16 slot_status;
482 int retval;
483
484 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
485 if (retval) {
486 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
487 __func__);
488 return retval;
489 }
490 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
491 return 0;
492}
493
494int pciehp_query_power_fault(struct slot *slot)
495{
496 struct controller *ctrl = slot->ctrl;
497 u16 slot_status;
498 int retval;
499
500 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
501 if (retval) {
502 ctrl_err(ctrl, "Cannot check for power fault\n");
503 return retval;
504 }
505 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
506}
507
508int pciehp_set_attention_status(struct slot *slot, u8 value)
509{
510 struct controller *ctrl = slot->ctrl;
511 u16 slot_cmd;
512 u16 cmd_mask;
513
514 cmd_mask = PCI_EXP_SLTCTL_AIC;
515 switch (value) {
516 case 0 :
517 slot_cmd = 0x00C0;
518 break;
519 case 1:
520 slot_cmd = 0x0040;
521 break;
522 case 2:
523 slot_cmd = 0x0080;
524 break;
525 default:
526 return -EINVAL;
527 }
528 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
529 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
530 return pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
531}
532
533void pciehp_green_led_on(struct slot *slot)
534{
535 struct controller *ctrl = slot->ctrl;
536 u16 slot_cmd;
537 u16 cmd_mask;
538
539 slot_cmd = 0x0100;
540 cmd_mask = PCI_EXP_SLTCTL_PIC;
541 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
542 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
543 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
544}
545
546void pciehp_green_led_off(struct slot *slot)
547{
548 struct controller *ctrl = slot->ctrl;
549 u16 slot_cmd;
550 u16 cmd_mask;
551
552 slot_cmd = 0x0300;
553 cmd_mask = PCI_EXP_SLTCTL_PIC;
554 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
555 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
556 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
557}
558
559void pciehp_green_led_blink(struct slot *slot)
560{
561 struct controller *ctrl = slot->ctrl;
562 u16 slot_cmd;
563 u16 cmd_mask;
564
565 slot_cmd = 0x0200;
566 cmd_mask = PCI_EXP_SLTCTL_PIC;
567 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
568 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
569 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
570}
571
572int pciehp_power_on_slot(struct slot * slot)
573{
574 struct controller *ctrl = slot->ctrl;
575 u16 slot_cmd;
576 u16 cmd_mask;
577 u16 slot_status;
578 int retval = 0;
579
580
581 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
582 if (retval) {
583 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
584 __func__);
585 return retval;
586 }
587 slot_status &= PCI_EXP_SLTSTA_PFD;
588 if (slot_status) {
589 retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status);
590 if (retval) {
591 ctrl_err(ctrl,
592 "%s: Cannot write to SLOTSTATUS register\n",
593 __func__);
594 return retval;
595 }
596 }
597 ctrl->power_fault_detected = 0;
598
599 slot_cmd = POWER_ON;
600 cmd_mask = PCI_EXP_SLTCTL_PCC;
601 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
602 if (retval) {
603 ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd);
604 return retval;
605 }
606 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
607 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
608
609 retval = pciehp_link_enable(ctrl);
610 if (retval)
611 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
612
613 return retval;
614}
615
616int pciehp_power_off_slot(struct slot * slot)
617{
618 struct controller *ctrl = slot->ctrl;
619 u16 slot_cmd;
620 u16 cmd_mask;
621 int retval;
622
623
624 pciehp_link_disable(ctrl);
625
626 if (ctrl->link_active_reporting)
627 pcie_wait_link_not_active(ctrl);
628 else
629 msleep(1000);
630
631 slot_cmd = POWER_OFF;
632 cmd_mask = PCI_EXP_SLTCTL_PCC;
633 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
634 if (retval) {
635 ctrl_err(ctrl, "Write command failed!\n");
636 return retval;
637 }
638 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
639 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
640 return 0;
641}
642
643static irqreturn_t pcie_isr(int irq, void *dev_id)
644{
645 struct controller *ctrl = (struct controller *)dev_id;
646 struct slot *slot = ctrl->slot;
647 u16 detected, intr_loc;
648
649
650
651
652
653
654 intr_loc = 0;
655 do {
656 if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) {
657 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n",
658 __func__);
659 return IRQ_NONE;
660 }
661
662 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
663 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
664 PCI_EXP_SLTSTA_CC);
665 detected &= ~intr_loc;
666 intr_loc |= detected;
667 if (!intr_loc)
668 return IRQ_NONE;
669 if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) {
670 ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n",
671 __func__);
672 return IRQ_NONE;
673 }
674 } while (detected);
675
676 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
677
678
679 if (intr_loc & PCI_EXP_SLTSTA_CC) {
680 ctrl->cmd_busy = 0;
681 smp_mb();
682 wake_up(&ctrl->queue);
683 }
684
685 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
686 return IRQ_HANDLED;
687
688
689 if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
690 pciehp_handle_switch_change(slot);
691
692
693 if (intr_loc & PCI_EXP_SLTSTA_ABP)
694 pciehp_handle_attention_button(slot);
695
696
697 if (intr_loc & PCI_EXP_SLTSTA_PDC)
698 pciehp_handle_presence_change(slot);
699
700
701 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
702 ctrl->power_fault_detected = 1;
703 pciehp_handle_power_fault(slot);
704 }
705 return IRQ_HANDLED;
706}
707
708int pcie_enable_notification(struct controller *ctrl)
709{
710 u16 cmd, mask;
711
712
713
714
715
716
717
718
719
720
721
722 cmd = PCI_EXP_SLTCTL_PDCE;
723 if (ATTN_BUTTN(ctrl))
724 cmd |= PCI_EXP_SLTCTL_ABPE;
725 if (MRL_SENS(ctrl))
726 cmd |= PCI_EXP_SLTCTL_MRLSCE;
727 if (!pciehp_poll_mode)
728 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
729
730 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
731 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
732 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE);
733
734 if (pcie_write_cmd(ctrl, cmd, mask)) {
735 ctrl_err(ctrl, "Cannot enable software notification\n");
736 return -1;
737 }
738 return 0;
739}
740
741static void pcie_disable_notification(struct controller *ctrl)
742{
743 u16 mask;
744 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
745 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
746 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
747 PCI_EXP_SLTCTL_DLLSCE);
748 if (pcie_write_cmd(ctrl, 0, mask))
749 ctrl_warn(ctrl, "Cannot disable software notification\n");
750}
751
752int pcie_init_notification(struct controller *ctrl)
753{
754 if (pciehp_request_irq(ctrl))
755 return -1;
756 if (pcie_enable_notification(ctrl)) {
757 pciehp_free_irq(ctrl);
758 return -1;
759 }
760 ctrl->notification_enabled = 1;
761 return 0;
762}
763
764static void pcie_shutdown_notification(struct controller *ctrl)
765{
766 if (ctrl->notification_enabled) {
767 pcie_disable_notification(ctrl);
768 pciehp_free_irq(ctrl);
769 ctrl->notification_enabled = 0;
770 }
771}
772
773static int pcie_init_slot(struct controller *ctrl)
774{
775 struct slot *slot;
776 char name[32];
777
778 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
779 if (!slot)
780 return -ENOMEM;
781
782 snprintf(name, sizeof(name), "pciehp-%u", PSN(ctrl));
783 slot->wq = alloc_workqueue(name, 0, 0);
784 if (!slot->wq)
785 goto abort;
786
787 slot->ctrl = ctrl;
788 mutex_init(&slot->lock);
789 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
790 ctrl->slot = slot;
791 return 0;
792abort:
793 kfree(slot);
794 return -ENOMEM;
795}
796
797static void pcie_cleanup_slot(struct controller *ctrl)
798{
799 struct slot *slot = ctrl->slot;
800 cancel_delayed_work(&slot->work);
801 destroy_workqueue(slot->wq);
802 kfree(slot);
803}
804
805static inline void dbg_ctrl(struct controller *ctrl)
806{
807 int i;
808 u16 reg16;
809 struct pci_dev *pdev = ctrl->pcie->port;
810
811 if (!pciehp_debug)
812 return;
813
814 ctrl_info(ctrl, "Hotplug Controller:\n");
815 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
816 pci_name(pdev), pdev->irq);
817 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor);
818 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device);
819 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n",
820 pdev->subsystem_device);
821 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n",
822 pdev->subsystem_vendor);
823 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n",
824 pci_pcie_cap(pdev));
825 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
826 if (!pci_resource_len(pdev, i))
827 continue;
828 ctrl_info(ctrl, " PCI resource [%d] : %pR\n",
829 i, &pdev->resource[i]);
830 }
831 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
832 ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl));
833 ctrl_info(ctrl, " Attention Button : %3s\n",
834 ATTN_BUTTN(ctrl) ? "yes" : "no");
835 ctrl_info(ctrl, " Power Controller : %3s\n",
836 POWER_CTRL(ctrl) ? "yes" : "no");
837 ctrl_info(ctrl, " MRL Sensor : %3s\n",
838 MRL_SENS(ctrl) ? "yes" : "no");
839 ctrl_info(ctrl, " Attention Indicator : %3s\n",
840 ATTN_LED(ctrl) ? "yes" : "no");
841 ctrl_info(ctrl, " Power Indicator : %3s\n",
842 PWR_LED(ctrl) ? "yes" : "no");
843 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n",
844 HP_SUPR_RM(ctrl) ? "yes" : "no");
845 ctrl_info(ctrl, " EMI Present : %3s\n",
846 EMI(ctrl) ? "yes" : "no");
847 ctrl_info(ctrl, " Command Completed : %3s\n",
848 NO_CMD_CMPL(ctrl) ? "no" : "yes");
849 pciehp_readw(ctrl, PCI_EXP_SLTSTA, ®16);
850 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
851 pciehp_readw(ctrl, PCI_EXP_SLTCTL, ®16);
852 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
853}
854
855struct controller *pcie_init(struct pcie_device *dev)
856{
857 struct controller *ctrl;
858 u32 slot_cap, link_cap;
859 struct pci_dev *pdev = dev->port;
860
861 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
862 if (!ctrl) {
863 dev_err(&dev->device, "%s: Out of memory\n", __func__);
864 goto abort;
865 }
866 ctrl->pcie = dev;
867 if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) {
868 ctrl_err(ctrl, "Cannot read SLOTCAP register\n");
869 goto abort_ctrl;
870 }
871
872 ctrl->slot_cap = slot_cap;
873 mutex_init(&ctrl->ctrl_lock);
874 init_waitqueue_head(&ctrl->queue);
875 dbg_ctrl(ctrl);
876
877
878
879
880
881
882 if (NO_CMD_CMPL(ctrl) ||
883 !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
884 ctrl->no_cmd_complete = 1;
885
886
887 if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) {
888 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
889 goto abort_ctrl;
890 }
891 if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
892 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
893 ctrl->link_active_reporting = 1;
894 }
895
896
897 if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f))
898 goto abort_ctrl;
899
900
901 pcie_disable_notification(ctrl);
902
903 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
904 pdev->vendor, pdev->device, pdev->subsystem_vendor,
905 pdev->subsystem_device);
906
907 if (pcie_init_slot(ctrl))
908 goto abort_ctrl;
909
910 return ctrl;
911
912abort_ctrl:
913 kfree(ctrl);
914abort:
915 return NULL;
916}
917
918void pciehp_release_ctrl(struct controller *ctrl)
919{
920 pcie_shutdown_notification(ctrl);
921 pcie_cleanup_slot(ctrl);
922 kfree(ctrl);
923}
924
