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12#define DRV_NAME "sh-pfc"
13
14#include <linux/bitops.h>
15#include <linux/err.h>
16#include <linux/errno.h>
17#include <linux/io.h>
18#include <linux/ioport.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pinctrl/machine.h>
22#include <linux/platform_device.h>
23#include <linux/slab.h>
24
25#include "core.h"
26
27static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev)
28{
29 struct resource *res;
30 int k;
31
32 if (pdev->num_resources == 0)
33 return -EINVAL;
34
35 pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources *
36 sizeof(*pfc->window), GFP_NOWAIT);
37 if (!pfc->window)
38 return -ENOMEM;
39
40 pfc->num_windows = pdev->num_resources;
41
42 for (k = 0, res = pdev->resource; k < pdev->num_resources; k++, res++) {
43 WARN_ON(resource_type(res) != IORESOURCE_MEM);
44 pfc->window[k].phys = res->start;
45 pfc->window[k].size = resource_size(res);
46 pfc->window[k].virt = devm_ioremap_nocache(pfc->dev, res->start,
47 resource_size(res));
48 if (!pfc->window[k].virt)
49 return -ENOMEM;
50 }
51
52 return 0;
53}
54
55static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
56 unsigned long address)
57{
58 struct sh_pfc_window *window;
59 unsigned int i;
60
61
62 for (i = 0; i < pfc->num_windows; i++) {
63 window = pfc->window + i;
64
65 if (address < window->phys)
66 continue;
67
68 if (address >= (window->phys + window->size))
69 continue;
70
71 return window->virt + (address - window->phys);
72 }
73
74 BUG();
75 return NULL;
76}
77
78int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
79{
80 unsigned int offset;
81 unsigned int i;
82
83 if (pfc->info->ranges == NULL)
84 return pin;
85
86 for (i = 0, offset = 0; i < pfc->info->nr_ranges; ++i) {
87 const struct pinmux_range *range = &pfc->info->ranges[i];
88
89 if (pin <= range->end)
90 return pin >= range->begin
91 ? offset + pin - range->begin : -1;
92
93 offset += range->end - range->begin + 1;
94 }
95
96 return -EINVAL;
97}
98
99static int sh_pfc_enum_in_range(pinmux_enum_t enum_id,
100 const struct pinmux_range *r)
101{
102 if (enum_id < r->begin)
103 return 0;
104
105 if (enum_id > r->end)
106 return 0;
107
108 return 1;
109}
110
111unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
112 unsigned long reg_width)
113{
114 switch (reg_width) {
115 case 8:
116 return ioread8(mapped_reg);
117 case 16:
118 return ioread16(mapped_reg);
119 case 32:
120 return ioread32(mapped_reg);
121 }
122
123 BUG();
124 return 0;
125}
126
127void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
128 unsigned long data)
129{
130 switch (reg_width) {
131 case 8:
132 iowrite8(data, mapped_reg);
133 return;
134 case 16:
135 iowrite16(data, mapped_reg);
136 return;
137 case 32:
138 iowrite32(data, mapped_reg);
139 return;
140 }
141
142 BUG();
143}
144
145static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
146 const struct pinmux_cfg_reg *crp,
147 unsigned long in_pos,
148 void __iomem **mapped_regp,
149 unsigned long *maskp,
150 unsigned long *posp)
151{
152 int k;
153
154 *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
155
156 if (crp->field_width) {
157 *maskp = (1 << crp->field_width) - 1;
158 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
159 } else {
160 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
161 *posp = crp->reg_width;
162 for (k = 0; k <= in_pos; k++)
163 *posp -= crp->var_field_width[k];
164 }
165}
166
167static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
168 const struct pinmux_cfg_reg *crp,
169 unsigned long field, unsigned long value)
170{
171 void __iomem *mapped_reg;
172 unsigned long mask, pos, data;
173
174 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
175
176 dev_dbg(pfc->dev, "write_reg addr = %lx, value = %ld, field = %ld, "
177 "r_width = %ld, f_width = %ld\n",
178 crp->reg, value, field, crp->reg_width, crp->field_width);
179
180 mask = ~(mask << pos);
181 value = value << pos;
182
183 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
184 data &= mask;
185 data |= value;
186
187 if (pfc->info->unlock_reg)
188 sh_pfc_write_raw_reg(
189 sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
190 ~data);
191
192 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
193}
194
195static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
196 const struct pinmux_cfg_reg **crp, int *fieldp,
197 int *valuep)
198{
199 const struct pinmux_cfg_reg *config_reg;
200 unsigned long r_width, f_width, curr_width, ncomb;
201 int k, m, n, pos, bit_pos;
202
203 k = 0;
204 while (1) {
205 config_reg = pfc->info->cfg_regs + k;
206
207 r_width = config_reg->reg_width;
208 f_width = config_reg->field_width;
209
210 if (!r_width)
211 break;
212
213 pos = 0;
214 m = 0;
215 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
216 if (f_width)
217 curr_width = f_width;
218 else
219 curr_width = config_reg->var_field_width[m];
220
221 ncomb = 1 << curr_width;
222 for (n = 0; n < ncomb; n++) {
223 if (config_reg->enum_ids[pos + n] == enum_id) {
224 *crp = config_reg;
225 *fieldp = m;
226 *valuep = n;
227 return 0;
228 }
229 }
230 pos += ncomb;
231 m++;
232 }
233 k++;
234 }
235
236 return -EINVAL;
237}
238
239static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos,
240 pinmux_enum_t *enum_idp)
241{
242 const pinmux_enum_t *data = pfc->info->gpio_data;
243 int k;
244
245 if (pos) {
246 *enum_idp = data[pos + 1];
247 return pos + 1;
248 }
249
250 for (k = 0; k < pfc->info->gpio_data_size; k++) {
251 if (data[k] == mark) {
252 *enum_idp = data[k + 1];
253 return k + 1;
254 }
255 }
256
257 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
258 mark);
259 return -EINVAL;
260}
261
262int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
263{
264 const struct pinmux_cfg_reg *cr = NULL;
265 pinmux_enum_t enum_id;
266 const struct pinmux_range *range;
267 int in_range, pos, field, value;
268 int ret;
269
270 switch (pinmux_type) {
271 case PINMUX_TYPE_GPIO:
272 case PINMUX_TYPE_FUNCTION:
273 range = NULL;
274 break;
275
276 case PINMUX_TYPE_OUTPUT:
277 range = &pfc->info->output;
278 break;
279
280 case PINMUX_TYPE_INPUT:
281 range = &pfc->info->input;
282 break;
283
284 case PINMUX_TYPE_INPUT_PULLUP:
285 range = &pfc->info->input_pu;
286 break;
287
288 case PINMUX_TYPE_INPUT_PULLDOWN:
289 range = &pfc->info->input_pd;
290 break;
291
292 default:
293 return -EINVAL;
294 }
295
296 pos = 0;
297 enum_id = 0;
298 field = 0;
299 value = 0;
300
301
302 while (1) {
303 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
304 if (pos < 0)
305 return pos;
306
307 if (!enum_id)
308 break;
309
310
311
312
313
314 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
315 if (!in_range) {
316 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
317
318
319
320 in_range = 1;
321 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
322
323
324
325 in_range = sh_pfc_enum_in_range(enum_id, range);
326
327
328
329
330
331
332 if (in_range && enum_id == range->force)
333 continue;
334 }
335
336 }
337
338 if (!in_range)
339 continue;
340
341 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
342 if (ret < 0)
343 return ret;
344
345 sh_pfc_write_config_reg(pfc, cr, field, value);
346 }
347
348 return 0;
349}
350
351static int sh_pfc_probe(struct platform_device *pdev)
352{
353 const struct sh_pfc_soc_info *info;
354 struct sh_pfc *pfc;
355 int ret;
356
357 info = pdev->id_entry->driver_data
358 ? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data;
359 if (info == NULL)
360 return -ENODEV;
361
362 pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
363 if (pfc == NULL)
364 return -ENOMEM;
365
366 pfc->info = info;
367 pfc->dev = &pdev->dev;
368
369 ret = sh_pfc_ioremap(pfc, pdev);
370 if (unlikely(ret < 0))
371 return ret;
372
373 spin_lock_init(&pfc->lock);
374
375 pinctrl_provide_dummies();
376
377
378
379
380 ret = sh_pfc_register_pinctrl(pfc);
381 if (unlikely(ret != 0))
382 return ret;
383
384#ifdef CONFIG_GPIO_SH_PFC
385
386
387
388 ret = sh_pfc_register_gpiochip(pfc);
389 if (unlikely(ret != 0)) {
390
391
392
393
394
395 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
396 }
397#endif
398
399 platform_set_drvdata(pdev, pfc);
400
401 dev_info(pfc->dev, "%s support registered\n", info->name);
402
403 return 0;
404}
405
406static int sh_pfc_remove(struct platform_device *pdev)
407{
408 struct sh_pfc *pfc = platform_get_drvdata(pdev);
409
410#ifdef CONFIG_GPIO_SH_PFC
411 sh_pfc_unregister_gpiochip(pfc);
412#endif
413 sh_pfc_unregister_pinctrl(pfc);
414
415 platform_set_drvdata(pdev, NULL);
416
417 return 0;
418}
419
420static const struct platform_device_id sh_pfc_id_table[] = {
421#ifdef CONFIG_PINCTRL_PFC_R8A73A4
422 { "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info },
423#endif
424#ifdef CONFIG_PINCTRL_PFC_R8A7740
425 { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
426#endif
427#ifdef CONFIG_PINCTRL_PFC_R8A7779
428 { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
429#endif
430#ifdef CONFIG_PINCTRL_PFC_SH7203
431 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
432#endif
433#ifdef CONFIG_PINCTRL_PFC_SH7264
434 { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
435#endif
436#ifdef CONFIG_PINCTRL_PFC_SH7269
437 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
438#endif
439#ifdef CONFIG_PINCTRL_PFC_SH7372
440 { "pfc-sh7372", (kernel_ulong_t)&sh7372_pinmux_info },
441#endif
442#ifdef CONFIG_PINCTRL_PFC_SH73A0
443 { "pfc-sh73a0", (kernel_ulong_t)&sh73a0_pinmux_info },
444#endif
445#ifdef CONFIG_PINCTRL_PFC_SH7720
446 { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
447#endif
448#ifdef CONFIG_PINCTRL_PFC_SH7722
449 { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
450#endif
451#ifdef CONFIG_PINCTRL_PFC_SH7723
452 { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
453#endif
454#ifdef CONFIG_PINCTRL_PFC_SH7724
455 { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
456#endif
457#ifdef CONFIG_PINCTRL_PFC_SH7734
458 { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
459#endif
460#ifdef CONFIG_PINCTRL_PFC_SH7757
461 { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
462#endif
463#ifdef CONFIG_PINCTRL_PFC_SH7785
464 { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
465#endif
466#ifdef CONFIG_PINCTRL_PFC_SH7786
467 { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
468#endif
469#ifdef CONFIG_PINCTRL_PFC_SHX3
470 { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
471#endif
472 { "sh-pfc", 0 },
473 { },
474};
475MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);
476
477static struct platform_driver sh_pfc_driver = {
478 .probe = sh_pfc_probe,
479 .remove = sh_pfc_remove,
480 .id_table = sh_pfc_id_table,
481 .driver = {
482 .name = DRV_NAME,
483 .owner = THIS_MODULE,
484 },
485};
486
487static int __init sh_pfc_init(void)
488{
489 return platform_driver_register(&sh_pfc_driver);
490}
491postcore_initcall(sh_pfc_init);
492
493static void __exit sh_pfc_exit(void)
494{
495 platform_driver_unregister(&sh_pfc_driver);
496}
497module_exit(sh_pfc_exit);
498
499MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
500MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
501MODULE_LICENSE("GPL v2");
502
