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22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
25#include <linux/idr.h>
26#include <linux/interrupt.h>
27#include <linux/module.h>
28#include <linux/kthread.h>
29#include <linux/pci.h>
30#include <linux/spinlock.h>
31#include <linux/ctype.h>
32#include <linux/aer.h>
33#include <linux/slab.h>
34#include <linux/firmware.h>
35#include <linux/miscdevice.h>
36#include <linux/percpu.h>
37
38#include <scsi/scsi.h>
39#include <scsi/scsi_device.h>
40#include <scsi/scsi_host.h>
41#include <scsi/scsi_transport_fc.h>
42
43#include "lpfc_hw4.h"
44#include "lpfc_hw.h"
45#include "lpfc_sli.h"
46#include "lpfc_sli4.h"
47#include "lpfc_nl.h"
48#include "lpfc_disc.h"
49#include "lpfc_scsi.h"
50#include "lpfc.h"
51#include "lpfc_logmsg.h"
52#include "lpfc_crtn.h"
53#include "lpfc_vport.h"
54#include "lpfc_version.h"
55
56char *_dump_buf_data;
57unsigned long _dump_buf_data_order;
58char *_dump_buf_dif;
59unsigned long _dump_buf_dif_order;
60spinlock_t _dump_buf_lock;
61
62
63uint16_t lpfc_used_cpu[LPFC_MAX_CPU];
64
65static void lpfc_get_hba_model_desc(struct lpfc_hba *, uint8_t *, uint8_t *);
66static int lpfc_post_rcv_buf(struct lpfc_hba *);
67static int lpfc_sli4_queue_verify(struct lpfc_hba *);
68static int lpfc_create_bootstrap_mbox(struct lpfc_hba *);
69static int lpfc_setup_endian_order(struct lpfc_hba *);
70static void lpfc_destroy_bootstrap_mbox(struct lpfc_hba *);
71static void lpfc_free_els_sgl_list(struct lpfc_hba *);
72static void lpfc_init_sgl_list(struct lpfc_hba *);
73static int lpfc_init_active_sgl_array(struct lpfc_hba *);
74static void lpfc_free_active_sgl(struct lpfc_hba *);
75static int lpfc_hba_down_post_s3(struct lpfc_hba *phba);
76static int lpfc_hba_down_post_s4(struct lpfc_hba *phba);
77static int lpfc_sli4_cq_event_pool_create(struct lpfc_hba *);
78static void lpfc_sli4_cq_event_pool_destroy(struct lpfc_hba *);
79static void lpfc_sli4_cq_event_release_all(struct lpfc_hba *);
80static void lpfc_sli4_disable_intr(struct lpfc_hba *);
81static uint32_t lpfc_sli4_enable_intr(struct lpfc_hba *, uint32_t);
82
83static struct scsi_transport_template *lpfc_transport_template = NULL;
84static struct scsi_transport_template *lpfc_vport_transport_template = NULL;
85static DEFINE_IDR(lpfc_hba_index);
86
87
88
89
90
91
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93
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95
96
97
98
99
100
101int
102lpfc_config_port_prep(struct lpfc_hba *phba)
103{
104 lpfc_vpd_t *vp = &phba->vpd;
105 int i = 0, rc;
106 LPFC_MBOXQ_t *pmb;
107 MAILBOX_t *mb;
108 char *lpfc_vpd_data = NULL;
109 uint16_t offset = 0;
110 static char licensed[56] =
111 "key unlock for use with gnu public licensed code only\0";
112 static int init_key = 1;
113
114 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
115 if (!pmb) {
116 phba->link_state = LPFC_HBA_ERROR;
117 return -ENOMEM;
118 }
119
120 mb = &pmb->u.mb;
121 phba->link_state = LPFC_INIT_MBX_CMDS;
122
123 if (lpfc_is_LC_HBA(phba->pcidev->device)) {
124 if (init_key) {
125 uint32_t *ptext = (uint32_t *) licensed;
126
127 for (i = 0; i < 56; i += sizeof (uint32_t), ptext++)
128 *ptext = cpu_to_be32(*ptext);
129 init_key = 0;
130 }
131
132 lpfc_read_nv(phba, pmb);
133 memset((char*)mb->un.varRDnvp.rsvd3, 0,
134 sizeof (mb->un.varRDnvp.rsvd3));
135 memcpy((char*)mb->un.varRDnvp.rsvd3, licensed,
136 sizeof (licensed));
137
138 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
139
140 if (rc != MBX_SUCCESS) {
141 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX,
142 "0324 Config Port initialization "
143 "error, mbxCmd x%x READ_NVPARM, "
144 "mbxStatus x%x\n",
145 mb->mbxCommand, mb->mbxStatus);
146 mempool_free(pmb, phba->mbox_mem_pool);
147 return -ERESTART;
148 }
149 memcpy(phba->wwnn, (char *)mb->un.varRDnvp.nodename,
150 sizeof(phba->wwnn));
151 memcpy(phba->wwpn, (char *)mb->un.varRDnvp.portname,
152 sizeof(phba->wwpn));
153 }
154
155 phba->sli3_options = 0x0;
156
157
158 lpfc_read_rev(phba, pmb);
159 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
160 if (rc != MBX_SUCCESS) {
161 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
162 "0439 Adapter failed to init, mbxCmd x%x "
163 "READ_REV, mbxStatus x%x\n",
164 mb->mbxCommand, mb->mbxStatus);
165 mempool_free( pmb, phba->mbox_mem_pool);
166 return -ERESTART;
167 }
168
169
170
171
172
173
174 if (mb->un.varRdRev.rr == 0) {
175 vp->rev.rBit = 0;
176 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
177 "0440 Adapter failed to init, READ_REV has "
178 "missing revision information.\n");
179 mempool_free(pmb, phba->mbox_mem_pool);
180 return -ERESTART;
181 }
182
183 if (phba->sli_rev == 3 && !mb->un.varRdRev.v3rsp) {
184 mempool_free(pmb, phba->mbox_mem_pool);
185 return -EINVAL;
186 }
187
188
189 vp->rev.rBit = 1;
190 memcpy(&vp->sli3Feat, &mb->un.varRdRev.sli3Feat, sizeof(uint32_t));
191 vp->rev.sli1FwRev = mb->un.varRdRev.sli1FwRev;
192 memcpy(vp->rev.sli1FwName, (char*) mb->un.varRdRev.sli1FwName, 16);
193 vp->rev.sli2FwRev = mb->un.varRdRev.sli2FwRev;
194 memcpy(vp->rev.sli2FwName, (char *) mb->un.varRdRev.sli2FwName, 16);
195 vp->rev.biuRev = mb->un.varRdRev.biuRev;
196 vp->rev.smRev = mb->un.varRdRev.smRev;
197 vp->rev.smFwRev = mb->un.varRdRev.un.smFwRev;
198 vp->rev.endecRev = mb->un.varRdRev.endecRev;
199 vp->rev.fcphHigh = mb->un.varRdRev.fcphHigh;
200 vp->rev.fcphLow = mb->un.varRdRev.fcphLow;
201 vp->rev.feaLevelHigh = mb->un.varRdRev.feaLevelHigh;
202 vp->rev.feaLevelLow = mb->un.varRdRev.feaLevelLow;
203 vp->rev.postKernRev = mb->un.varRdRev.postKernRev;
204 vp->rev.opFwRev = mb->un.varRdRev.opFwRev;
205
206
207
208
209
210 if (vp->rev.feaLevelHigh < 9)
211 phba->sli3_options |= LPFC_SLI3_VPORT_TEARDOWN;
212
213 if (lpfc_is_LC_HBA(phba->pcidev->device))
214 memcpy(phba->RandomData, (char *)&mb->un.varWords[24],
215 sizeof (phba->RandomData));
216
217
218 lpfc_vpd_data = kmalloc(DMP_VPD_SIZE, GFP_KERNEL);
219 if (!lpfc_vpd_data)
220 goto out_free_mbox;
221 do {
222 lpfc_dump_mem(phba, pmb, offset, DMP_REGION_VPD);
223 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
224
225 if (rc != MBX_SUCCESS) {
226 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
227 "0441 VPD not present on adapter, "
228 "mbxCmd x%x DUMP VPD, mbxStatus x%x\n",
229 mb->mbxCommand, mb->mbxStatus);
230 mb->un.varDmp.word_cnt = 0;
231 }
232
233
234
235 if (mb->un.varDmp.word_cnt == 0)
236 break;
237 if (mb->un.varDmp.word_cnt > DMP_VPD_SIZE - offset)
238 mb->un.varDmp.word_cnt = DMP_VPD_SIZE - offset;
239 lpfc_sli_pcimem_bcopy(((uint8_t *)mb) + DMP_RSP_OFFSET,
240 lpfc_vpd_data + offset,
241 mb->un.varDmp.word_cnt);
242 offset += mb->un.varDmp.word_cnt;
243 } while (mb->un.varDmp.word_cnt && offset < DMP_VPD_SIZE);
244 lpfc_parse_vpd(phba, lpfc_vpd_data, offset);
245
246 kfree(lpfc_vpd_data);
247out_free_mbox:
248 mempool_free(pmb, phba->mbox_mem_pool);
249 return 0;
250}
251
252
253
254
255
256
257
258
259
260
261
262static void
263lpfc_config_async_cmpl(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq)
264{
265 if (pmboxq->u.mb.mbxStatus == MBX_SUCCESS)
266 phba->temp_sensor_support = 1;
267 else
268 phba->temp_sensor_support = 0;
269 mempool_free(pmboxq, phba->mbox_mem_pool);
270 return;
271}
272
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280
281
282
283static void
284lpfc_dump_wakeup_param_cmpl(struct lpfc_hba *phba, LPFC_MBOXQ_t *pmboxq)
285{
286 struct prog_id *prg;
287 uint32_t prog_id_word;
288 char dist = ' ';
289
290 char dist_char[] = "nabx";
291
292 if (pmboxq->u.mb.mbxStatus != MBX_SUCCESS) {
293 mempool_free(pmboxq, phba->mbox_mem_pool);
294 return;
295 }
296
297 prg = (struct prog_id *) &prog_id_word;
298
299
300 prog_id_word = pmboxq->u.mb.un.varWords[7];
301
302
303 if (prg->dist < 4)
304 dist = dist_char[prg->dist];
305
306 if ((prg->dist == 3) && (prg->num == 0))
307 sprintf(phba->OptionROMVersion, "%d.%d%d",
308 prg->ver, prg->rev, prg->lev);
309 else
310 sprintf(phba->OptionROMVersion, "%d.%d%d%c%d",
311 prg->ver, prg->rev, prg->lev,
312 dist, prg->num);
313 mempool_free(pmboxq, phba->mbox_mem_pool);
314 return;
315}
316
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324
325
326void
327lpfc_update_vport_wwn(struct lpfc_vport *vport)
328{
329
330 if (vport->phba->cfg_soft_wwnn)
331 u64_to_wwn(vport->phba->cfg_soft_wwnn,
332 vport->fc_sparam.nodeName.u.wwn);
333 if (vport->phba->cfg_soft_wwpn)
334 u64_to_wwn(vport->phba->cfg_soft_wwpn,
335 vport->fc_sparam.portName.u.wwn);
336
337
338
339
340
341 if (vport->fc_nodename.u.wwn[0] == 0 || vport->phba->cfg_soft_wwnn)
342 memcpy(&vport->fc_nodename, &vport->fc_sparam.nodeName,
343 sizeof(struct lpfc_name));
344 else
345 memcpy(&vport->fc_sparam.nodeName, &vport->fc_nodename,
346 sizeof(struct lpfc_name));
347
348 if (vport->fc_portname.u.wwn[0] == 0 || vport->phba->cfg_soft_wwpn)
349 memcpy(&vport->fc_portname, &vport->fc_sparam.portName,
350 sizeof(struct lpfc_name));
351 else
352 memcpy(&vport->fc_sparam.portName, &vport->fc_portname,
353 sizeof(struct lpfc_name));
354}
355
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367
368
369int
370lpfc_config_port_post(struct lpfc_hba *phba)
371{
372 struct lpfc_vport *vport = phba->pport;
373 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
374 LPFC_MBOXQ_t *pmb;
375 MAILBOX_t *mb;
376 struct lpfc_dmabuf *mp;
377 struct lpfc_sli *psli = &phba->sli;
378 uint32_t status, timeout;
379 int i, j;
380 int rc;
381
382 spin_lock_irq(&phba->hbalock);
383
384
385
386
387 if (phba->over_temp_state == HBA_OVER_TEMP)
388 phba->over_temp_state = HBA_NORMAL_TEMP;
389 spin_unlock_irq(&phba->hbalock);
390
391 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
392 if (!pmb) {
393 phba->link_state = LPFC_HBA_ERROR;
394 return -ENOMEM;
395 }
396 mb = &pmb->u.mb;
397
398
399 rc = lpfc_read_sparam(phba, pmb, 0);
400 if (rc) {
401 mempool_free(pmb, phba->mbox_mem_pool);
402 return -ENOMEM;
403 }
404
405 pmb->vport = vport;
406 if (lpfc_sli_issue_mbox(phba, pmb, MBX_POLL) != MBX_SUCCESS) {
407 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
408 "0448 Adapter failed init, mbxCmd x%x "
409 "READ_SPARM mbxStatus x%x\n",
410 mb->mbxCommand, mb->mbxStatus);
411 phba->link_state = LPFC_HBA_ERROR;
412 mp = (struct lpfc_dmabuf *) pmb->context1;
413 mempool_free(pmb, phba->mbox_mem_pool);
414 lpfc_mbuf_free(phba, mp->virt, mp->phys);
415 kfree(mp);
416 return -EIO;
417 }
418
419 mp = (struct lpfc_dmabuf *) pmb->context1;
420
421 memcpy(&vport->fc_sparam, mp->virt, sizeof (struct serv_parm));
422 lpfc_mbuf_free(phba, mp->virt, mp->phys);
423 kfree(mp);
424 pmb->context1 = NULL;
425 lpfc_update_vport_wwn(vport);
426
427
428 fc_host_node_name(shost) = wwn_to_u64(vport->fc_nodename.u.wwn);
429 fc_host_port_name(shost) = wwn_to_u64(vport->fc_portname.u.wwn);
430 fc_host_max_npiv_vports(shost) = phba->max_vpi;
431
432
433
434 if (phba->SerialNumber[0] == 0) {
435 uint8_t *outptr;
436
437 outptr = &vport->fc_nodename.u.s.IEEE[0];
438 for (i = 0; i < 12; i++) {
439 status = *outptr++;
440 j = ((status & 0xf0) >> 4);
441 if (j <= 9)
442 phba->SerialNumber[i] =
443 (char)((uint8_t) 0x30 + (uint8_t) j);
444 else
445 phba->SerialNumber[i] =
446 (char)((uint8_t) 0x61 + (uint8_t) (j - 10));
447 i++;
448 j = (status & 0xf);
449 if (j <= 9)
450 phba->SerialNumber[i] =
451 (char)((uint8_t) 0x30 + (uint8_t) j);
452 else
453 phba->SerialNumber[i] =
454 (char)((uint8_t) 0x61 + (uint8_t) (j - 10));
455 }
456 }
457
458 lpfc_read_config(phba, pmb);
459 pmb->vport = vport;
460 if (lpfc_sli_issue_mbox(phba, pmb, MBX_POLL) != MBX_SUCCESS) {
461 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
462 "0453 Adapter failed to init, mbxCmd x%x "
463 "READ_CONFIG, mbxStatus x%x\n",
464 mb->mbxCommand, mb->mbxStatus);
465 phba->link_state = LPFC_HBA_ERROR;
466 mempool_free( pmb, phba->mbox_mem_pool);
467 return -EIO;
468 }
469
470
471 lpfc_sli_read_link_ste(phba);
472
473
474 if (phba->cfg_hba_queue_depth > (mb->un.varRdConfig.max_xri+1))
475 phba->cfg_hba_queue_depth =
476 (mb->un.varRdConfig.max_xri + 1) -
477 lpfc_sli4_get_els_iocb_cnt(phba);
478
479 phba->lmt = mb->un.varRdConfig.lmt;
480
481
482 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
483
484 phba->link_state = LPFC_LINK_DOWN;
485
486
487 if (psli->ring[psli->extra_ring].sli.sli3.cmdringaddr)
488 psli->ring[psli->extra_ring].flag |= LPFC_STOP_IOCB_EVENT;
489 if (psli->ring[psli->fcp_ring].sli.sli3.cmdringaddr)
490 psli->ring[psli->fcp_ring].flag |= LPFC_STOP_IOCB_EVENT;
491 if (psli->ring[psli->next_ring].sli.sli3.cmdringaddr)
492 psli->ring[psli->next_ring].flag |= LPFC_STOP_IOCB_EVENT;
493
494
495 if (phba->sli_rev != 3)
496 lpfc_post_rcv_buf(phba);
497
498
499
500
501 if (phba->intr_type == MSIX) {
502 rc = lpfc_config_msi(phba, pmb);
503 if (rc) {
504 mempool_free(pmb, phba->mbox_mem_pool);
505 return -EIO;
506 }
507 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
508 if (rc != MBX_SUCCESS) {
509 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX,
510 "0352 Config MSI mailbox command "
511 "failed, mbxCmd x%x, mbxStatus x%x\n",
512 pmb->u.mb.mbxCommand,
513 pmb->u.mb.mbxStatus);
514 mempool_free(pmb, phba->mbox_mem_pool);
515 return -EIO;
516 }
517 }
518
519 spin_lock_irq(&phba->hbalock);
520
521 phba->hba_flag &= ~HBA_ERATT_HANDLED;
522
523
524 if (lpfc_readl(phba->HCregaddr, &status)) {
525 spin_unlock_irq(&phba->hbalock);
526 return -EIO;
527 }
528 status |= HC_MBINT_ENA | HC_ERINT_ENA | HC_LAINT_ENA;
529 if (psli->num_rings > 0)
530 status |= HC_R0INT_ENA;
531 if (psli->num_rings > 1)
532 status |= HC_R1INT_ENA;
533 if (psli->num_rings > 2)
534 status |= HC_R2INT_ENA;
535 if (psli->num_rings > 3)
536 status |= HC_R3INT_ENA;
537
538 if ((phba->cfg_poll & ENABLE_FCP_RING_POLLING) &&
539 (phba->cfg_poll & DISABLE_FCP_RING_INT))
540 status &= ~(HC_R0INT_ENA);
541
542 writel(status, phba->HCregaddr);
543 readl(phba->HCregaddr);
544 spin_unlock_irq(&phba->hbalock);
545
546
547 timeout = phba->fc_ratov * 2;
548 mod_timer(&vport->els_tmofunc,
549 jiffies + msecs_to_jiffies(1000 * timeout));
550
551 mod_timer(&phba->hb_tmofunc,
552 jiffies + msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
553 phba->hb_outstanding = 0;
554 phba->last_completion_time = jiffies;
555
556 mod_timer(&phba->eratt_poll,
557 jiffies + msecs_to_jiffies(1000 * LPFC_ERATT_POLL_INTERVAL));
558
559 if (phba->hba_flag & LINK_DISABLED) {
560 lpfc_printf_log(phba,
561 KERN_ERR, LOG_INIT,
562 "2598 Adapter Link is disabled.\n");
563 lpfc_down_link(phba, pmb);
564 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
565 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
566 if ((rc != MBX_SUCCESS) && (rc != MBX_BUSY)) {
567 lpfc_printf_log(phba,
568 KERN_ERR, LOG_INIT,
569 "2599 Adapter failed to issue DOWN_LINK"
570 " mbox command rc 0x%x\n", rc);
571
572 mempool_free(pmb, phba->mbox_mem_pool);
573 return -EIO;
574 }
575 } else if (phba->cfg_suppress_link_up == LPFC_INITIALIZE_LINK) {
576 mempool_free(pmb, phba->mbox_mem_pool);
577 rc = phba->lpfc_hba_init_link(phba, MBX_NOWAIT);
578 if (rc)
579 return rc;
580 }
581
582 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
583 if (!pmb) {
584 phba->link_state = LPFC_HBA_ERROR;
585 return -ENOMEM;
586 }
587
588 lpfc_config_async(phba, pmb, LPFC_ELS_RING);
589 pmb->mbox_cmpl = lpfc_config_async_cmpl;
590 pmb->vport = phba->pport;
591 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
592
593 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
594 lpfc_printf_log(phba,
595 KERN_ERR,
596 LOG_INIT,
597 "0456 Adapter failed to issue "
598 "ASYNCEVT_ENABLE mbox status x%x\n",
599 rc);
600 mempool_free(pmb, phba->mbox_mem_pool);
601 }
602
603
604 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
605 if (!pmb) {
606 phba->link_state = LPFC_HBA_ERROR;
607 return -ENOMEM;
608 }
609
610 lpfc_dump_wakeup_param(phba, pmb);
611 pmb->mbox_cmpl = lpfc_dump_wakeup_param_cmpl;
612 pmb->vport = phba->pport;
613 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
614
615 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
616 lpfc_printf_log(phba, KERN_ERR, LOG_INIT, "0435 Adapter failed "
617 "to get Option ROM version status x%x\n", rc);
618 mempool_free(pmb, phba->mbox_mem_pool);
619 }
620
621 return 0;
622}
623
624
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631
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633
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635
636
637
638int
639lpfc_hba_init_link(struct lpfc_hba *phba, uint32_t flag)
640{
641 return lpfc_hba_init_link_fc_topology(phba, phba->cfg_topology, flag);
642}
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659int
660lpfc_hba_init_link_fc_topology(struct lpfc_hba *phba, uint32_t fc_topology,
661 uint32_t flag)
662{
663 struct lpfc_vport *vport = phba->pport;
664 LPFC_MBOXQ_t *pmb;
665 MAILBOX_t *mb;
666 int rc;
667
668 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
669 if (!pmb) {
670 phba->link_state = LPFC_HBA_ERROR;
671 return -ENOMEM;
672 }
673 mb = &pmb->u.mb;
674 pmb->vport = vport;
675
676 if ((phba->cfg_link_speed > LPFC_USER_LINK_SPEED_MAX) ||
677 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_1G) &&
678 !(phba->lmt & LMT_1Gb)) ||
679 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_2G) &&
680 !(phba->lmt & LMT_2Gb)) ||
681 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_4G) &&
682 !(phba->lmt & LMT_4Gb)) ||
683 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_8G) &&
684 !(phba->lmt & LMT_8Gb)) ||
685 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_10G) &&
686 !(phba->lmt & LMT_10Gb)) ||
687 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_16G) &&
688 !(phba->lmt & LMT_16Gb))) {
689
690 lpfc_printf_log(phba, KERN_ERR, LOG_LINK_EVENT,
691 "1302 Invalid speed for this board:%d "
692 "Reset link speed to auto.\n",
693 phba->cfg_link_speed);
694 phba->cfg_link_speed = LPFC_USER_LINK_SPEED_AUTO;
695 }
696 lpfc_init_link(phba, pmb, fc_topology, phba->cfg_link_speed);
697 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
698 if (phba->sli_rev < LPFC_SLI_REV4)
699 lpfc_set_loopback_flag(phba);
700 rc = lpfc_sli_issue_mbox(phba, pmb, flag);
701 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
702 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
703 "0498 Adapter failed to init, mbxCmd x%x "
704 "INIT_LINK, mbxStatus x%x\n",
705 mb->mbxCommand, mb->mbxStatus);
706 if (phba->sli_rev <= LPFC_SLI_REV3) {
707
708 writel(0, phba->HCregaddr);
709 readl(phba->HCregaddr);
710
711 writel(0xffffffff, phba->HAregaddr);
712 readl(phba->HAregaddr);
713 }
714 phba->link_state = LPFC_HBA_ERROR;
715 if (rc != MBX_BUSY || flag == MBX_POLL)
716 mempool_free(pmb, phba->mbox_mem_pool);
717 return -EIO;
718 }
719 phba->cfg_suppress_link_up = LPFC_INITIALIZE_LINK;
720 if (flag == MBX_POLL)
721 mempool_free(pmb, phba->mbox_mem_pool);
722
723 return 0;
724}
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739int
740lpfc_hba_down_link(struct lpfc_hba *phba, uint32_t flag)
741{
742 LPFC_MBOXQ_t *pmb;
743 int rc;
744
745 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
746 if (!pmb) {
747 phba->link_state = LPFC_HBA_ERROR;
748 return -ENOMEM;
749 }
750
751 lpfc_printf_log(phba,
752 KERN_ERR, LOG_INIT,
753 "0491 Adapter Link is disabled.\n");
754 lpfc_down_link(phba, pmb);
755 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
756 rc = lpfc_sli_issue_mbox(phba, pmb, flag);
757 if ((rc != MBX_SUCCESS) && (rc != MBX_BUSY)) {
758 lpfc_printf_log(phba,
759 KERN_ERR, LOG_INIT,
760 "2522 Adapter failed to issue DOWN_LINK"
761 " mbox command rc 0x%x\n", rc);
762
763 mempool_free(pmb, phba->mbox_mem_pool);
764 return -EIO;
765 }
766 if (flag == MBX_POLL)
767 mempool_free(pmb, phba->mbox_mem_pool);
768
769 return 0;
770}
771
772
773
774
775
776
777
778
779
780
781
782
783int
784lpfc_hba_down_prep(struct lpfc_hba *phba)
785{
786 struct lpfc_vport **vports;
787 int i;
788
789 if (phba->sli_rev <= LPFC_SLI_REV3) {
790
791 writel(0, phba->HCregaddr);
792 readl(phba->HCregaddr);
793 }
794
795 if (phba->pport->load_flag & FC_UNLOADING)
796 lpfc_cleanup_discovery_resources(phba->pport);
797 else {
798 vports = lpfc_create_vport_work_array(phba);
799 if (vports != NULL)
800 for (i = 0; i <= phba->max_vports &&
801 vports[i] != NULL; i++)
802 lpfc_cleanup_discovery_resources(vports[i]);
803 lpfc_destroy_vport_work_array(phba, vports);
804 }
805 return 0;
806}
807
808
809
810
811
812
813
814
815
816
817
818
819static int
820lpfc_hba_down_post_s3(struct lpfc_hba *phba)
821{
822 struct lpfc_sli *psli = &phba->sli;
823 struct lpfc_sli_ring *pring;
824 struct lpfc_dmabuf *mp, *next_mp;
825 LIST_HEAD(completions);
826 int i;
827
828 if (phba->sli3_options & LPFC_SLI3_HBQ_ENABLED)
829 lpfc_sli_hbqbuf_free_all(phba);
830 else {
831
832 pring = &psli->ring[LPFC_ELS_RING];
833 list_for_each_entry_safe(mp, next_mp, &pring->postbufq, list) {
834 list_del(&mp->list);
835 pring->postbufq_cnt--;
836 lpfc_mbuf_free(phba, mp->virt, mp->phys);
837 kfree(mp);
838 }
839 }
840
841 spin_lock_irq(&phba->hbalock);
842 for (i = 0; i < psli->num_rings; i++) {
843 pring = &psli->ring[i];
844
845
846
847
848 list_splice_init(&pring->txcmplq, &completions);
849 spin_unlock_irq(&phba->hbalock);
850
851
852 lpfc_sli_cancel_iocbs(phba, &completions, IOSTAT_LOCAL_REJECT,
853 IOERR_SLI_ABORTED);
854
855 lpfc_sli_abort_iocb_ring(phba, pring);
856 spin_lock_irq(&phba->hbalock);
857 }
858 spin_unlock_irq(&phba->hbalock);
859
860 return 0;
861}
862
863
864
865
866
867
868
869
870
871
872
873
874static int
875lpfc_hba_down_post_s4(struct lpfc_hba *phba)
876{
877 struct lpfc_scsi_buf *psb, *psb_next;
878 LIST_HEAD(aborts);
879 int ret;
880 unsigned long iflag = 0;
881 struct lpfc_sglq *sglq_entry = NULL;
882
883 ret = lpfc_hba_down_post_s3(phba);
884 if (ret)
885 return ret;
886
887
888
889
890
891
892 spin_lock_irq(&phba->hbalock);
893
894
895
896
897 spin_lock(&phba->sli4_hba.abts_sgl_list_lock);
898 list_for_each_entry(sglq_entry,
899 &phba->sli4_hba.lpfc_abts_els_sgl_list, list)
900 sglq_entry->state = SGL_FREED;
901
902 list_splice_init(&phba->sli4_hba.lpfc_abts_els_sgl_list,
903 &phba->sli4_hba.lpfc_sgl_list);
904 spin_unlock(&phba->sli4_hba.abts_sgl_list_lock);
905
906
907
908 spin_lock(&phba->sli4_hba.abts_scsi_buf_list_lock);
909 list_splice_init(&phba->sli4_hba.lpfc_abts_scsi_buf_list,
910 &aborts);
911 spin_unlock(&phba->sli4_hba.abts_scsi_buf_list_lock);
912 spin_unlock_irq(&phba->hbalock);
913
914 list_for_each_entry_safe(psb, psb_next, &aborts, list) {
915 psb->pCmd = NULL;
916 psb->status = IOSTAT_SUCCESS;
917 }
918 spin_lock_irqsave(&phba->scsi_buf_list_put_lock, iflag);
919 list_splice(&aborts, &phba->lpfc_scsi_buf_list_put);
920 spin_unlock_irqrestore(&phba->scsi_buf_list_put_lock, iflag);
921 return 0;
922}
923
924
925
926
927
928
929
930
931
932
933
934
935int
936lpfc_hba_down_post(struct lpfc_hba *phba)
937{
938 return (*phba->lpfc_hba_down_post)(phba);
939}
940
941
942
943
944
945
946
947
948
949
950
951
952
953static void
954lpfc_hb_timeout(unsigned long ptr)
955{
956 struct lpfc_hba *phba;
957 uint32_t tmo_posted;
958 unsigned long iflag;
959
960 phba = (struct lpfc_hba *)ptr;
961
962
963 spin_lock_irqsave(&phba->pport->work_port_lock, iflag);
964 tmo_posted = phba->pport->work_port_events & WORKER_HB_TMO;
965 if (!tmo_posted)
966 phba->pport->work_port_events |= WORKER_HB_TMO;
967 spin_unlock_irqrestore(&phba->pport->work_port_lock, iflag);
968
969
970 if (!tmo_posted)
971 lpfc_worker_wake_up(phba);
972 return;
973}
974
975
976
977
978
979
980
981
982
983
984
985
986
987static void
988lpfc_rrq_timeout(unsigned long ptr)
989{
990 struct lpfc_hba *phba;
991 unsigned long iflag;
992
993 phba = (struct lpfc_hba *)ptr;
994 spin_lock_irqsave(&phba->pport->work_port_lock, iflag);
995 phba->hba_flag |= HBA_RRQ_ACTIVE;
996 spin_unlock_irqrestore(&phba->pport->work_port_lock, iflag);
997 lpfc_worker_wake_up(phba);
998}
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016static void
1017lpfc_hb_mbox_cmpl(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq)
1018{
1019 unsigned long drvr_flag;
1020
1021 spin_lock_irqsave(&phba->hbalock, drvr_flag);
1022 phba->hb_outstanding = 0;
1023 spin_unlock_irqrestore(&phba->hbalock, drvr_flag);
1024
1025
1026 mempool_free(pmboxq, phba->mbox_mem_pool);
1027 if (!(phba->pport->fc_flag & FC_OFFLINE_MODE) &&
1028 !(phba->link_state == LPFC_HBA_ERROR) &&
1029 !(phba->pport->load_flag & FC_UNLOADING))
1030 mod_timer(&phba->hb_tmofunc,
1031 jiffies +
1032 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
1033 return;
1034}
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052void
1053lpfc_hb_timeout_handler(struct lpfc_hba *phba)
1054{
1055 struct lpfc_vport **vports;
1056 LPFC_MBOXQ_t *pmboxq;
1057 struct lpfc_dmabuf *buf_ptr;
1058 int retval, i;
1059 struct lpfc_sli *psli = &phba->sli;
1060 LIST_HEAD(completions);
1061
1062 vports = lpfc_create_vport_work_array(phba);
1063 if (vports != NULL)
1064 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++)
1065 lpfc_rcv_seq_check_edtov(vports[i]);
1066 lpfc_destroy_vport_work_array(phba, vports);
1067
1068 if ((phba->link_state == LPFC_HBA_ERROR) ||
1069 (phba->pport->load_flag & FC_UNLOADING) ||
1070 (phba->pport->fc_flag & FC_OFFLINE_MODE))
1071 return;
1072
1073 spin_lock_irq(&phba->pport->work_port_lock);
1074
1075 if (time_after(phba->last_completion_time +
1076 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL),
1077 jiffies)) {
1078 spin_unlock_irq(&phba->pport->work_port_lock);
1079 if (!phba->hb_outstanding)
1080 mod_timer(&phba->hb_tmofunc,
1081 jiffies +
1082 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
1083 else
1084 mod_timer(&phba->hb_tmofunc,
1085 jiffies +
1086 msecs_to_jiffies(1000 * LPFC_HB_MBOX_TIMEOUT));
1087 return;
1088 }
1089 spin_unlock_irq(&phba->pport->work_port_lock);
1090
1091 if (phba->elsbuf_cnt &&
1092 (phba->elsbuf_cnt == phba->elsbuf_prev_cnt)) {
1093 spin_lock_irq(&phba->hbalock);
1094 list_splice_init(&phba->elsbuf, &completions);
1095 phba->elsbuf_cnt = 0;
1096 phba->elsbuf_prev_cnt = 0;
1097 spin_unlock_irq(&phba->hbalock);
1098
1099 while (!list_empty(&completions)) {
1100 list_remove_head(&completions, buf_ptr,
1101 struct lpfc_dmabuf, list);
1102 lpfc_mbuf_free(phba, buf_ptr->virt, buf_ptr->phys);
1103 kfree(buf_ptr);
1104 }
1105 }
1106 phba->elsbuf_prev_cnt = phba->elsbuf_cnt;
1107
1108
1109 if (phba->cfg_enable_hba_heartbeat) {
1110 if (!phba->hb_outstanding) {
1111 if ((!(psli->sli_flag & LPFC_SLI_MBOX_ACTIVE)) &&
1112 (list_empty(&psli->mboxq))) {
1113 pmboxq = mempool_alloc(phba->mbox_mem_pool,
1114 GFP_KERNEL);
1115 if (!pmboxq) {
1116 mod_timer(&phba->hb_tmofunc,
1117 jiffies +
1118 msecs_to_jiffies(1000 *
1119 LPFC_HB_MBOX_INTERVAL));
1120 return;
1121 }
1122
1123 lpfc_heart_beat(phba, pmboxq);
1124 pmboxq->mbox_cmpl = lpfc_hb_mbox_cmpl;
1125 pmboxq->vport = phba->pport;
1126 retval = lpfc_sli_issue_mbox(phba, pmboxq,
1127 MBX_NOWAIT);
1128
1129 if (retval != MBX_BUSY &&
1130 retval != MBX_SUCCESS) {
1131 mempool_free(pmboxq,
1132 phba->mbox_mem_pool);
1133 mod_timer(&phba->hb_tmofunc,
1134 jiffies +
1135 msecs_to_jiffies(1000 *
1136 LPFC_HB_MBOX_INTERVAL));
1137 return;
1138 }
1139 phba->skipped_hb = 0;
1140 phba->hb_outstanding = 1;
1141 } else if (time_before_eq(phba->last_completion_time,
1142 phba->skipped_hb)) {
1143 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
1144 "2857 Last completion time not "
1145 " updated in %d ms\n",
1146 jiffies_to_msecs(jiffies
1147 - phba->last_completion_time));
1148 } else
1149 phba->skipped_hb = jiffies;
1150
1151 mod_timer(&phba->hb_tmofunc,
1152 jiffies +
1153 msecs_to_jiffies(1000 * LPFC_HB_MBOX_TIMEOUT));
1154 return;
1155 } else {
1156
1157
1158
1159
1160
1161 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
1162 "0459 Adapter heartbeat still out"
1163 "standing:last compl time was %d ms.\n",
1164 jiffies_to_msecs(jiffies
1165 - phba->last_completion_time));
1166 mod_timer(&phba->hb_tmofunc,
1167 jiffies +
1168 msecs_to_jiffies(1000 * LPFC_HB_MBOX_TIMEOUT));
1169 }
1170 }
1171}
1172
1173
1174
1175
1176
1177
1178
1179
1180static void
1181lpfc_offline_eratt(struct lpfc_hba *phba)
1182{
1183 struct lpfc_sli *psli = &phba->sli;
1184
1185 spin_lock_irq(&phba->hbalock);
1186 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
1187 spin_unlock_irq(&phba->hbalock);
1188 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
1189
1190 lpfc_offline(phba);
1191 lpfc_reset_barrier(phba);
1192 spin_lock_irq(&phba->hbalock);
1193 lpfc_sli_brdreset(phba);
1194 spin_unlock_irq(&phba->hbalock);
1195 lpfc_hba_down_post(phba);
1196 lpfc_sli_brdready(phba, HS_MBRDY);
1197 lpfc_unblock_mgmt_io(phba);
1198 phba->link_state = LPFC_HBA_ERROR;
1199 return;
1200}
1201
1202
1203
1204
1205
1206
1207
1208
1209void
1210lpfc_sli4_offline_eratt(struct lpfc_hba *phba)
1211{
1212 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
1213 lpfc_offline(phba);
1214 lpfc_sli4_brdreset(phba);
1215 lpfc_hba_down_post(phba);
1216 lpfc_sli4_post_status_check(phba);
1217 lpfc_unblock_mgmt_io(phba);
1218 phba->link_state = LPFC_HBA_ERROR;
1219}
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230static void
1231lpfc_handle_deferred_eratt(struct lpfc_hba *phba)
1232{
1233 uint32_t old_host_status = phba->work_hs;
1234 struct lpfc_sli_ring *pring;
1235 struct lpfc_sli *psli = &phba->sli;
1236
1237
1238
1239
1240 if (pci_channel_offline(phba->pcidev)) {
1241 spin_lock_irq(&phba->hbalock);
1242 phba->hba_flag &= ~DEFER_ERATT;
1243 spin_unlock_irq(&phba->hbalock);
1244 return;
1245 }
1246
1247 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1248 "0479 Deferred Adapter Hardware Error "
1249 "Data: x%x x%x x%x\n",
1250 phba->work_hs,
1251 phba->work_status[0], phba->work_status[1]);
1252
1253 spin_lock_irq(&phba->hbalock);
1254 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
1255 spin_unlock_irq(&phba->hbalock);
1256
1257
1258
1259
1260
1261
1262
1263 pring = &psli->ring[psli->fcp_ring];
1264 lpfc_sli_abort_iocb_ring(phba, pring);
1265
1266
1267
1268
1269
1270 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
1271 lpfc_offline(phba);
1272
1273
1274 while (phba->work_hs & HS_FFER1) {
1275 msleep(100);
1276 if (lpfc_readl(phba->HSregaddr, &phba->work_hs)) {
1277 phba->work_hs = UNPLUG_ERR ;
1278 break;
1279 }
1280
1281 if (phba->pport->load_flag & FC_UNLOADING) {
1282 phba->work_hs = 0;
1283 break;
1284 }
1285 }
1286
1287
1288
1289
1290
1291
1292 if ((!phba->work_hs) && (!(phba->pport->load_flag & FC_UNLOADING)))
1293 phba->work_hs = old_host_status & ~HS_FFER1;
1294
1295 spin_lock_irq(&phba->hbalock);
1296 phba->hba_flag &= ~DEFER_ERATT;
1297 spin_unlock_irq(&phba->hbalock);
1298 phba->work_status[0] = readl(phba->MBslimaddr + 0xa8);
1299 phba->work_status[1] = readl(phba->MBslimaddr + 0xac);
1300}
1301
1302static void
1303lpfc_board_errevt_to_mgmt(struct lpfc_hba *phba)
1304{
1305 struct lpfc_board_event_header board_event;
1306 struct Scsi_Host *shost;
1307
1308 board_event.event_type = FC_REG_BOARD_EVENT;
1309 board_event.subcategory = LPFC_EVENT_PORTINTERR;
1310 shost = lpfc_shost_from_vport(phba->pport);
1311 fc_host_post_vendor_event(shost, fc_get_event_number(),
1312 sizeof(board_event),
1313 (char *) &board_event,
1314 LPFC_NL_VENDOR_ID);
1315}
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327static void
1328lpfc_handle_eratt_s3(struct lpfc_hba *phba)
1329{
1330 struct lpfc_vport *vport = phba->pport;
1331 struct lpfc_sli *psli = &phba->sli;
1332 struct lpfc_sli_ring *pring;
1333 uint32_t event_data;
1334 unsigned long temperature;
1335 struct temp_event temp_event_data;
1336 struct Scsi_Host *shost;
1337
1338
1339
1340
1341 if (pci_channel_offline(phba->pcidev)) {
1342 spin_lock_irq(&phba->hbalock);
1343 phba->hba_flag &= ~DEFER_ERATT;
1344 spin_unlock_irq(&phba->hbalock);
1345 return;
1346 }
1347
1348
1349 if (!phba->cfg_enable_hba_reset)
1350 return;
1351
1352
1353 lpfc_board_errevt_to_mgmt(phba);
1354
1355 if (phba->hba_flag & DEFER_ERATT)
1356 lpfc_handle_deferred_eratt(phba);
1357
1358 if ((phba->work_hs & HS_FFER6) || (phba->work_hs & HS_FFER8)) {
1359 if (phba->work_hs & HS_FFER6)
1360
1361 lpfc_printf_log(phba, KERN_INFO, LOG_LINK_EVENT,
1362 "1301 Re-establishing Link "
1363 "Data: x%x x%x x%x\n",
1364 phba->work_hs, phba->work_status[0],
1365 phba->work_status[1]);
1366 if (phba->work_hs & HS_FFER8)
1367
1368 lpfc_printf_log(phba, KERN_INFO, LOG_LINK_EVENT,
1369 "2861 Host Authentication device "
1370 "zeroization Data:x%x x%x x%x\n",
1371 phba->work_hs, phba->work_status[0],
1372 phba->work_status[1]);
1373
1374 spin_lock_irq(&phba->hbalock);
1375 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
1376 spin_unlock_irq(&phba->hbalock);
1377
1378
1379
1380
1381
1382
1383
1384 pring = &psli->ring[psli->fcp_ring];
1385 lpfc_sli_abort_iocb_ring(phba, pring);
1386
1387
1388
1389
1390
1391 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
1392 lpfc_offline(phba);
1393 lpfc_sli_brdrestart(phba);
1394 if (lpfc_online(phba) == 0) {
1395 lpfc_unblock_mgmt_io(phba);
1396 return;
1397 }
1398 lpfc_unblock_mgmt_io(phba);
1399 } else if (phba->work_hs & HS_CRIT_TEMP) {
1400 temperature = readl(phba->MBslimaddr + TEMPERATURE_OFFSET);
1401 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
1402 temp_event_data.event_code = LPFC_CRIT_TEMP;
1403 temp_event_data.data = (uint32_t)temperature;
1404
1405 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1406 "0406 Adapter maximum temperature exceeded "
1407 "(%ld), taking this port offline "
1408 "Data: x%x x%x x%x\n",
1409 temperature, phba->work_hs,
1410 phba->work_status[0], phba->work_status[1]);
1411
1412 shost = lpfc_shost_from_vport(phba->pport);
1413 fc_host_post_vendor_event(shost, fc_get_event_number(),
1414 sizeof(temp_event_data),
1415 (char *) &temp_event_data,
1416 SCSI_NL_VID_TYPE_PCI
1417 | PCI_VENDOR_ID_EMULEX);
1418
1419 spin_lock_irq(&phba->hbalock);
1420 phba->over_temp_state = HBA_OVER_TEMP;
1421 spin_unlock_irq(&phba->hbalock);
1422 lpfc_offline_eratt(phba);
1423
1424 } else {
1425
1426
1427
1428
1429 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1430 "0457 Adapter Hardware Error "
1431 "Data: x%x x%x x%x\n",
1432 phba->work_hs,
1433 phba->work_status[0], phba->work_status[1]);
1434
1435 event_data = FC_REG_DUMP_EVENT;
1436 shost = lpfc_shost_from_vport(vport);
1437 fc_host_post_vendor_event(shost, fc_get_event_number(),
1438 sizeof(event_data), (char *) &event_data,
1439 SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX);
1440
1441 lpfc_offline_eratt(phba);
1442 }
1443 return;
1444}
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457static int
1458lpfc_sli4_port_sta_fn_reset(struct lpfc_hba *phba, int mbx_action)
1459{
1460 int rc;
1461 uint32_t intr_mode;
1462
1463
1464
1465
1466
1467 rc = lpfc_sli4_pdev_status_reg_wait(phba);
1468 if (!rc) {
1469
1470 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1471 "2887 Reset Needed: Attempting Port "
1472 "Recovery...\n");
1473 lpfc_offline_prep(phba, mbx_action);
1474 lpfc_offline(phba);
1475
1476 lpfc_sli4_disable_intr(phba);
1477 lpfc_sli_brdrestart(phba);
1478
1479 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
1480 if (intr_mode == LPFC_INTR_ERROR) {
1481 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1482 "3175 Failed to enable interrupt\n");
1483 return -EIO;
1484 } else {
1485 phba->intr_mode = intr_mode;
1486 }
1487 rc = lpfc_online(phba);
1488 if (rc == 0)
1489 lpfc_unblock_mgmt_io(phba);
1490 }
1491 return rc;
1492}
1493
1494
1495
1496
1497
1498
1499
1500
1501static void
1502lpfc_handle_eratt_s4(struct lpfc_hba *phba)
1503{
1504 struct lpfc_vport *vport = phba->pport;
1505 uint32_t event_data;
1506 struct Scsi_Host *shost;
1507 uint32_t if_type;
1508 struct lpfc_register portstat_reg = {0};
1509 uint32_t reg_err1, reg_err2;
1510 uint32_t uerrlo_reg, uemasklo_reg;
1511 uint32_t pci_rd_rc1, pci_rd_rc2;
1512 int rc;
1513
1514
1515
1516
1517 if (pci_channel_offline(phba->pcidev))
1518 return;
1519
1520 if (!phba->cfg_enable_hba_reset)
1521 return;
1522
1523 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
1524 switch (if_type) {
1525 case LPFC_SLI_INTF_IF_TYPE_0:
1526 pci_rd_rc1 = lpfc_readl(
1527 phba->sli4_hba.u.if_type0.UERRLOregaddr,
1528 &uerrlo_reg);
1529 pci_rd_rc2 = lpfc_readl(
1530 phba->sli4_hba.u.if_type0.UEMASKLOregaddr,
1531 &uemasklo_reg);
1532
1533 if (pci_rd_rc1 == -EIO && pci_rd_rc2 == -EIO)
1534 return;
1535 lpfc_sli4_offline_eratt(phba);
1536 break;
1537 case LPFC_SLI_INTF_IF_TYPE_2:
1538 pci_rd_rc1 = lpfc_readl(
1539 phba->sli4_hba.u.if_type2.STATUSregaddr,
1540 &portstat_reg.word0);
1541
1542 if (pci_rd_rc1 == -EIO) {
1543 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1544 "3151 PCI bus read access failure: x%x\n",
1545 readl(phba->sli4_hba.u.if_type2.STATUSregaddr));
1546 return;
1547 }
1548 reg_err1 = readl(phba->sli4_hba.u.if_type2.ERR1regaddr);
1549 reg_err2 = readl(phba->sli4_hba.u.if_type2.ERR2regaddr);
1550 if (bf_get(lpfc_sliport_status_oti, &portstat_reg)) {
1551
1552 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1553 "2889 Port Overtemperature event, "
1554 "taking port offline\n");
1555 spin_lock_irq(&phba->hbalock);
1556 phba->over_temp_state = HBA_OVER_TEMP;
1557 spin_unlock_irq(&phba->hbalock);
1558 lpfc_sli4_offline_eratt(phba);
1559 break;
1560 }
1561 if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
1562 reg_err2 == SLIPORT_ERR2_REG_FW_RESTART)
1563 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1564 "3143 Port Down: Firmware Restarted\n");
1565 else if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
1566 reg_err2 == SLIPORT_ERR2_REG_FORCED_DUMP)
1567 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1568 "3144 Port Down: Debug Dump\n");
1569 else if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
1570 reg_err2 == SLIPORT_ERR2_REG_FUNC_PROVISON)
1571 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1572 "3145 Port Down: Provisioning\n");
1573
1574
1575 rc = lpfc_sli4_port_sta_fn_reset(phba, LPFC_MBX_NO_WAIT);
1576 if (rc == 0) {
1577
1578 if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
1579 reg_err2 == SLIPORT_ERR2_REG_FORCED_DUMP)
1580 return;
1581 else
1582 break;
1583 }
1584
1585 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1586 "3152 Unrecoverable error, bring the port "
1587 "offline\n");
1588 lpfc_sli4_offline_eratt(phba);
1589 break;
1590 case LPFC_SLI_INTF_IF_TYPE_1:
1591 default:
1592 break;
1593 }
1594 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
1595 "3123 Report dump event to upper layer\n");
1596
1597 lpfc_board_errevt_to_mgmt(phba);
1598
1599 event_data = FC_REG_DUMP_EVENT;
1600 shost = lpfc_shost_from_vport(vport);
1601 fc_host_post_vendor_event(shost, fc_get_event_number(),
1602 sizeof(event_data), (char *) &event_data,
1603 SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX);
1604}
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617void
1618lpfc_handle_eratt(struct lpfc_hba *phba)
1619{
1620 (*phba->lpfc_handle_eratt)(phba);
1621}
1622
1623
1624
1625
1626
1627
1628
1629
1630void
1631lpfc_handle_latt(struct lpfc_hba *phba)
1632{
1633 struct lpfc_vport *vport = phba->pport;
1634 struct lpfc_sli *psli = &phba->sli;
1635 LPFC_MBOXQ_t *pmb;
1636 volatile uint32_t control;
1637 struct lpfc_dmabuf *mp;
1638 int rc = 0;
1639
1640 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
1641 if (!pmb) {
1642 rc = 1;
1643 goto lpfc_handle_latt_err_exit;
1644 }
1645
1646 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
1647 if (!mp) {
1648 rc = 2;
1649 goto lpfc_handle_latt_free_pmb;
1650 }
1651
1652 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
1653 if (!mp->virt) {
1654 rc = 3;
1655 goto lpfc_handle_latt_free_mp;
1656 }
1657
1658
1659 lpfc_els_flush_all_cmd(phba);
1660
1661 psli->slistat.link_event++;
1662 lpfc_read_topology(phba, pmb, mp);
1663 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
1664 pmb->vport = vport;
1665
1666 phba->sli.ring[LPFC_ELS_RING].flag |= LPFC_STOP_IOCB_EVENT;
1667 rc = lpfc_sli_issue_mbox (phba, pmb, MBX_NOWAIT);
1668 if (rc == MBX_NOT_FINISHED) {
1669 rc = 4;
1670 goto lpfc_handle_latt_free_mbuf;
1671 }
1672
1673
1674 spin_lock_irq(&phba->hbalock);
1675 writel(HA_LATT, phba->HAregaddr);
1676 readl(phba->HAregaddr);
1677 spin_unlock_irq(&phba->hbalock);
1678
1679 return;
1680
1681lpfc_handle_latt_free_mbuf:
1682 phba->sli.ring[LPFC_ELS_RING].flag &= ~LPFC_STOP_IOCB_EVENT;
1683 lpfc_mbuf_free(phba, mp->virt, mp->phys);
1684lpfc_handle_latt_free_mp:
1685 kfree(mp);
1686lpfc_handle_latt_free_pmb:
1687 mempool_free(pmb, phba->mbox_mem_pool);
1688lpfc_handle_latt_err_exit:
1689
1690 spin_lock_irq(&phba->hbalock);
1691 psli->sli_flag |= LPFC_PROCESS_LA;
1692 control = readl(phba->HCregaddr);
1693 control |= HC_LAINT_ENA;
1694 writel(control, phba->HCregaddr);
1695 readl(phba->HCregaddr);
1696
1697
1698 writel(HA_LATT, phba->HAregaddr);
1699 readl(phba->HAregaddr);
1700 spin_unlock_irq(&phba->hbalock);
1701 lpfc_linkdown(phba);
1702 phba->link_state = LPFC_HBA_ERROR;
1703
1704 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX,
1705 "0300 LATT: Cannot issue READ_LA: Data:%d\n", rc);
1706
1707 return;
1708}
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724int
1725lpfc_parse_vpd(struct lpfc_hba *phba, uint8_t *vpd, int len)
1726{
1727 uint8_t lenlo, lenhi;
1728 int Length;
1729 int i, j;
1730 int finished = 0;
1731 int index = 0;
1732
1733 if (!vpd)
1734 return 0;
1735
1736
1737 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
1738 "0455 Vital Product Data: x%x x%x x%x x%x\n",
1739 (uint32_t) vpd[0], (uint32_t) vpd[1], (uint32_t) vpd[2],
1740 (uint32_t) vpd[3]);
1741 while (!finished && (index < (len - 4))) {
1742 switch (vpd[index]) {
1743 case 0x82:
1744 case 0x91:
1745 index += 1;
1746 lenlo = vpd[index];
1747 index += 1;
1748 lenhi = vpd[index];
1749 index += 1;
1750 i = ((((unsigned short)lenhi) << 8) + lenlo);
1751 index += i;
1752 break;
1753 case 0x90:
1754 index += 1;
1755 lenlo = vpd[index];
1756 index += 1;
1757 lenhi = vpd[index];
1758 index += 1;
1759 Length = ((((unsigned short)lenhi) << 8) + lenlo);
1760 if (Length > len - index)
1761 Length = len - index;
1762 while (Length > 0) {
1763
1764 if ((vpd[index] == 'S') && (vpd[index+1] == 'N')) {
1765 index += 2;
1766 i = vpd[index];
1767 index += 1;
1768 j = 0;
1769 Length -= (3+i);
1770 while(i--) {
1771 phba->SerialNumber[j++] = vpd[index++];
1772 if (j == 31)
1773 break;
1774 }
1775 phba->SerialNumber[j] = 0;
1776 continue;
1777 }
1778 else if ((vpd[index] == 'V') && (vpd[index+1] == '1')) {
1779 phba->vpd_flag |= VPD_MODEL_DESC;
1780 index += 2;
1781 i = vpd[index];
1782 index += 1;
1783 j = 0;
1784 Length -= (3+i);
1785 while(i--) {
1786 phba->ModelDesc[j++] = vpd[index++];
1787 if (j == 255)
1788 break;
1789 }
1790 phba->ModelDesc[j] = 0;
1791 continue;
1792 }
1793 else if ((vpd[index] == 'V') && (vpd[index+1] == '2')) {
1794 phba->vpd_flag |= VPD_MODEL_NAME;
1795 index += 2;
1796 i = vpd[index];
1797 index += 1;
1798 j = 0;
1799 Length -= (3+i);
1800 while(i--) {
1801 phba->ModelName[j++] = vpd[index++];
1802 if (j == 79)
1803 break;
1804 }
1805 phba->ModelName[j] = 0;
1806 continue;
1807 }
1808 else if ((vpd[index] == 'V') && (vpd[index+1] == '3')) {
1809 phba->vpd_flag |= VPD_PROGRAM_TYPE;
1810 index += 2;
1811 i = vpd[index];
1812 index += 1;
1813 j = 0;
1814 Length -= (3+i);
1815 while(i--) {
1816 phba->ProgramType[j++] = vpd[index++];
1817 if (j == 255)
1818 break;
1819 }
1820 phba->ProgramType[j] = 0;
1821 continue;
1822 }
1823 else if ((vpd[index] == 'V') && (vpd[index+1] == '4')) {
1824 phba->vpd_flag |= VPD_PORT;
1825 index += 2;
1826 i = vpd[index];
1827 index += 1;
1828 j = 0;
1829 Length -= (3+i);
1830 while(i--) {
1831 if ((phba->sli_rev == LPFC_SLI_REV4) &&
1832 (phba->sli4_hba.pport_name_sta ==
1833 LPFC_SLI4_PPNAME_GET)) {
1834 j++;
1835 index++;
1836 } else
1837 phba->Port[j++] = vpd[index++];
1838 if (j == 19)
1839 break;
1840 }
1841 if ((phba->sli_rev != LPFC_SLI_REV4) ||
1842 (phba->sli4_hba.pport_name_sta ==
1843 LPFC_SLI4_PPNAME_NON))
1844 phba->Port[j] = 0;
1845 continue;
1846 }
1847 else {
1848 index += 2;
1849 i = vpd[index];
1850 index += 1;
1851 index += i;
1852 Length -= (3 + i);
1853 }
1854 }
1855 finished = 0;
1856 break;
1857 case 0x78:
1858 finished = 1;
1859 break;
1860 default:
1861 index ++;
1862 break;
1863 }
1864 }
1865
1866 return(1);
1867}
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881static void
1882lpfc_get_hba_model_desc(struct lpfc_hba *phba, uint8_t *mdp, uint8_t *descp)
1883{
1884 lpfc_vpd_t *vp;
1885 uint16_t dev_id = phba->pcidev->device;
1886 int max_speed;
1887 int GE = 0;
1888 int oneConnect = 0;
1889 struct {
1890 char *name;
1891 char *bus;
1892 char *function;
1893 } m = {"<Unknown>", "", ""};
1894
1895 if (mdp && mdp[0] != '\0'
1896 && descp && descp[0] != '\0')
1897 return;
1898
1899 if (phba->lmt & LMT_16Gb)
1900 max_speed = 16;
1901 else if (phba->lmt & LMT_10Gb)
1902 max_speed = 10;
1903 else if (phba->lmt & LMT_8Gb)
1904 max_speed = 8;
1905 else if (phba->lmt & LMT_4Gb)
1906 max_speed = 4;
1907 else if (phba->lmt & LMT_2Gb)
1908 max_speed = 2;
1909 else if (phba->lmt & LMT_1Gb)
1910 max_speed = 1;
1911 else
1912 max_speed = 0;
1913
1914 vp = &phba->vpd;
1915
1916 switch (dev_id) {
1917 case PCI_DEVICE_ID_FIREFLY:
1918 m = (typeof(m)){"LP6000", "PCI", "Fibre Channel Adapter"};
1919 break;
1920 case PCI_DEVICE_ID_SUPERFLY:
1921 if (vp->rev.biuRev >= 1 && vp->rev.biuRev <= 3)
1922 m = (typeof(m)){"LP7000", "PCI",
1923 "Fibre Channel Adapter"};
1924 else
1925 m = (typeof(m)){"LP7000E", "PCI",
1926 "Fibre Channel Adapter"};
1927 break;
1928 case PCI_DEVICE_ID_DRAGONFLY:
1929 m = (typeof(m)){"LP8000", "PCI",
1930 "Fibre Channel Adapter"};
1931 break;
1932 case PCI_DEVICE_ID_CENTAUR:
1933 if (FC_JEDEC_ID(vp->rev.biuRev) == CENTAUR_2G_JEDEC_ID)
1934 m = (typeof(m)){"LP9002", "PCI",
1935 "Fibre Channel Adapter"};
1936 else
1937 m = (typeof(m)){"LP9000", "PCI",
1938 "Fibre Channel Adapter"};
1939 break;
1940 case PCI_DEVICE_ID_RFLY:
1941 m = (typeof(m)){"LP952", "PCI",
1942 "Fibre Channel Adapter"};
1943 break;
1944 case PCI_DEVICE_ID_PEGASUS:
1945 m = (typeof(m)){"LP9802", "PCI-X",
1946 "Fibre Channel Adapter"};
1947 break;
1948 case PCI_DEVICE_ID_THOR:
1949 m = (typeof(m)){"LP10000", "PCI-X",
1950 "Fibre Channel Adapter"};
1951 break;
1952 case PCI_DEVICE_ID_VIPER:
1953 m = (typeof(m)){"LPX1000", "PCI-X",
1954 "Fibre Channel Adapter"};
1955 break;
1956 case PCI_DEVICE_ID_PFLY:
1957 m = (typeof(m)){"LP982", "PCI-X",
1958 "Fibre Channel Adapter"};
1959 break;
1960 case PCI_DEVICE_ID_TFLY:
1961 m = (typeof(m)){"LP1050", "PCI-X",
1962 "Fibre Channel Adapter"};
1963 break;
1964 case PCI_DEVICE_ID_HELIOS:
1965 m = (typeof(m)){"LP11000", "PCI-X2",
1966 "Fibre Channel Adapter"};
1967 break;
1968 case PCI_DEVICE_ID_HELIOS_SCSP:
1969 m = (typeof(m)){"LP11000-SP", "PCI-X2",
1970 "Fibre Channel Adapter"};
1971 break;
1972 case PCI_DEVICE_ID_HELIOS_DCSP:
1973 m = (typeof(m)){"LP11002-SP", "PCI-X2",
1974 "Fibre Channel Adapter"};
1975 break;
1976 case PCI_DEVICE_ID_NEPTUNE:
1977 m = (typeof(m)){"LPe1000", "PCIe", "Fibre Channel Adapter"};
1978 break;
1979 case PCI_DEVICE_ID_NEPTUNE_SCSP:
1980 m = (typeof(m)){"LPe1000-SP", "PCIe", "Fibre Channel Adapter"};
1981 break;
1982 case PCI_DEVICE_ID_NEPTUNE_DCSP:
1983 m = (typeof(m)){"LPe1002-SP", "PCIe", "Fibre Channel Adapter"};
1984 break;
1985 case PCI_DEVICE_ID_BMID:
1986 m = (typeof(m)){"LP1150", "PCI-X2", "Fibre Channel Adapter"};
1987 break;
1988 case PCI_DEVICE_ID_BSMB:
1989 m = (typeof(m)){"LP111", "PCI-X2", "Fibre Channel Adapter"};
1990 break;
1991 case PCI_DEVICE_ID_ZEPHYR:
1992 m = (typeof(m)){"LPe11000", "PCIe", "Fibre Channel Adapter"};
1993 break;
1994 case PCI_DEVICE_ID_ZEPHYR_SCSP:
1995 m = (typeof(m)){"LPe11000", "PCIe", "Fibre Channel Adapter"};
1996 break;
1997 case PCI_DEVICE_ID_ZEPHYR_DCSP:
1998 m = (typeof(m)){"LP2105", "PCIe", "FCoE Adapter"};
1999 GE = 1;
2000 break;
2001 case PCI_DEVICE_ID_ZMID:
2002 m = (typeof(m)){"LPe1150", "PCIe", "Fibre Channel Adapter"};
2003 break;
2004 case PCI_DEVICE_ID_ZSMB:
2005 m = (typeof(m)){"LPe111", "PCIe", "Fibre Channel Adapter"};
2006 break;
2007 case PCI_DEVICE_ID_LP101:
2008 m = (typeof(m)){"LP101", "PCI-X", "Fibre Channel Adapter"};
2009 break;
2010 case PCI_DEVICE_ID_LP10000S:
2011 m = (typeof(m)){"LP10000-S", "PCI", "Fibre Channel Adapter"};
2012 break;
2013 case PCI_DEVICE_ID_LP11000S:
2014 m = (typeof(m)){"LP11000-S", "PCI-X2", "Fibre Channel Adapter"};
2015 break;
2016 case PCI_DEVICE_ID_LPE11000S:
2017 m = (typeof(m)){"LPe11000-S", "PCIe", "Fibre Channel Adapter"};
2018 break;
2019 case PCI_DEVICE_ID_SAT:
2020 m = (typeof(m)){"LPe12000", "PCIe", "Fibre Channel Adapter"};
2021 break;
2022 case PCI_DEVICE_ID_SAT_MID:
2023 m = (typeof(m)){"LPe1250", "PCIe", "Fibre Channel Adapter"};
2024 break;
2025 case PCI_DEVICE_ID_SAT_SMB:
2026 m = (typeof(m)){"LPe121", "PCIe", "Fibre Channel Adapter"};
2027 break;
2028 case PCI_DEVICE_ID_SAT_DCSP:
2029 m = (typeof(m)){"LPe12002-SP", "PCIe", "Fibre Channel Adapter"};
2030 break;
2031 case PCI_DEVICE_ID_SAT_SCSP:
2032 m = (typeof(m)){"LPe12000-SP", "PCIe", "Fibre Channel Adapter"};
2033 break;
2034 case PCI_DEVICE_ID_SAT_S:
2035 m = (typeof(m)){"LPe12000-S", "PCIe", "Fibre Channel Adapter"};
2036 break;
2037 case PCI_DEVICE_ID_HORNET:
2038 m = (typeof(m)){"LP21000", "PCIe", "FCoE Adapter"};
2039 GE = 1;
2040 break;
2041 case PCI_DEVICE_ID_PROTEUS_VF:
2042 m = (typeof(m)){"LPev12000", "PCIe IOV",
2043 "Fibre Channel Adapter"};
2044 break;
2045 case PCI_DEVICE_ID_PROTEUS_PF:
2046 m = (typeof(m)){"LPev12000", "PCIe IOV",
2047 "Fibre Channel Adapter"};
2048 break;
2049 case PCI_DEVICE_ID_PROTEUS_S:
2050 m = (typeof(m)){"LPemv12002-S", "PCIe IOV",
2051 "Fibre Channel Adapter"};
2052 break;
2053 case PCI_DEVICE_ID_TIGERSHARK:
2054 oneConnect = 1;
2055 m = (typeof(m)){"OCe10100", "PCIe", "FCoE"};
2056 break;
2057 case PCI_DEVICE_ID_TOMCAT:
2058 oneConnect = 1;
2059 m = (typeof(m)){"OCe11100", "PCIe", "FCoE"};
2060 break;
2061 case PCI_DEVICE_ID_FALCON:
2062 m = (typeof(m)){"LPSe12002-ML1-E", "PCIe",
2063 "EmulexSecure Fibre"};
2064 break;
2065 case PCI_DEVICE_ID_BALIUS:
2066 m = (typeof(m)){"LPVe12002", "PCIe Shared I/O",
2067 "Fibre Channel Adapter"};
2068 break;
2069 case PCI_DEVICE_ID_LANCER_FC:
2070 case PCI_DEVICE_ID_LANCER_FC_VF:
2071 m = (typeof(m)){"LPe16000", "PCIe", "Fibre Channel Adapter"};
2072 break;
2073 case PCI_DEVICE_ID_LANCER_FCOE:
2074 case PCI_DEVICE_ID_LANCER_FCOE_VF:
2075 oneConnect = 1;
2076 m = (typeof(m)){"OCe15100", "PCIe", "FCoE"};
2077 break;
2078 case PCI_DEVICE_ID_SKYHAWK:
2079 case PCI_DEVICE_ID_SKYHAWK_VF:
2080 oneConnect = 1;
2081 m = (typeof(m)){"OCe14000", "PCIe", "FCoE"};
2082 break;
2083 default:
2084 m = (typeof(m)){"Unknown", "", ""};
2085 break;
2086 }
2087
2088 if (mdp && mdp[0] == '\0')
2089 snprintf(mdp, 79,"%s", m.name);
2090
2091
2092
2093
2094 if (descp && descp[0] == '\0') {
2095 if (oneConnect)
2096 snprintf(descp, 255,
2097 "Emulex OneConnect %s, %s Initiator %s",
2098 m.name, m.function,
2099 phba->Port);
2100 else if (max_speed == 0)
2101 snprintf(descp, 255,
2102 "Emulex %s %s %s ",
2103 m.name, m.bus, m.function);
2104 else
2105 snprintf(descp, 255,
2106 "Emulex %s %d%s %s %s",
2107 m.name, max_speed, (GE) ? "GE" : "Gb",
2108 m.bus, m.function);
2109 }
2110}
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124int
2125lpfc_post_buffer(struct lpfc_hba *phba, struct lpfc_sli_ring *pring, int cnt)
2126{
2127 IOCB_t *icmd;
2128 struct lpfc_iocbq *iocb;
2129 struct lpfc_dmabuf *mp1, *mp2;
2130
2131 cnt += pring->missbufcnt;
2132
2133
2134 while (cnt > 0) {
2135
2136 iocb = lpfc_sli_get_iocbq(phba);
2137 if (iocb == NULL) {
2138 pring->missbufcnt = cnt;
2139 return cnt;
2140 }
2141 icmd = &iocb->iocb;
2142
2143
2144
2145 mp1 = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL);
2146 if (mp1)
2147 mp1->virt = lpfc_mbuf_alloc(phba, MEM_PRI, &mp1->phys);
2148 if (!mp1 || !mp1->virt) {
2149 kfree(mp1);
2150 lpfc_sli_release_iocbq(phba, iocb);
2151 pring->missbufcnt = cnt;
2152 return cnt;
2153 }
2154
2155 INIT_LIST_HEAD(&mp1->list);
2156
2157 if (cnt > 1) {
2158 mp2 = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL);
2159 if (mp2)
2160 mp2->virt = lpfc_mbuf_alloc(phba, MEM_PRI,
2161 &mp2->phys);
2162 if (!mp2 || !mp2->virt) {
2163 kfree(mp2);
2164 lpfc_mbuf_free(phba, mp1->virt, mp1->phys);
2165 kfree(mp1);
2166 lpfc_sli_release_iocbq(phba, iocb);
2167 pring->missbufcnt = cnt;
2168 return cnt;
2169 }
2170
2171 INIT_LIST_HEAD(&mp2->list);
2172 } else {
2173 mp2 = NULL;
2174 }
2175
2176 icmd->un.cont64[0].addrHigh = putPaddrHigh(mp1->phys);
2177 icmd->un.cont64[0].addrLow = putPaddrLow(mp1->phys);
2178 icmd->un.cont64[0].tus.f.bdeSize = FCELSSIZE;
2179 icmd->ulpBdeCount = 1;
2180 cnt--;
2181 if (mp2) {
2182 icmd->un.cont64[1].addrHigh = putPaddrHigh(mp2->phys);
2183 icmd->un.cont64[1].addrLow = putPaddrLow(mp2->phys);
2184 icmd->un.cont64[1].tus.f.bdeSize = FCELSSIZE;
2185 cnt--;
2186 icmd->ulpBdeCount = 2;
2187 }
2188
2189 icmd->ulpCommand = CMD_QUE_RING_BUF64_CN;
2190 icmd->ulpLe = 1;
2191
2192 if (lpfc_sli_issue_iocb(phba, pring->ringno, iocb, 0) ==
2193 IOCB_ERROR) {
2194 lpfc_mbuf_free(phba, mp1->virt, mp1->phys);
2195 kfree(mp1);
2196 cnt++;
2197 if (mp2) {
2198 lpfc_mbuf_free(phba, mp2->virt, mp2->phys);
2199 kfree(mp2);
2200 cnt++;
2201 }
2202 lpfc_sli_release_iocbq(phba, iocb);
2203 pring->missbufcnt = cnt;
2204 return cnt;
2205 }
2206 lpfc_sli_ringpostbuf_put(phba, pring, mp1);
2207 if (mp2)
2208 lpfc_sli_ringpostbuf_put(phba, pring, mp2);
2209 }
2210 pring->missbufcnt = 0;
2211 return 0;
2212}
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225static int
2226lpfc_post_rcv_buf(struct lpfc_hba *phba)
2227{
2228 struct lpfc_sli *psli = &phba->sli;
2229
2230
2231 lpfc_post_buffer(phba, &psli->ring[LPFC_ELS_RING], LPFC_BUF_RING0);
2232
2233
2234 return 0;
2235}
2236
2237#define S(N,V) (((V)<<(N))|((V)>>(32-(N))))
2238
2239
2240
2241
2242
2243
2244
2245
2246static void
2247lpfc_sha_init(uint32_t * HashResultPointer)
2248{
2249 HashResultPointer[0] = 0x67452301;
2250 HashResultPointer[1] = 0xEFCDAB89;
2251 HashResultPointer[2] = 0x98BADCFE;
2252 HashResultPointer[3] = 0x10325476;
2253 HashResultPointer[4] = 0xC3D2E1F0;
2254}
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266static void
2267lpfc_sha_iterate(uint32_t * HashResultPointer, uint32_t * HashWorkingPointer)
2268{
2269 int t;
2270 uint32_t TEMP;
2271 uint32_t A, B, C, D, E;
2272 t = 16;
2273 do {
2274 HashWorkingPointer[t] =
2275 S(1,
2276 HashWorkingPointer[t - 3] ^ HashWorkingPointer[t -
2277 8] ^
2278 HashWorkingPointer[t - 14] ^ HashWorkingPointer[t - 16]);
2279 } while (++t <= 79);
2280 t = 0;
2281 A = HashResultPointer[0];
2282 B = HashResultPointer[1];
2283 C = HashResultPointer[2];
2284 D = HashResultPointer[3];
2285 E = HashResultPointer[4];
2286
2287 do {
2288 if (t < 20) {
2289 TEMP = ((B & C) | ((~B) & D)) + 0x5A827999;
2290 } else if (t < 40) {
2291 TEMP = (B ^ C ^ D) + 0x6ED9EBA1;
2292 } else if (t < 60) {
2293 TEMP = ((B & C) | (B & D) | (C & D)) + 0x8F1BBCDC;
2294 } else {
2295 TEMP = (B ^ C ^ D) + 0xCA62C1D6;
2296 }
2297 TEMP += S(5, A) + E + HashWorkingPointer[t];
2298 E = D;
2299 D = C;
2300 C = S(30, B);
2301 B = A;
2302 A = TEMP;
2303 } while (++t <= 79);
2304
2305 HashResultPointer[0] += A;
2306 HashResultPointer[1] += B;
2307 HashResultPointer[2] += C;
2308 HashResultPointer[3] += D;
2309 HashResultPointer[4] += E;
2310
2311}
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323static void
2324lpfc_challenge_key(uint32_t * RandomChallenge, uint32_t * HashWorking)
2325{
2326 *HashWorking = (*RandomChallenge ^ *HashWorking);
2327}
2328
2329
2330
2331
2332
2333
2334
2335
2336void
2337lpfc_hba_init(struct lpfc_hba *phba, uint32_t *hbainit)
2338{
2339 int t;
2340 uint32_t *HashWorking;
2341 uint32_t *pwwnn = (uint32_t *) phba->wwnn;
2342
2343 HashWorking = kcalloc(80, sizeof(uint32_t), GFP_KERNEL);
2344 if (!HashWorking)
2345 return;
2346
2347 HashWorking[0] = HashWorking[78] = *pwwnn++;
2348 HashWorking[1] = HashWorking[79] = *pwwnn;
2349
2350 for (t = 0; t < 7; t++)
2351 lpfc_challenge_key(phba->RandomData + t, HashWorking + t);
2352
2353 lpfc_sha_init(hbainit);
2354 lpfc_sha_iterate(hbainit, HashWorking);
2355 kfree(HashWorking);
2356}
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367void
2368lpfc_cleanup(struct lpfc_vport *vport)
2369{
2370 struct lpfc_hba *phba = vport->phba;
2371 struct lpfc_nodelist *ndlp, *next_ndlp;
2372 int i = 0;
2373
2374 if (phba->link_state > LPFC_LINK_DOWN)
2375 lpfc_port_link_failure(vport);
2376
2377 list_for_each_entry_safe(ndlp, next_ndlp, &vport->fc_nodes, nlp_listp) {
2378 if (!NLP_CHK_NODE_ACT(ndlp)) {
2379 ndlp = lpfc_enable_node(vport, ndlp,
2380 NLP_STE_UNUSED_NODE);
2381 if (!ndlp)
2382 continue;
2383 spin_lock_irq(&phba->ndlp_lock);
2384 NLP_SET_FREE_REQ(ndlp);
2385 spin_unlock_irq(&phba->ndlp_lock);
2386
2387 lpfc_nlp_put(ndlp);
2388 continue;
2389 }
2390 spin_lock_irq(&phba->ndlp_lock);
2391 if (NLP_CHK_FREE_REQ(ndlp)) {
2392
2393 spin_unlock_irq(&phba->ndlp_lock);
2394 continue;
2395 } else
2396
2397 NLP_SET_FREE_REQ(ndlp);
2398 spin_unlock_irq(&phba->ndlp_lock);
2399
2400 if (vport->port_type != LPFC_PHYSICAL_PORT &&
2401 ndlp->nlp_DID == Fabric_DID) {
2402
2403 lpfc_nlp_put(ndlp);
2404 continue;
2405 }
2406
2407
2408
2409
2410 if (ndlp->nlp_state == NLP_STE_UNUSED_NODE) {
2411 lpfc_nlp_put(ndlp);
2412 continue;
2413 }
2414
2415 if (ndlp->nlp_type & NLP_FABRIC)
2416 lpfc_disc_state_machine(vport, ndlp, NULL,
2417 NLP_EVT_DEVICE_RECOVERY);
2418
2419 lpfc_disc_state_machine(vport, ndlp, NULL,
2420 NLP_EVT_DEVICE_RM);
2421 }
2422
2423
2424
2425
2426
2427 while (!list_empty(&vport->fc_nodes)) {
2428 if (i++ > 3000) {
2429 lpfc_printf_vlog(vport, KERN_ERR, LOG_DISCOVERY,
2430 "0233 Nodelist not empty\n");
2431 list_for_each_entry_safe(ndlp, next_ndlp,
2432 &vport->fc_nodes, nlp_listp) {
2433 lpfc_printf_vlog(ndlp->vport, KERN_ERR,
2434 LOG_NODE,
2435 "0282 did:x%x ndlp:x%p "
2436 "usgmap:x%x refcnt:%d\n",
2437 ndlp->nlp_DID, (void *)ndlp,
2438 ndlp->nlp_usg_map,
2439 atomic_read(
2440 &ndlp->kref.refcount));
2441 }
2442 break;
2443 }
2444
2445
2446 msleep(10);
2447 }
2448 lpfc_cleanup_vports_rrqs(vport, NULL);
2449}
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459void
2460lpfc_stop_vport_timers(struct lpfc_vport *vport)
2461{
2462 del_timer_sync(&vport->els_tmofunc);
2463 del_timer_sync(&vport->fc_fdmitmo);
2464 del_timer_sync(&vport->delayed_disc_tmo);
2465 lpfc_can_disctmo(vport);
2466 return;
2467}
2468
2469
2470
2471
2472
2473
2474
2475
2476void
2477__lpfc_sli4_stop_fcf_redisc_wait_timer(struct lpfc_hba *phba)
2478{
2479
2480 phba->fcf.fcf_flag &= ~FCF_REDISC_PEND;
2481
2482
2483 del_timer(&phba->fcf.redisc_wait);
2484}
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495void
2496lpfc_sli4_stop_fcf_redisc_wait_timer(struct lpfc_hba *phba)
2497{
2498 spin_lock_irq(&phba->hbalock);
2499 if (!(phba->fcf.fcf_flag & FCF_REDISC_PEND)) {
2500
2501 spin_unlock_irq(&phba->hbalock);
2502 return;
2503 }
2504 __lpfc_sli4_stop_fcf_redisc_wait_timer(phba);
2505
2506 phba->fcf.fcf_flag &= ~(FCF_DEAD_DISC | FCF_ACVL_DISC);
2507 spin_unlock_irq(&phba->hbalock);
2508}
2509
2510
2511
2512
2513
2514
2515
2516
2517void
2518lpfc_stop_hba_timers(struct lpfc_hba *phba)
2519{
2520 lpfc_stop_vport_timers(phba->pport);
2521 del_timer_sync(&phba->sli.mbox_tmo);
2522 del_timer_sync(&phba->fabric_block_timer);
2523 del_timer_sync(&phba->eratt_poll);
2524 del_timer_sync(&phba->hb_tmofunc);
2525 if (phba->sli_rev == LPFC_SLI_REV4) {
2526 del_timer_sync(&phba->rrq_tmr);
2527 phba->hba_flag &= ~HBA_RRQ_ACTIVE;
2528 }
2529 phba->hb_outstanding = 0;
2530
2531 switch (phba->pci_dev_grp) {
2532 case LPFC_PCI_DEV_LP:
2533
2534 del_timer_sync(&phba->fcp_poll_timer);
2535 break;
2536 case LPFC_PCI_DEV_OC:
2537
2538 lpfc_sli4_stop_fcf_redisc_wait_timer(phba);
2539 break;
2540 default:
2541 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
2542 "0297 Invalid device group (x%x)\n",
2543 phba->pci_dev_grp);
2544 break;
2545 }
2546 return;
2547}
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559static void
2560lpfc_block_mgmt_io(struct lpfc_hba *phba, int mbx_action)
2561{
2562 unsigned long iflag;
2563 uint8_t actcmd = MBX_HEARTBEAT;
2564 unsigned long timeout;
2565
2566 spin_lock_irqsave(&phba->hbalock, iflag);
2567 phba->sli.sli_flag |= LPFC_BLOCK_MGMT_IO;
2568 spin_unlock_irqrestore(&phba->hbalock, iflag);
2569 if (mbx_action == LPFC_MBX_NO_WAIT)
2570 return;
2571 timeout = msecs_to_jiffies(LPFC_MBOX_TMO * 1000) + jiffies;
2572 spin_lock_irqsave(&phba->hbalock, iflag);
2573 if (phba->sli.mbox_active) {
2574 actcmd = phba->sli.mbox_active->u.mb.mbxCommand;
2575
2576
2577
2578 timeout = msecs_to_jiffies(lpfc_mbox_tmo_val(phba,
2579 phba->sli.mbox_active) * 1000) + jiffies;
2580 }
2581 spin_unlock_irqrestore(&phba->hbalock, iflag);
2582
2583
2584 while (phba->sli.mbox_active) {
2585
2586 msleep(2);
2587 if (time_after(jiffies, timeout)) {
2588 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
2589 "2813 Mgmt IO is Blocked %x "
2590 "- mbox cmd %x still active\n",
2591 phba->sli.sli_flag, actcmd);
2592 break;
2593 }
2594 }
2595}
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605void
2606lpfc_sli4_node_prep(struct lpfc_hba *phba)
2607{
2608 struct lpfc_nodelist *ndlp, *next_ndlp;
2609 struct lpfc_vport **vports;
2610 int i;
2611
2612 if (phba->sli_rev != LPFC_SLI_REV4)
2613 return;
2614
2615 vports = lpfc_create_vport_work_array(phba);
2616 if (vports != NULL) {
2617 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
2618 if (vports[i]->load_flag & FC_UNLOADING)
2619 continue;
2620
2621 list_for_each_entry_safe(ndlp, next_ndlp,
2622 &vports[i]->fc_nodes,
2623 nlp_listp) {
2624 if (NLP_CHK_NODE_ACT(ndlp))
2625 ndlp->nlp_rpi =
2626 lpfc_sli4_alloc_rpi(phba);
2627 }
2628 }
2629 }
2630 lpfc_destroy_vport_work_array(phba, vports);
2631}
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645int
2646lpfc_online(struct lpfc_hba *phba)
2647{
2648 struct lpfc_vport *vport;
2649 struct lpfc_vport **vports;
2650 int i;
2651 bool vpis_cleared = false;
2652
2653 if (!phba)
2654 return 0;
2655 vport = phba->pport;
2656
2657 if (!(vport->fc_flag & FC_OFFLINE_MODE))
2658 return 0;
2659
2660 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
2661 "0458 Bring Adapter online\n");
2662
2663 lpfc_block_mgmt_io(phba, LPFC_MBX_WAIT);
2664
2665 if (!lpfc_sli_queue_setup(phba)) {
2666 lpfc_unblock_mgmt_io(phba);
2667 return 1;
2668 }
2669
2670 if (phba->sli_rev == LPFC_SLI_REV4) {
2671 if (lpfc_sli4_hba_setup(phba)) {
2672 lpfc_unblock_mgmt_io(phba);
2673 return 1;
2674 }
2675 spin_lock_irq(&phba->hbalock);
2676 if (!phba->sli4_hba.max_cfg_param.vpi_used)
2677 vpis_cleared = true;
2678 spin_unlock_irq(&phba->hbalock);
2679 } else {
2680 if (lpfc_sli_hba_setup(phba)) {
2681 lpfc_unblock_mgmt_io(phba);
2682 return 1;
2683 }
2684 }
2685
2686 vports = lpfc_create_vport_work_array(phba);
2687 if (vports != NULL)
2688 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
2689 struct Scsi_Host *shost;
2690 shost = lpfc_shost_from_vport(vports[i]);
2691 spin_lock_irq(shost->host_lock);
2692 vports[i]->fc_flag &= ~FC_OFFLINE_MODE;
2693 if (phba->sli3_options & LPFC_SLI3_NPIV_ENABLED)
2694 vports[i]->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
2695 if (phba->sli_rev == LPFC_SLI_REV4) {
2696 vports[i]->fc_flag |= FC_VPORT_NEEDS_INIT_VPI;
2697 if ((vpis_cleared) &&
2698 (vports[i]->port_type !=
2699 LPFC_PHYSICAL_PORT))
2700 vports[i]->vpi = 0;
2701 }
2702 spin_unlock_irq(shost->host_lock);
2703 }
2704 lpfc_destroy_vport_work_array(phba, vports);
2705
2706 lpfc_unblock_mgmt_io(phba);
2707 return 0;
2708}
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721void
2722lpfc_unblock_mgmt_io(struct lpfc_hba * phba)
2723{
2724 unsigned long iflag;
2725
2726 spin_lock_irqsave(&phba->hbalock, iflag);
2727 phba->sli.sli_flag &= ~LPFC_BLOCK_MGMT_IO;
2728 spin_unlock_irqrestore(&phba->hbalock, iflag);
2729}
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739void
2740lpfc_offline_prep(struct lpfc_hba *phba, int mbx_action)
2741{
2742 struct lpfc_vport *vport = phba->pport;
2743 struct lpfc_nodelist *ndlp, *next_ndlp;
2744 struct lpfc_vport **vports;
2745 struct Scsi_Host *shost;
2746 int i;
2747
2748 if (vport->fc_flag & FC_OFFLINE_MODE)
2749 return;
2750
2751 lpfc_block_mgmt_io(phba, mbx_action);
2752
2753 lpfc_linkdown(phba);
2754
2755
2756 vports = lpfc_create_vport_work_array(phba);
2757 if (vports != NULL) {
2758 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
2759 if (vports[i]->load_flag & FC_UNLOADING)
2760 continue;
2761 shost = lpfc_shost_from_vport(vports[i]);
2762 spin_lock_irq(shost->host_lock);
2763 vports[i]->vpi_state &= ~LPFC_VPI_REGISTERED;
2764 vports[i]->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
2765 vports[i]->fc_flag &= ~FC_VFI_REGISTERED;
2766 spin_unlock_irq(shost->host_lock);
2767
2768 shost = lpfc_shost_from_vport(vports[i]);
2769 list_for_each_entry_safe(ndlp, next_ndlp,
2770 &vports[i]->fc_nodes,
2771 nlp_listp) {
2772 if (!NLP_CHK_NODE_ACT(ndlp))
2773 continue;
2774 if (ndlp->nlp_state == NLP_STE_UNUSED_NODE)
2775 continue;
2776 if (ndlp->nlp_type & NLP_FABRIC) {
2777 lpfc_disc_state_machine(vports[i], ndlp,
2778 NULL, NLP_EVT_DEVICE_RECOVERY);
2779 lpfc_disc_state_machine(vports[i], ndlp,
2780 NULL, NLP_EVT_DEVICE_RM);
2781 }
2782 spin_lock_irq(shost->host_lock);
2783 ndlp->nlp_flag &= ~NLP_NPR_ADISC;
2784 spin_unlock_irq(shost->host_lock);
2785
2786
2787
2788
2789
2790 if (phba->sli_rev == LPFC_SLI_REV4)
2791 lpfc_sli4_free_rpi(phba, ndlp->nlp_rpi);
2792 lpfc_unreg_rpi(vports[i], ndlp);
2793 }
2794 }
2795 }
2796 lpfc_destroy_vport_work_array(phba, vports);
2797
2798 lpfc_sli_mbox_sys_shutdown(phba, mbx_action);
2799}
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809void
2810lpfc_offline(struct lpfc_hba *phba)
2811{
2812 struct Scsi_Host *shost;
2813 struct lpfc_vport **vports;
2814 int i;
2815
2816 if (phba->pport->fc_flag & FC_OFFLINE_MODE)
2817 return;
2818
2819
2820 lpfc_stop_port(phba);
2821 vports = lpfc_create_vport_work_array(phba);
2822 if (vports != NULL)
2823 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++)
2824 lpfc_stop_vport_timers(vports[i]);
2825 lpfc_destroy_vport_work_array(phba, vports);
2826 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
2827 "0460 Bring Adapter offline\n");
2828
2829
2830 lpfc_sli_hba_down(phba);
2831 spin_lock_irq(&phba->hbalock);
2832 phba->work_ha = 0;
2833 spin_unlock_irq(&phba->hbalock);
2834 vports = lpfc_create_vport_work_array(phba);
2835 if (vports != NULL)
2836 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
2837 shost = lpfc_shost_from_vport(vports[i]);
2838 spin_lock_irq(shost->host_lock);
2839 vports[i]->work_port_events = 0;
2840 vports[i]->fc_flag |= FC_OFFLINE_MODE;
2841 spin_unlock_irq(shost->host_lock);
2842 }
2843 lpfc_destroy_vport_work_array(phba, vports);
2844}
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854static void
2855lpfc_scsi_free(struct lpfc_hba *phba)
2856{
2857 struct lpfc_scsi_buf *sb, *sb_next;
2858 struct lpfc_iocbq *io, *io_next;
2859
2860 spin_lock_irq(&phba->hbalock);
2861
2862
2863
2864 spin_lock(&phba->scsi_buf_list_put_lock);
2865 list_for_each_entry_safe(sb, sb_next, &phba->lpfc_scsi_buf_list_put,
2866 list) {
2867 list_del(&sb->list);
2868 pci_pool_free(phba->lpfc_scsi_dma_buf_pool, sb->data,
2869 sb->dma_handle);
2870 kfree(sb);
2871 phba->total_scsi_bufs--;
2872 }
2873 spin_unlock(&phba->scsi_buf_list_put_lock);
2874
2875 spin_lock(&phba->scsi_buf_list_get_lock);
2876 list_for_each_entry_safe(sb, sb_next, &phba->lpfc_scsi_buf_list_get,
2877 list) {
2878 list_del(&sb->list);
2879 pci_pool_free(phba->lpfc_scsi_dma_buf_pool, sb->data,
2880 sb->dma_handle);
2881 kfree(sb);
2882 phba->total_scsi_bufs--;
2883 }
2884 spin_unlock(&phba->scsi_buf_list_get_lock);
2885
2886
2887 list_for_each_entry_safe(io, io_next, &phba->lpfc_iocb_list, list) {
2888 list_del(&io->list);
2889 kfree(io);
2890 phba->total_iocbq_bufs--;
2891 }
2892
2893 spin_unlock_irq(&phba->hbalock);
2894}
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908int
2909lpfc_sli4_xri_sgl_update(struct lpfc_hba *phba)
2910{
2911 struct lpfc_sglq *sglq_entry = NULL, *sglq_entry_next = NULL;
2912 struct lpfc_scsi_buf *psb = NULL, *psb_next = NULL;
2913 uint16_t i, lxri, xri_cnt, els_xri_cnt, scsi_xri_cnt;
2914 LIST_HEAD(els_sgl_list);
2915 LIST_HEAD(scsi_sgl_list);
2916 int rc;
2917
2918
2919
2920
2921 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
2922 if (els_xri_cnt > phba->sli4_hba.els_xri_cnt) {
2923
2924 xri_cnt = els_xri_cnt - phba->sli4_hba.els_xri_cnt;
2925 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
2926 "3157 ELS xri-sgl count increased from "
2927 "%d to %d\n", phba->sli4_hba.els_xri_cnt,
2928 els_xri_cnt);
2929
2930 for (i = 0; i < xri_cnt; i++) {
2931 sglq_entry = kzalloc(sizeof(struct lpfc_sglq),
2932 GFP_KERNEL);
2933 if (sglq_entry == NULL) {
2934 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
2935 "2562 Failure to allocate an "
2936 "ELS sgl entry:%d\n", i);
2937 rc = -ENOMEM;
2938 goto out_free_mem;
2939 }
2940 sglq_entry->buff_type = GEN_BUFF_TYPE;
2941 sglq_entry->virt = lpfc_mbuf_alloc(phba, 0,
2942 &sglq_entry->phys);
2943 if (sglq_entry->virt == NULL) {
2944 kfree(sglq_entry);
2945 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
2946 "2563 Failure to allocate an "
2947 "ELS mbuf:%d\n", i);
2948 rc = -ENOMEM;
2949 goto out_free_mem;
2950 }
2951 sglq_entry->sgl = sglq_entry->virt;
2952 memset(sglq_entry->sgl, 0, LPFC_BPL_SIZE);
2953 sglq_entry->state = SGL_FREED;
2954 list_add_tail(&sglq_entry->list, &els_sgl_list);
2955 }
2956 spin_lock_irq(&phba->hbalock);
2957 list_splice_init(&els_sgl_list, &phba->sli4_hba.lpfc_sgl_list);
2958 spin_unlock_irq(&phba->hbalock);
2959 } else if (els_xri_cnt < phba->sli4_hba.els_xri_cnt) {
2960
2961 xri_cnt = phba->sli4_hba.els_xri_cnt - els_xri_cnt;
2962 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
2963 "3158 ELS xri-sgl count decreased from "
2964 "%d to %d\n", phba->sli4_hba.els_xri_cnt,
2965 els_xri_cnt);
2966 spin_lock_irq(&phba->hbalock);
2967 list_splice_init(&phba->sli4_hba.lpfc_sgl_list, &els_sgl_list);
2968 spin_unlock_irq(&phba->hbalock);
2969
2970 for (i = 0; i < xri_cnt; i++) {
2971 list_remove_head(&els_sgl_list,
2972 sglq_entry, struct lpfc_sglq, list);
2973 if (sglq_entry) {
2974 lpfc_mbuf_free(phba, sglq_entry->virt,
2975 sglq_entry->phys);
2976 kfree(sglq_entry);
2977 }
2978 }
2979 spin_lock_irq(&phba->hbalock);
2980 list_splice_init(&els_sgl_list, &phba->sli4_hba.lpfc_sgl_list);
2981 spin_unlock_irq(&phba->hbalock);
2982 } else
2983 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
2984 "3163 ELS xri-sgl count unchanged: %d\n",
2985 els_xri_cnt);
2986 phba->sli4_hba.els_xri_cnt = els_xri_cnt;
2987
2988
2989 sglq_entry = NULL;
2990 sglq_entry_next = NULL;
2991 list_for_each_entry_safe(sglq_entry, sglq_entry_next,
2992 &phba->sli4_hba.lpfc_sgl_list, list) {
2993 lxri = lpfc_sli4_next_xritag(phba);
2994 if (lxri == NO_XRI) {
2995 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
2996 "2400 Failed to allocate xri for "
2997 "ELS sgl\n");
2998 rc = -ENOMEM;
2999 goto out_free_mem;
3000 }
3001 sglq_entry->sli4_lxritag = lxri;
3002 sglq_entry->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
3003 }
3004
3005
3006
3007
3008 phba->total_scsi_bufs = 0;
3009
3010
3011 phba->sli4_hba.scsi_xri_max = phba->sli4_hba.max_cfg_param.max_xri -
3012 els_xri_cnt;
3013
3014 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3015 "2401 Current allocated SCSI xri-sgl count:%d, "
3016 "maximum SCSI xri count:%d\n",
3017 phba->sli4_hba.scsi_xri_cnt,
3018 phba->sli4_hba.scsi_xri_max);
3019
3020 spin_lock_irq(&phba->scsi_buf_list_get_lock);
3021 spin_lock_irq(&phba->scsi_buf_list_put_lock);
3022 list_splice_init(&phba->lpfc_scsi_buf_list_get, &scsi_sgl_list);
3023 list_splice(&phba->lpfc_scsi_buf_list_put, &scsi_sgl_list);
3024 spin_unlock_irq(&phba->scsi_buf_list_put_lock);
3025 spin_unlock_irq(&phba->scsi_buf_list_get_lock);
3026
3027 if (phba->sli4_hba.scsi_xri_cnt > phba->sli4_hba.scsi_xri_max) {
3028
3029 scsi_xri_cnt = phba->sli4_hba.scsi_xri_cnt -
3030 phba->sli4_hba.scsi_xri_max;
3031
3032 for (i = 0; i < scsi_xri_cnt; i++) {
3033 list_remove_head(&scsi_sgl_list, psb,
3034 struct lpfc_scsi_buf, list);
3035 pci_pool_free(phba->lpfc_scsi_dma_buf_pool, psb->data,
3036 psb->dma_handle);
3037 kfree(psb);
3038 }
3039 spin_lock_irq(&phba->scsi_buf_list_get_lock);
3040 phba->sli4_hba.scsi_xri_cnt -= scsi_xri_cnt;
3041 spin_unlock_irq(&phba->scsi_buf_list_get_lock);
3042 }
3043
3044
3045 psb = NULL;
3046 psb_next = NULL;
3047 list_for_each_entry_safe(psb, psb_next, &scsi_sgl_list, list) {
3048 lxri = lpfc_sli4_next_xritag(phba);
3049 if (lxri == NO_XRI) {
3050 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3051 "2560 Failed to allocate xri for "
3052 "scsi buffer\n");
3053 rc = -ENOMEM;
3054 goto out_free_mem;
3055 }
3056 psb->cur_iocbq.sli4_lxritag = lxri;
3057 psb->cur_iocbq.sli4_xritag = phba->sli4_hba.xri_ids[lxri];
3058 }
3059 spin_lock_irq(&phba->scsi_buf_list_get_lock);
3060 spin_lock_irq(&phba->scsi_buf_list_put_lock);
3061 list_splice_init(&scsi_sgl_list, &phba->lpfc_scsi_buf_list_get);
3062 INIT_LIST_HEAD(&phba->lpfc_scsi_buf_list_put);
3063 spin_unlock_irq(&phba->scsi_buf_list_put_lock);
3064 spin_unlock_irq(&phba->scsi_buf_list_get_lock);
3065
3066 return 0;
3067
3068out_free_mem:
3069 lpfc_free_els_sgl_list(phba);
3070 lpfc_scsi_free(phba);
3071 return rc;
3072}
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090struct lpfc_vport *
3091lpfc_create_port(struct lpfc_hba *phba, int instance, struct device *dev)
3092{
3093 struct lpfc_vport *vport;
3094 struct Scsi_Host *shost;
3095 int error = 0;
3096
3097 if (dev != &phba->pcidev->dev)
3098 shost = scsi_host_alloc(&lpfc_vport_template,
3099 sizeof(struct lpfc_vport));
3100 else
3101 shost = scsi_host_alloc(&lpfc_template,
3102 sizeof(struct lpfc_vport));
3103 if (!shost)
3104 goto out;
3105
3106 vport = (struct lpfc_vport *) shost->hostdata;
3107 vport->phba = phba;
3108 vport->load_flag |= FC_LOADING;
3109 vport->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
3110 vport->fc_rscn_flush = 0;
3111
3112 lpfc_get_vport_cfgparam(vport);
3113 shost->unique_id = instance;
3114 shost->max_id = LPFC_MAX_TARGET;
3115 shost->max_lun = vport->cfg_max_luns;
3116 shost->this_id = -1;
3117 shost->max_cmd_len = 16;
3118 if (phba->sli_rev == LPFC_SLI_REV4) {
3119 shost->dma_boundary =
3120 phba->sli4_hba.pc_sli4_params.sge_supp_len-1;
3121 shost->sg_tablesize = phba->cfg_sg_seg_cnt;
3122 }
3123
3124
3125
3126
3127
3128
3129 shost->can_queue = phba->cfg_hba_queue_depth - 10;
3130 if (dev != &phba->pcidev->dev) {
3131 shost->transportt = lpfc_vport_transport_template;
3132 vport->port_type = LPFC_NPIV_PORT;
3133 } else {
3134 shost->transportt = lpfc_transport_template;
3135 vport->port_type = LPFC_PHYSICAL_PORT;
3136 }
3137
3138
3139 INIT_LIST_HEAD(&vport->fc_nodes);
3140 INIT_LIST_HEAD(&vport->rcv_buffer_list);
3141 spin_lock_init(&vport->work_port_lock);
3142
3143 init_timer(&vport->fc_disctmo);
3144 vport->fc_disctmo.function = lpfc_disc_timeout;
3145 vport->fc_disctmo.data = (unsigned long)vport;
3146
3147 init_timer(&vport->fc_fdmitmo);
3148 vport->fc_fdmitmo.function = lpfc_fdmi_tmo;
3149 vport->fc_fdmitmo.data = (unsigned long)vport;
3150
3151 init_timer(&vport->els_tmofunc);
3152 vport->els_tmofunc.function = lpfc_els_timeout;
3153 vport->els_tmofunc.data = (unsigned long)vport;
3154
3155 init_timer(&vport->delayed_disc_tmo);
3156 vport->delayed_disc_tmo.function = lpfc_delayed_disc_tmo;
3157 vport->delayed_disc_tmo.data = (unsigned long)vport;
3158
3159 error = scsi_add_host_with_dma(shost, dev, &phba->pcidev->dev);
3160 if (error)
3161 goto out_put_shost;
3162
3163 spin_lock_irq(&phba->hbalock);
3164 list_add_tail(&vport->listentry, &phba->port_list);
3165 spin_unlock_irq(&phba->hbalock);
3166 return vport;
3167
3168out_put_shost:
3169 scsi_host_put(shost);
3170out:
3171 return NULL;
3172}
3173
3174
3175
3176
3177
3178
3179
3180
3181void
3182destroy_port(struct lpfc_vport *vport)
3183{
3184 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
3185 struct lpfc_hba *phba = vport->phba;
3186
3187 lpfc_debugfs_terminate(vport);
3188 fc_remove_host(shost);
3189 scsi_remove_host(shost);
3190
3191 spin_lock_irq(&phba->hbalock);
3192 list_del_init(&vport->listentry);
3193 spin_unlock_irq(&phba->hbalock);
3194
3195 lpfc_cleanup(vport);
3196 return;
3197}
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209int
3210lpfc_get_instance(void)
3211{
3212 int ret;
3213
3214 ret = idr_alloc(&lpfc_hba_index, NULL, 0, 0, GFP_KERNEL);
3215 return ret < 0 ? -1 : ret;
3216}
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233int lpfc_scan_finished(struct Scsi_Host *shost, unsigned long time)
3234{
3235 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
3236 struct lpfc_hba *phba = vport->phba;
3237 int stat = 0;
3238
3239 spin_lock_irq(shost->host_lock);
3240
3241 if (vport->load_flag & FC_UNLOADING) {
3242 stat = 1;
3243 goto finished;
3244 }
3245 if (time >= msecs_to_jiffies(30 * 1000)) {
3246 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3247 "0461 Scanning longer than 30 "
3248 "seconds. Continuing initialization\n");
3249 stat = 1;
3250 goto finished;
3251 }
3252 if (time >= msecs_to_jiffies(15 * 1000) &&
3253 phba->link_state <= LPFC_LINK_DOWN) {
3254 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3255 "0465 Link down longer than 15 "
3256 "seconds. Continuing initialization\n");
3257 stat = 1;
3258 goto finished;
3259 }
3260
3261 if (vport->port_state != LPFC_VPORT_READY)
3262 goto finished;
3263 if (vport->num_disc_nodes || vport->fc_prli_sent)
3264 goto finished;
3265 if (vport->fc_map_cnt == 0 && time < msecs_to_jiffies(2 * 1000))
3266 goto finished;
3267 if ((phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) != 0)
3268 goto finished;
3269
3270 stat = 1;
3271
3272finished:
3273 spin_unlock_irq(shost->host_lock);
3274 return stat;
3275}
3276
3277
3278
3279
3280
3281
3282
3283
3284void lpfc_host_attrib_init(struct Scsi_Host *shost)
3285{
3286 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
3287 struct lpfc_hba *phba = vport->phba;
3288
3289
3290
3291
3292 fc_host_node_name(shost) = wwn_to_u64(vport->fc_nodename.u.wwn);
3293 fc_host_port_name(shost) = wwn_to_u64(vport->fc_portname.u.wwn);
3294 fc_host_supported_classes(shost) = FC_COS_CLASS3;
3295
3296 memset(fc_host_supported_fc4s(shost), 0,
3297 sizeof(fc_host_supported_fc4s(shost)));
3298 fc_host_supported_fc4s(shost)[2] = 1;
3299 fc_host_supported_fc4s(shost)[7] = 1;
3300
3301 lpfc_vport_symbolic_node_name(vport, fc_host_symbolic_name(shost),
3302 sizeof fc_host_symbolic_name(shost));
3303
3304 fc_host_supported_speeds(shost) = 0;
3305 if (phba->lmt & LMT_16Gb)
3306 fc_host_supported_speeds(shost) |= FC_PORTSPEED_16GBIT;
3307 if (phba->lmt & LMT_10Gb)
3308 fc_host_supported_speeds(shost) |= FC_PORTSPEED_10GBIT;
3309 if (phba->lmt & LMT_8Gb)
3310 fc_host_supported_speeds(shost) |= FC_PORTSPEED_8GBIT;
3311 if (phba->lmt & LMT_4Gb)
3312 fc_host_supported_speeds(shost) |= FC_PORTSPEED_4GBIT;
3313 if (phba->lmt & LMT_2Gb)
3314 fc_host_supported_speeds(shost) |= FC_PORTSPEED_2GBIT;
3315 if (phba->lmt & LMT_1Gb)
3316 fc_host_supported_speeds(shost) |= FC_PORTSPEED_1GBIT;
3317
3318 fc_host_maxframe_size(shost) =
3319 (((uint32_t) vport->fc_sparam.cmn.bbRcvSizeMsb & 0x0F) << 8) |
3320 (uint32_t) vport->fc_sparam.cmn.bbRcvSizeLsb;
3321
3322 fc_host_dev_loss_tmo(shost) = vport->cfg_devloss_tmo;
3323
3324
3325 memset(fc_host_active_fc4s(shost), 0,
3326 sizeof(fc_host_active_fc4s(shost)));
3327 fc_host_active_fc4s(shost)[2] = 1;
3328 fc_host_active_fc4s(shost)[7] = 1;
3329
3330 fc_host_max_npiv_vports(shost) = phba->max_vpi;
3331 spin_lock_irq(shost->host_lock);
3332 vport->load_flag &= ~FC_LOADING;
3333 spin_unlock_irq(shost->host_lock);
3334}
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344static void
3345lpfc_stop_port_s3(struct lpfc_hba *phba)
3346{
3347
3348 writel(0, phba->HCregaddr);
3349 readl(phba->HCregaddr);
3350
3351 writel(0xffffffff, phba->HAregaddr);
3352 readl(phba->HAregaddr);
3353
3354
3355 lpfc_stop_hba_timers(phba);
3356 phba->pport->work_port_events = 0;
3357}
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367static void
3368lpfc_stop_port_s4(struct lpfc_hba *phba)
3369{
3370
3371 lpfc_stop_hba_timers(phba);
3372 phba->pport->work_port_events = 0;
3373 phba->sli4_hba.intr_enable = 0;
3374}
3375
3376
3377
3378
3379
3380
3381
3382
3383void
3384lpfc_stop_port(struct lpfc_hba *phba)
3385{
3386 phba->lpfc_stop_port(phba);
3387}
3388
3389
3390
3391
3392
3393
3394
3395void
3396lpfc_fcf_redisc_wait_start_timer(struct lpfc_hba *phba)
3397{
3398 unsigned long fcf_redisc_wait_tmo =
3399 (jiffies + msecs_to_jiffies(LPFC_FCF_REDISCOVER_WAIT_TMO));
3400
3401 mod_timer(&phba->fcf.redisc_wait, fcf_redisc_wait_tmo);
3402 spin_lock_irq(&phba->hbalock);
3403
3404 phba->fcf.fcf_flag &= ~(FCF_AVAILABLE | FCF_SCAN_DONE);
3405
3406 phba->fcf.fcf_flag |= FCF_REDISC_PEND;
3407 spin_unlock_irq(&phba->hbalock);
3408}
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420void
3421lpfc_sli4_fcf_redisc_wait_tmo(unsigned long ptr)
3422{
3423 struct lpfc_hba *phba = (struct lpfc_hba *)ptr;
3424
3425
3426 spin_lock_irq(&phba->hbalock);
3427 if (!(phba->fcf.fcf_flag & FCF_REDISC_PEND)) {
3428 spin_unlock_irq(&phba->hbalock);
3429 return;
3430 }
3431
3432 phba->fcf.fcf_flag &= ~FCF_REDISC_PEND;
3433
3434 phba->fcf.fcf_flag |= FCF_REDISC_EVT;
3435 spin_unlock_irq(&phba->hbalock);
3436 lpfc_printf_log(phba, KERN_INFO, LOG_FIP,
3437 "2776 FCF rediscover quiescent timer expired\n");
3438
3439 lpfc_worker_wake_up(phba);
3440}
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453static uint16_t
3454lpfc_sli4_parse_latt_fault(struct lpfc_hba *phba,
3455 struct lpfc_acqe_link *acqe_link)
3456{
3457 uint16_t latt_fault;
3458
3459 switch (bf_get(lpfc_acqe_link_fault, acqe_link)) {
3460 case LPFC_ASYNC_LINK_FAULT_NONE:
3461 case LPFC_ASYNC_LINK_FAULT_LOCAL:
3462 case LPFC_ASYNC_LINK_FAULT_REMOTE:
3463 latt_fault = 0;
3464 break;
3465 default:
3466 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
3467 "0398 Invalid link fault code: x%x\n",
3468 bf_get(lpfc_acqe_link_fault, acqe_link));
3469 latt_fault = MBXERR_ERROR;
3470 break;
3471 }
3472 return latt_fault;
3473}
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485static uint8_t
3486lpfc_sli4_parse_latt_type(struct lpfc_hba *phba,
3487 struct lpfc_acqe_link *acqe_link)
3488{
3489 uint8_t att_type;
3490
3491 switch (bf_get(lpfc_acqe_link_status, acqe_link)) {
3492 case LPFC_ASYNC_LINK_STATUS_DOWN:
3493 case LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN:
3494 att_type = LPFC_ATT_LINK_DOWN;
3495 break;
3496 case LPFC_ASYNC_LINK_STATUS_UP:
3497
3498 att_type = LPFC_ATT_RESERVED;
3499 break;
3500 case LPFC_ASYNC_LINK_STATUS_LOGICAL_UP:
3501 att_type = LPFC_ATT_LINK_UP;
3502 break;
3503 default:
3504 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
3505 "0399 Invalid link attention type: x%x\n",
3506 bf_get(lpfc_acqe_link_status, acqe_link));
3507 att_type = LPFC_ATT_RESERVED;
3508 break;
3509 }
3510 return att_type;
3511}
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523static uint8_t
3524lpfc_sli4_parse_latt_link_speed(struct lpfc_hba *phba,
3525 struct lpfc_acqe_link *acqe_link)
3526{
3527 uint8_t link_speed;
3528
3529 switch (bf_get(lpfc_acqe_link_speed, acqe_link)) {
3530 case LPFC_ASYNC_LINK_SPEED_ZERO:
3531 case LPFC_ASYNC_LINK_SPEED_10MBPS:
3532 case LPFC_ASYNC_LINK_SPEED_100MBPS:
3533 link_speed = LPFC_LINK_SPEED_UNKNOWN;
3534 break;
3535 case LPFC_ASYNC_LINK_SPEED_1GBPS:
3536 link_speed = LPFC_LINK_SPEED_1GHZ;
3537 break;
3538 case LPFC_ASYNC_LINK_SPEED_10GBPS:
3539 link_speed = LPFC_LINK_SPEED_10GHZ;
3540 break;
3541 default:
3542 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
3543 "0483 Invalid link-attention link speed: x%x\n",
3544 bf_get(lpfc_acqe_link_speed, acqe_link));
3545 link_speed = LPFC_LINK_SPEED_UNKNOWN;
3546 break;
3547 }
3548 return link_speed;
3549}
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559uint32_t
3560lpfc_sli_port_speed_get(struct lpfc_hba *phba)
3561{
3562 uint32_t link_speed;
3563
3564 if (!lpfc_is_link_up(phba))
3565 return 0;
3566
3567 switch (phba->fc_linkspeed) {
3568 case LPFC_LINK_SPEED_1GHZ:
3569 link_speed = 1000;
3570 break;
3571 case LPFC_LINK_SPEED_2GHZ:
3572 link_speed = 2000;
3573 break;
3574 case LPFC_LINK_SPEED_4GHZ:
3575 link_speed = 4000;
3576 break;
3577 case LPFC_LINK_SPEED_8GHZ:
3578 link_speed = 8000;
3579 break;
3580 case LPFC_LINK_SPEED_10GHZ:
3581 link_speed = 10000;
3582 break;
3583 case LPFC_LINK_SPEED_16GHZ:
3584 link_speed = 16000;
3585 break;
3586 default:
3587 link_speed = 0;
3588 }
3589 return link_speed;
3590}
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603static uint32_t
3604lpfc_sli4_port_speed_parse(struct lpfc_hba *phba, uint32_t evt_code,
3605 uint8_t speed_code)
3606{
3607 uint32_t port_speed;
3608
3609 switch (evt_code) {
3610 case LPFC_TRAILER_CODE_LINK:
3611 switch (speed_code) {
3612 case LPFC_EVT_CODE_LINK_NO_LINK:
3613 port_speed = 0;
3614 break;
3615 case LPFC_EVT_CODE_LINK_10_MBIT:
3616 port_speed = 10;
3617 break;
3618 case LPFC_EVT_CODE_LINK_100_MBIT:
3619 port_speed = 100;
3620 break;
3621 case LPFC_EVT_CODE_LINK_1_GBIT:
3622 port_speed = 1000;
3623 break;
3624 case LPFC_EVT_CODE_LINK_10_GBIT:
3625 port_speed = 10000;
3626 break;
3627 default:
3628 port_speed = 0;
3629 }
3630 break;
3631 case LPFC_TRAILER_CODE_FC:
3632 switch (speed_code) {
3633 case LPFC_EVT_CODE_FC_NO_LINK:
3634 port_speed = 0;
3635 break;
3636 case LPFC_EVT_CODE_FC_1_GBAUD:
3637 port_speed = 1000;
3638 break;
3639 case LPFC_EVT_CODE_FC_2_GBAUD:
3640 port_speed = 2000;
3641 break;
3642 case LPFC_EVT_CODE_FC_4_GBAUD:
3643 port_speed = 4000;
3644 break;
3645 case LPFC_EVT_CODE_FC_8_GBAUD:
3646 port_speed = 8000;
3647 break;
3648 case LPFC_EVT_CODE_FC_10_GBAUD:
3649 port_speed = 10000;
3650 break;
3651 case LPFC_EVT_CODE_FC_16_GBAUD:
3652 port_speed = 16000;
3653 break;
3654 default:
3655 port_speed = 0;
3656 }
3657 break;
3658 default:
3659 port_speed = 0;
3660 }
3661 return port_speed;
3662}
3663
3664
3665
3666
3667
3668
3669
3670
3671static void
3672lpfc_sli4_async_link_evt(struct lpfc_hba *phba,
3673 struct lpfc_acqe_link *acqe_link)
3674{
3675 struct lpfc_dmabuf *mp;
3676 LPFC_MBOXQ_t *pmb;
3677 MAILBOX_t *mb;
3678 struct lpfc_mbx_read_top *la;
3679 uint8_t att_type;
3680 int rc;
3681
3682 att_type = lpfc_sli4_parse_latt_type(phba, acqe_link);
3683 if (att_type != LPFC_ATT_LINK_DOWN && att_type != LPFC_ATT_LINK_UP)
3684 return;
3685 phba->fcoe_eventtag = acqe_link->event_tag;
3686 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
3687 if (!pmb) {
3688 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3689 "0395 The mboxq allocation failed\n");
3690 return;
3691 }
3692 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
3693 if (!mp) {
3694 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3695 "0396 The lpfc_dmabuf allocation failed\n");
3696 goto out_free_pmb;
3697 }
3698 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
3699 if (!mp->virt) {
3700 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3701 "0397 The mbuf allocation failed\n");
3702 goto out_free_dmabuf;
3703 }
3704
3705
3706 lpfc_els_flush_all_cmd(phba);
3707
3708
3709 phba->sli.ring[LPFC_ELS_RING].flag |= LPFC_STOP_IOCB_EVENT;
3710
3711
3712 phba->sli.slistat.link_event++;
3713
3714
3715 lpfc_read_topology(phba, pmb, mp);
3716 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
3717 pmb->vport = phba->pport;
3718
3719
3720 phba->sli4_hba.link_state.speed =
3721 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_LINK,
3722 bf_get(lpfc_acqe_link_speed, acqe_link));
3723 phba->sli4_hba.link_state.duplex =
3724 bf_get(lpfc_acqe_link_duplex, acqe_link);
3725 phba->sli4_hba.link_state.status =
3726 bf_get(lpfc_acqe_link_status, acqe_link);
3727 phba->sli4_hba.link_state.type =
3728 bf_get(lpfc_acqe_link_type, acqe_link);
3729 phba->sli4_hba.link_state.number =
3730 bf_get(lpfc_acqe_link_number, acqe_link);
3731 phba->sli4_hba.link_state.fault =
3732 bf_get(lpfc_acqe_link_fault, acqe_link);
3733 phba->sli4_hba.link_state.logical_speed =
3734 bf_get(lpfc_acqe_logical_link_speed, acqe_link) * 10;
3735
3736 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3737 "2900 Async FC/FCoE Link event - Speed:%dGBit "
3738 "duplex:x%x LA Type:x%x Port Type:%d Port Number:%d "
3739 "Logical speed:%dMbps Fault:%d\n",
3740 phba->sli4_hba.link_state.speed,
3741 phba->sli4_hba.link_state.topology,
3742 phba->sli4_hba.link_state.status,
3743 phba->sli4_hba.link_state.type,
3744 phba->sli4_hba.link_state.number,
3745 phba->sli4_hba.link_state.logical_speed,
3746 phba->sli4_hba.link_state.fault);
3747
3748
3749
3750
3751 if (!(phba->hba_flag & HBA_FCOE_MODE)) {
3752 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
3753 if (rc == MBX_NOT_FINISHED)
3754 goto out_free_dmabuf;
3755 return;
3756 }
3757
3758
3759
3760
3761
3762
3763 mb = &pmb->u.mb;
3764 mb->mbxStatus = lpfc_sli4_parse_latt_fault(phba, acqe_link);
3765
3766
3767 la = (struct lpfc_mbx_read_top *) &pmb->u.mb.un.varReadTop;
3768 la->eventTag = acqe_link->event_tag;
3769 bf_set(lpfc_mbx_read_top_att_type, la, att_type);
3770 bf_set(lpfc_mbx_read_top_link_spd, la,
3771 lpfc_sli4_parse_latt_link_speed(phba, acqe_link));
3772
3773
3774 bf_set(lpfc_mbx_read_top_topology, la, LPFC_TOPOLOGY_PT_PT);
3775 bf_set(lpfc_mbx_read_top_alpa_granted, la, 0);
3776 bf_set(lpfc_mbx_read_top_il, la, 0);
3777 bf_set(lpfc_mbx_read_top_pb, la, 0);
3778 bf_set(lpfc_mbx_read_top_fa, la, 0);
3779 bf_set(lpfc_mbx_read_top_mm, la, 0);
3780
3781
3782 lpfc_mbx_cmpl_read_topology(phba, pmb);
3783
3784 return;
3785
3786out_free_dmabuf:
3787 kfree(mp);
3788out_free_pmb:
3789 mempool_free(pmb, phba->mbox_mem_pool);
3790}
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801static void
3802lpfc_sli4_async_fc_evt(struct lpfc_hba *phba, struct lpfc_acqe_fc_la *acqe_fc)
3803{
3804 struct lpfc_dmabuf *mp;
3805 LPFC_MBOXQ_t *pmb;
3806 int rc;
3807
3808 if (bf_get(lpfc_trailer_type, acqe_fc) !=
3809 LPFC_FC_LA_EVENT_TYPE_FC_LINK) {
3810 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3811 "2895 Non FC link Event detected.(%d)\n",
3812 bf_get(lpfc_trailer_type, acqe_fc));
3813 return;
3814 }
3815
3816 phba->sli4_hba.link_state.speed =
3817 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_FC,
3818 bf_get(lpfc_acqe_fc_la_speed, acqe_fc));
3819 phba->sli4_hba.link_state.duplex = LPFC_ASYNC_LINK_DUPLEX_FULL;
3820 phba->sli4_hba.link_state.topology =
3821 bf_get(lpfc_acqe_fc_la_topology, acqe_fc);
3822 phba->sli4_hba.link_state.status =
3823 bf_get(lpfc_acqe_fc_la_att_type, acqe_fc);
3824 phba->sli4_hba.link_state.type =
3825 bf_get(lpfc_acqe_fc_la_port_type, acqe_fc);
3826 phba->sli4_hba.link_state.number =
3827 bf_get(lpfc_acqe_fc_la_port_number, acqe_fc);
3828 phba->sli4_hba.link_state.fault =
3829 bf_get(lpfc_acqe_link_fault, acqe_fc);
3830 phba->sli4_hba.link_state.logical_speed =
3831 bf_get(lpfc_acqe_fc_la_llink_spd, acqe_fc) * 10;
3832 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3833 "2896 Async FC event - Speed:%dGBaud Topology:x%x "
3834 "LA Type:x%x Port Type:%d Port Number:%d Logical speed:"
3835 "%dMbps Fault:%d\n",
3836 phba->sli4_hba.link_state.speed,
3837 phba->sli4_hba.link_state.topology,
3838 phba->sli4_hba.link_state.status,
3839 phba->sli4_hba.link_state.type,
3840 phba->sli4_hba.link_state.number,
3841 phba->sli4_hba.link_state.logical_speed,
3842 phba->sli4_hba.link_state.fault);
3843 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
3844 if (!pmb) {
3845 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3846 "2897 The mboxq allocation failed\n");
3847 return;
3848 }
3849 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
3850 if (!mp) {
3851 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3852 "2898 The lpfc_dmabuf allocation failed\n");
3853 goto out_free_pmb;
3854 }
3855 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
3856 if (!mp->virt) {
3857 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3858 "2899 The mbuf allocation failed\n");
3859 goto out_free_dmabuf;
3860 }
3861
3862
3863 lpfc_els_flush_all_cmd(phba);
3864
3865
3866 phba->sli.ring[LPFC_ELS_RING].flag |= LPFC_STOP_IOCB_EVENT;
3867
3868
3869 phba->sli.slistat.link_event++;
3870
3871
3872 lpfc_read_topology(phba, pmb, mp);
3873 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
3874 pmb->vport = phba->pport;
3875
3876 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
3877 if (rc == MBX_NOT_FINISHED)
3878 goto out_free_dmabuf;
3879 return;
3880
3881out_free_dmabuf:
3882 kfree(mp);
3883out_free_pmb:
3884 mempool_free(pmb, phba->mbox_mem_pool);
3885}
3886
3887
3888
3889
3890
3891
3892
3893
3894static void
3895lpfc_sli4_async_sli_evt(struct lpfc_hba *phba, struct lpfc_acqe_sli *acqe_sli)
3896{
3897 char port_name;
3898 char message[128];
3899 uint8_t status;
3900 struct lpfc_acqe_misconfigured_event *misconfigured;
3901
3902
3903 if ((bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) !=
3904 LPFC_SLI_INTF_IF_TYPE_2) ||
3905 (bf_get(lpfc_trailer_type, acqe_sli) !=
3906 LPFC_SLI_EVENT_TYPE_MISCONFIGURED)) {
3907 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3908 "2901 Async SLI event - Event Data1:x%08x Event Data2:"
3909 "x%08x SLI Event Type:%d\n",
3910 acqe_sli->event_data1, acqe_sli->event_data2,
3911 bf_get(lpfc_trailer_type, acqe_sli));
3912 return;
3913 }
3914
3915 port_name = phba->Port[0];
3916 if (port_name == 0x00)
3917 port_name = '?';
3918
3919 misconfigured = (struct lpfc_acqe_misconfigured_event *)
3920 &acqe_sli->event_data1;
3921
3922
3923 switch (phba->sli4_hba.lnk_info.lnk_no) {
3924 case LPFC_LINK_NUMBER_0:
3925 status = bf_get(lpfc_sli_misconfigured_port0,
3926 &misconfigured->theEvent);
3927 break;
3928 case LPFC_LINK_NUMBER_1:
3929 status = bf_get(lpfc_sli_misconfigured_port1,
3930 &misconfigured->theEvent);
3931 break;
3932 case LPFC_LINK_NUMBER_2:
3933 status = bf_get(lpfc_sli_misconfigured_port2,
3934 &misconfigured->theEvent);
3935 break;
3936 case LPFC_LINK_NUMBER_3:
3937 status = bf_get(lpfc_sli_misconfigured_port3,
3938 &misconfigured->theEvent);
3939 break;
3940 default:
3941 status = ~LPFC_SLI_EVENT_STATUS_VALID;
3942 break;
3943 }
3944
3945 switch (status) {
3946 case LPFC_SLI_EVENT_STATUS_VALID:
3947 return;
3948 case LPFC_SLI_EVENT_STATUS_NOT_PRESENT:
3949 sprintf(message, "Optics faulted/incorrectly installed/not " \
3950 "installed - Reseat optics, if issue not "
3951 "resolved, replace.");
3952 break;
3953 case LPFC_SLI_EVENT_STATUS_WRONG_TYPE:
3954 sprintf(message,
3955 "Optics of two types installed - Remove one optic or " \
3956 "install matching pair of optics.");
3957 break;
3958 case LPFC_SLI_EVENT_STATUS_UNSUPPORTED:
3959 sprintf(message, "Incompatible optics - Replace with " \
3960 "compatible optics for card to function.");
3961 break;
3962 default:
3963
3964 sprintf(message, "Unknown event status x%02x", status);
3965 break;
3966 }
3967
3968 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3969 "3176 Misconfigured Physical Port - "
3970 "Port Name %c %s\n", port_name, message);
3971}
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982
3983static struct lpfc_nodelist *
3984lpfc_sli4_perform_vport_cvl(struct lpfc_vport *vport)
3985{
3986 struct lpfc_nodelist *ndlp;
3987 struct Scsi_Host *shost;
3988 struct lpfc_hba *phba;
3989
3990 if (!vport)
3991 return NULL;
3992 phba = vport->phba;
3993 if (!phba)
3994 return NULL;
3995 ndlp = lpfc_findnode_did(vport, Fabric_DID);
3996 if (!ndlp) {
3997
3998 ndlp = mempool_alloc(phba->nlp_mem_pool, GFP_KERNEL);
3999 if (!ndlp)
4000 return 0;
4001 lpfc_nlp_init(vport, ndlp, Fabric_DID);
4002
4003 ndlp->nlp_type |= NLP_FABRIC;
4004
4005 lpfc_enqueue_node(vport, ndlp);
4006 } else if (!NLP_CHK_NODE_ACT(ndlp)) {
4007
4008 ndlp = lpfc_enable_node(vport, ndlp, NLP_STE_UNUSED_NODE);
4009 if (!ndlp)
4010 return 0;
4011 }
4012 if ((phba->pport->port_state < LPFC_FLOGI) &&
4013 (phba->pport->port_state != LPFC_VPORT_FAILED))
4014 return NULL;
4015
4016 if ((vport != phba->pport) && (vport->port_state < LPFC_FDISC)
4017 && (vport->port_state != LPFC_VPORT_FAILED))
4018 return NULL;
4019 shost = lpfc_shost_from_vport(vport);
4020 if (!shost)
4021 return NULL;
4022 lpfc_linkdown_port(vport);
4023 lpfc_cleanup_pending_mbox(vport);
4024 spin_lock_irq(shost->host_lock);
4025 vport->fc_flag |= FC_VPORT_CVL_RCVD;
4026 spin_unlock_irq(shost->host_lock);
4027
4028 return ndlp;
4029}
4030
4031
4032
4033
4034
4035
4036
4037
4038static void
4039lpfc_sli4_perform_all_vport_cvl(struct lpfc_hba *phba)
4040{
4041 struct lpfc_vport **vports;
4042 int i;
4043
4044 vports = lpfc_create_vport_work_array(phba);
4045 if (vports)
4046 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++)
4047 lpfc_sli4_perform_vport_cvl(vports[i]);
4048 lpfc_destroy_vport_work_array(phba, vports);
4049}
4050
4051
4052
4053
4054
4055
4056
4057
4058static void
4059lpfc_sli4_perform_inuse_fcf_recovery(struct lpfc_hba *phba,
4060 struct lpfc_acqe_fip *acqe_fip)
4061{
4062 int rc;
4063
4064 spin_lock_irq(&phba->hbalock);
4065
4066 phba->fcf.fcf_flag |= FCF_DEAD_DISC;
4067 spin_unlock_irq(&phba->hbalock);
4068
4069 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
4070 "2771 Start FCF fast failover process due to in-use "
4071 "FCF DEAD/MODIFIED event: evt_tag:x%x, index:x%x\n",
4072 acqe_fip->event_tag, acqe_fip->index);
4073 rc = lpfc_sli4_redisc_fcf_table(phba);
4074 if (rc) {
4075 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
4076 "2772 Issue FCF rediscover mabilbox command "
4077 "failed, fail through to FCF dead event\n");
4078 spin_lock_irq(&phba->hbalock);
4079 phba->fcf.fcf_flag &= ~FCF_DEAD_DISC;
4080 spin_unlock_irq(&phba->hbalock);
4081
4082
4083
4084
4085 lpfc_sli4_fcf_dead_failthrough(phba);
4086 } else {
4087
4088 lpfc_sli4_clear_fcf_rr_bmask(phba);
4089
4090
4091
4092
4093 lpfc_sli4_perform_all_vport_cvl(phba);
4094 }
4095}
4096
4097
4098
4099
4100
4101
4102
4103
4104static void
4105lpfc_sli4_async_fip_evt(struct lpfc_hba *phba,
4106 struct lpfc_acqe_fip *acqe_fip)
4107{
4108 uint8_t event_type = bf_get(lpfc_trailer_type, acqe_fip);
4109 int rc;
4110 struct lpfc_vport *vport;
4111 struct lpfc_nodelist *ndlp;
4112 struct Scsi_Host *shost;
4113 int active_vlink_present;
4114 struct lpfc_vport **vports;
4115 int i;
4116
4117 phba->fc_eventTag = acqe_fip->event_tag;
4118 phba->fcoe_eventtag = acqe_fip->event_tag;
4119 switch (event_type) {
4120 case LPFC_FIP_EVENT_TYPE_NEW_FCF:
4121 case LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD:
4122 if (event_type == LPFC_FIP_EVENT_TYPE_NEW_FCF)
4123 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
4124 LOG_DISCOVERY,
4125 "2546 New FCF event, evt_tag:x%x, "
4126 "index:x%x\n",
4127 acqe_fip->event_tag,
4128 acqe_fip->index);
4129 else
4130 lpfc_printf_log(phba, KERN_WARNING, LOG_FIP |
4131 LOG_DISCOVERY,
4132 "2788 FCF param modified event, "
4133 "evt_tag:x%x, index:x%x\n",
4134 acqe_fip->event_tag,
4135 acqe_fip->index);
4136 if (phba->fcf.fcf_flag & FCF_DISCOVERY) {
4137
4138
4139
4140
4141
4142 lpfc_printf_log(phba, KERN_INFO, LOG_FIP |
4143 LOG_DISCOVERY,
4144 "2779 Read FCF (x%x) for updating "
4145 "roundrobin FCF failover bmask\n",
4146 acqe_fip->index);
4147 rc = lpfc_sli4_read_fcf_rec(phba, acqe_fip->index);
4148 }
4149
4150
4151 spin_lock_irq(&phba->hbalock);
4152 if (phba->hba_flag & FCF_TS_INPROG) {
4153 spin_unlock_irq(&phba->hbalock);
4154 break;
4155 }
4156
4157 if (phba->fcf.fcf_flag & FCF_REDISC_EVT) {
4158 spin_unlock_irq(&phba->hbalock);
4159 break;
4160 }
4161
4162
4163
4164
4165
4166 if (phba->pport->port_state > LPFC_FLOGI) {
4167 spin_unlock_irq(&phba->hbalock);
4168 if (phba->fcf.current_rec.fcf_indx ==
4169 acqe_fip->index) {
4170 lpfc_printf_log(phba, KERN_ERR, LOG_FIP,
4171 "3300 In-use FCF (%d) "
4172 "modified, perform FCF "
4173 "rediscovery\n",
4174 acqe_fip->index);
4175 lpfc_sli4_perform_inuse_fcf_recovery(phba,
4176 acqe_fip);
4177 }
4178 break;
4179 }
4180 spin_unlock_irq(&phba->hbalock);
4181
4182
4183 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
4184 "2770 Start FCF table scan per async FCF "
4185 "event, evt_tag:x%x, index:x%x\n",
4186 acqe_fip->event_tag, acqe_fip->index);
4187 rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba,
4188 LPFC_FCOE_FCF_GET_FIRST);
4189 if (rc)
4190 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
4191 "2547 Issue FCF scan read FCF mailbox "
4192 "command failed (x%x)\n", rc);
4193 break;
4194
4195 case LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL:
4196 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4197 "2548 FCF Table full count 0x%x tag 0x%x\n",
4198 bf_get(lpfc_acqe_fip_fcf_count, acqe_fip),
4199 acqe_fip->event_tag);
4200 break;
4201
4202 case LPFC_FIP_EVENT_TYPE_FCF_DEAD:
4203 phba->fcoe_cvl_eventtag = acqe_fip->event_tag;
4204 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
4205 "2549 FCF (x%x) disconnected from network, "
4206 "tag:x%x\n", acqe_fip->index, acqe_fip->event_tag);
4207
4208
4209
4210
4211 spin_lock_irq(&phba->hbalock);
4212 if (phba->fcf.fcf_flag & FCF_DISCOVERY) {
4213 spin_unlock_irq(&phba->hbalock);
4214
4215 lpfc_sli4_fcf_rr_index_clear(phba, acqe_fip->index);
4216 break;
4217 }
4218 spin_unlock_irq(&phba->hbalock);
4219
4220
4221 if (phba->fcf.current_rec.fcf_indx != acqe_fip->index)
4222 break;
4223
4224
4225
4226
4227
4228
4229
4230 lpfc_sli4_perform_inuse_fcf_recovery(phba, acqe_fip);
4231 break;
4232 case LPFC_FIP_EVENT_TYPE_CVL:
4233 phba->fcoe_cvl_eventtag = acqe_fip->event_tag;
4234 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
4235 "2718 Clear Virtual Link Received for VPI 0x%x"
4236 " tag 0x%x\n", acqe_fip->index, acqe_fip->event_tag);
4237
4238 vport = lpfc_find_vport_by_vpid(phba,
4239 acqe_fip->index);
4240 ndlp = lpfc_sli4_perform_vport_cvl(vport);
4241 if (!ndlp)
4242 break;
4243 active_vlink_present = 0;
4244
4245 vports = lpfc_create_vport_work_array(phba);
4246 if (vports) {
4247 for (i = 0; i <= phba->max_vports && vports[i] != NULL;
4248 i++) {
4249 if ((!(vports[i]->fc_flag &
4250 FC_VPORT_CVL_RCVD)) &&
4251 (vports[i]->port_state > LPFC_FDISC)) {
4252 active_vlink_present = 1;
4253 break;
4254 }
4255 }
4256 lpfc_destroy_vport_work_array(phba, vports);
4257 }
4258
4259 if (active_vlink_present) {
4260
4261
4262
4263
4264 mod_timer(&ndlp->nlp_delayfunc,
4265 jiffies + msecs_to_jiffies(1000));
4266 shost = lpfc_shost_from_vport(vport);
4267 spin_lock_irq(shost->host_lock);
4268 ndlp->nlp_flag |= NLP_DELAY_TMO;
4269 spin_unlock_irq(shost->host_lock);
4270 ndlp->nlp_last_elscmd = ELS_CMD_FDISC;
4271 vport->port_state = LPFC_FDISC;
4272 } else {
4273
4274
4275
4276
4277
4278
4279
4280 spin_lock_irq(&phba->hbalock);
4281 if (phba->fcf.fcf_flag & FCF_DISCOVERY) {
4282 spin_unlock_irq(&phba->hbalock);
4283 break;
4284 }
4285
4286 phba->fcf.fcf_flag |= FCF_ACVL_DISC;
4287 spin_unlock_irq(&phba->hbalock);
4288 lpfc_printf_log(phba, KERN_INFO, LOG_FIP |
4289 LOG_DISCOVERY,
4290 "2773 Start FCF failover per CVL, "
4291 "evt_tag:x%x\n", acqe_fip->event_tag);
4292 rc = lpfc_sli4_redisc_fcf_table(phba);
4293 if (rc) {
4294 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
4295 LOG_DISCOVERY,
4296 "2774 Issue FCF rediscover "
4297 "mabilbox command failed, "
4298 "through to CVL event\n");
4299 spin_lock_irq(&phba->hbalock);
4300 phba->fcf.fcf_flag &= ~FCF_ACVL_DISC;
4301 spin_unlock_irq(&phba->hbalock);
4302
4303
4304
4305
4306 lpfc_retry_pport_discovery(phba);
4307 } else
4308
4309
4310
4311
4312 lpfc_sli4_clear_fcf_rr_bmask(phba);
4313 }
4314 break;
4315 default:
4316 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4317 "0288 Unknown FCoE event type 0x%x event tag "
4318 "0x%x\n", event_type, acqe_fip->event_tag);
4319 break;
4320 }
4321}
4322
4323
4324
4325
4326
4327
4328
4329
4330static void
4331lpfc_sli4_async_dcbx_evt(struct lpfc_hba *phba,
4332 struct lpfc_acqe_dcbx *acqe_dcbx)
4333{
4334 phba->fc_eventTag = acqe_dcbx->event_tag;
4335 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4336 "0290 The SLI4 DCBX asynchronous event is not "
4337 "handled yet\n");
4338}
4339
4340
4341
4342
4343
4344
4345
4346
4347
4348
4349static void
4350lpfc_sli4_async_grp5_evt(struct lpfc_hba *phba,
4351 struct lpfc_acqe_grp5 *acqe_grp5)
4352{
4353 uint16_t prev_ll_spd;
4354
4355 phba->fc_eventTag = acqe_grp5->event_tag;
4356 phba->fcoe_eventtag = acqe_grp5->event_tag;
4357 prev_ll_spd = phba->sli4_hba.link_state.logical_speed;
4358 phba->sli4_hba.link_state.logical_speed =
4359 (bf_get(lpfc_acqe_grp5_llink_spd, acqe_grp5)) * 10;
4360 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
4361 "2789 GRP5 Async Event: Updating logical link speed "
4362 "from %dMbps to %dMbps\n", prev_ll_spd,
4363 phba->sli4_hba.link_state.logical_speed);
4364}
4365
4366
4367
4368
4369
4370
4371
4372
4373void lpfc_sli4_async_event_proc(struct lpfc_hba *phba)
4374{
4375 struct lpfc_cq_event *cq_event;
4376
4377
4378 spin_lock_irq(&phba->hbalock);
4379 phba->hba_flag &= ~ASYNC_EVENT;
4380 spin_unlock_irq(&phba->hbalock);
4381
4382 while (!list_empty(&phba->sli4_hba.sp_asynce_work_queue)) {
4383
4384 spin_lock_irq(&phba->hbalock);
4385 list_remove_head(&phba->sli4_hba.sp_asynce_work_queue,
4386 cq_event, struct lpfc_cq_event, list);
4387 spin_unlock_irq(&phba->hbalock);
4388
4389 switch (bf_get(lpfc_trailer_code, &cq_event->cqe.mcqe_cmpl)) {
4390 case LPFC_TRAILER_CODE_LINK:
4391 lpfc_sli4_async_link_evt(phba,
4392 &cq_event->cqe.acqe_link);
4393 break;
4394 case LPFC_TRAILER_CODE_FCOE:
4395 lpfc_sli4_async_fip_evt(phba, &cq_event->cqe.acqe_fip);
4396 break;
4397 case LPFC_TRAILER_CODE_DCBX:
4398 lpfc_sli4_async_dcbx_evt(phba,
4399 &cq_event->cqe.acqe_dcbx);
4400 break;
4401 case LPFC_TRAILER_CODE_GRP5:
4402 lpfc_sli4_async_grp5_evt(phba,
4403 &cq_event->cqe.acqe_grp5);
4404 break;
4405 case LPFC_TRAILER_CODE_FC:
4406 lpfc_sli4_async_fc_evt(phba, &cq_event->cqe.acqe_fc);
4407 break;
4408 case LPFC_TRAILER_CODE_SLI:
4409 lpfc_sli4_async_sli_evt(phba, &cq_event->cqe.acqe_sli);
4410 break;
4411 default:
4412 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4413 "1804 Invalid asynchrous event code: "
4414 "x%x\n", bf_get(lpfc_trailer_code,
4415 &cq_event->cqe.mcqe_cmpl));
4416 break;
4417 }
4418
4419 lpfc_sli4_cq_event_release(phba, cq_event);
4420 }
4421}
4422
4423
4424
4425
4426
4427
4428
4429
4430void lpfc_sli4_fcf_redisc_event_proc(struct lpfc_hba *phba)
4431{
4432 int rc;
4433
4434 spin_lock_irq(&phba->hbalock);
4435
4436 phba->fcf.fcf_flag &= ~FCF_REDISC_EVT;
4437
4438 phba->fcf.failover_rec.flag = 0;
4439
4440 phba->fcf.fcf_flag |= FCF_REDISC_FOV;
4441 spin_unlock_irq(&phba->hbalock);
4442
4443
4444 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
4445 "2777 Start post-quiescent FCF table scan\n");
4446 rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba, LPFC_FCOE_FCF_GET_FIRST);
4447 if (rc)
4448 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
4449 "2747 Issue FCF scan read FCF mailbox "
4450 "command failed 0x%x\n", rc);
4451}
4452
4453
4454
4455
4456
4457
4458
4459
4460
4461
4462
4463int
4464lpfc_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)
4465{
4466 int rc;
4467
4468
4469 phba->pci_dev_grp = dev_grp;
4470
4471
4472 if (dev_grp == LPFC_PCI_DEV_OC)
4473 phba->sli_rev = LPFC_SLI_REV4;
4474
4475
4476 rc = lpfc_init_api_table_setup(phba, dev_grp);
4477 if (rc)
4478 return -ENODEV;
4479
4480 rc = lpfc_scsi_api_table_setup(phba, dev_grp);
4481 if (rc)
4482 return -ENODEV;
4483
4484 rc = lpfc_sli_api_table_setup(phba, dev_grp);
4485 if (rc)
4486 return -ENODEV;
4487
4488 rc = lpfc_mbox_api_table_setup(phba, dev_grp);
4489 if (rc)
4490 return -ENODEV;
4491
4492 return 0;
4493}
4494
4495
4496
4497
4498
4499
4500
4501
4502
4503static void lpfc_log_intr_mode(struct lpfc_hba *phba, uint32_t intr_mode)
4504{
4505 switch (intr_mode) {
4506 case 0:
4507 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
4508 "0470 Enable INTx interrupt mode.\n");
4509 break;
4510 case 1:
4511 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
4512 "0481 Enabled MSI interrupt mode.\n");
4513 break;
4514 case 2:
4515 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
4516 "0480 Enabled MSI-X interrupt mode.\n");
4517 break;
4518 default:
4519 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
4520 "0482 Illegal interrupt mode.\n");
4521 break;
4522 }
4523 return;
4524}
4525
4526
4527
4528
4529
4530
4531
4532
4533
4534
4535
4536
4537static int
4538lpfc_enable_pci_dev(struct lpfc_hba *phba)
4539{
4540 struct pci_dev *pdev;
4541 int bars = 0;
4542
4543
4544 if (!phba->pcidev)
4545 goto out_error;
4546 else
4547 pdev = phba->pcidev;
4548
4549 bars = pci_select_bars(pdev, IORESOURCE_MEM);
4550
4551 if (pci_enable_device_mem(pdev))
4552 goto out_error;
4553
4554 if (pci_request_selected_regions(pdev, bars, LPFC_DRIVER_NAME))
4555 goto out_disable_device;
4556
4557 pci_set_master(pdev);
4558 pci_try_set_mwi(pdev);
4559 pci_save_state(pdev);
4560
4561
4562 if (pci_find_capability(pdev, PCI_CAP_ID_EXP))
4563 pdev->needs_freset = 1;
4564
4565 return 0;
4566
4567out_disable_device:
4568 pci_disable_device(pdev);
4569out_error:
4570 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
4571 "1401 Failed to enable pci device, bars:x%x\n", bars);
4572 return -ENODEV;
4573}
4574
4575
4576
4577
4578
4579
4580
4581
4582static void
4583lpfc_disable_pci_dev(struct lpfc_hba *phba)
4584{
4585 struct pci_dev *pdev;
4586 int bars;
4587
4588
4589 if (!phba->pcidev)
4590 return;
4591 else
4592 pdev = phba->pcidev;
4593
4594 bars = pci_select_bars(pdev, IORESOURCE_MEM);
4595
4596 pci_release_selected_regions(pdev, bars);
4597 pci_disable_device(pdev);
4598
4599 pci_set_drvdata(pdev, NULL);
4600
4601 return;
4602}
4603
4604
4605
4606
4607
4608
4609
4610
4611
4612
4613void
4614lpfc_reset_hba(struct lpfc_hba *phba)
4615{
4616
4617 if (!phba->cfg_enable_hba_reset) {
4618 phba->link_state = LPFC_HBA_ERROR;
4619 return;
4620 }
4621 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
4622 lpfc_offline(phba);
4623 lpfc_sli_brdrestart(phba);
4624 lpfc_online(phba);
4625 lpfc_unblock_mgmt_io(phba);
4626}
4627
4628
4629
4630
4631
4632
4633
4634
4635
4636
4637
4638uint16_t
4639lpfc_sli_sriov_nr_virtfn_get(struct lpfc_hba *phba)
4640{
4641 struct pci_dev *pdev = phba->pcidev;
4642 uint16_t nr_virtfn;
4643 int pos;
4644
4645 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
4646 if (pos == 0)
4647 return 0;
4648
4649 pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF, &nr_virtfn);
4650 return nr_virtfn;
4651}
4652
4653
4654
4655
4656
4657
4658
4659
4660
4661
4662
4663
4664int
4665lpfc_sli_probe_sriov_nr_virtfn(struct lpfc_hba *phba, int nr_vfn)
4666{
4667 struct pci_dev *pdev = phba->pcidev;
4668 uint16_t max_nr_vfn;
4669 int rc;
4670
4671 max_nr_vfn = lpfc_sli_sriov_nr_virtfn_get(phba);
4672 if (nr_vfn > max_nr_vfn) {
4673 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
4674 "3057 Requested vfs (%d) greater than "
4675 "supported vfs (%d)", nr_vfn, max_nr_vfn);
4676 return -EINVAL;
4677 }
4678
4679 rc = pci_enable_sriov(pdev, nr_vfn);
4680 if (rc) {
4681 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
4682 "2806 Failed to enable sriov on this device "
4683 "with vfn number nr_vf:%d, rc:%d\n",
4684 nr_vfn, rc);
4685 } else
4686 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
4687 "2807 Successful enable sriov on this device "
4688 "with vfn number nr_vf:%d\n", nr_vfn);
4689 return rc;
4690}
4691
4692
4693
4694
4695
4696
4697
4698
4699
4700
4701
4702
4703static int
4704lpfc_sli_driver_resource_setup(struct lpfc_hba *phba)
4705{
4706 struct lpfc_sli *psli;
4707 int rc;
4708
4709
4710
4711
4712
4713
4714 init_timer(&phba->hb_tmofunc);
4715 phba->hb_tmofunc.function = lpfc_hb_timeout;
4716 phba->hb_tmofunc.data = (unsigned long)phba;
4717
4718 psli = &phba->sli;
4719
4720 init_timer(&psli->mbox_tmo);
4721 psli->mbox_tmo.function = lpfc_mbox_timeout;
4722 psli->mbox_tmo.data = (unsigned long) phba;
4723
4724 init_timer(&phba->fcp_poll_timer);
4725 phba->fcp_poll_timer.function = lpfc_poll_timeout;
4726 phba->fcp_poll_timer.data = (unsigned long) phba;
4727
4728 init_timer(&phba->fabric_block_timer);
4729 phba->fabric_block_timer.function = lpfc_fabric_block_timeout;
4730 phba->fabric_block_timer.data = (unsigned long) phba;
4731
4732 init_timer(&phba->eratt_poll);
4733 phba->eratt_poll.function = lpfc_poll_eratt;
4734 phba->eratt_poll.data = (unsigned long) phba;
4735
4736
4737 phba->work_ha_mask = (HA_ERATT | HA_MBATT | HA_LATT);
4738 phba->work_ha_mask |= (HA_RXMASK << (LPFC_ELS_RING * 4));
4739
4740
4741 lpfc_get_cfgparam(phba);
4742 if (phba->pcidev->device == PCI_DEVICE_ID_HORNET) {
4743 phba->menlo_flag |= HBA_MENLO_SUPPORT;
4744
4745 if (phba->cfg_sg_seg_cnt < LPFC_DEFAULT_MENLO_SG_SEG_CNT)
4746 phba->cfg_sg_seg_cnt = LPFC_DEFAULT_MENLO_SG_SEG_CNT;
4747 }
4748
4749 if (!phba->sli.ring)
4750 phba->sli.ring = (struct lpfc_sli_ring *)
4751 kzalloc(LPFC_SLI3_MAX_RING *
4752 sizeof(struct lpfc_sli_ring), GFP_KERNEL);
4753 if (!phba->sli.ring)
4754 return -ENOMEM;
4755
4756
4757
4758
4759
4760
4761
4762 lpfc_vport_template.sg_tablesize = phba->cfg_sg_seg_cnt;
4763 lpfc_template.sg_tablesize = phba->cfg_sg_seg_cnt;
4764
4765
4766 if (phba->cfg_enable_bg) {
4767
4768
4769
4770
4771
4772
4773
4774
4775
4776 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
4777 sizeof(struct fcp_rsp) +
4778 (LPFC_MAX_SG_SEG_CNT * sizeof(struct ulp_bde64));
4779
4780 if (phba->cfg_sg_seg_cnt > LPFC_MAX_SG_SEG_CNT_DIF)
4781 phba->cfg_sg_seg_cnt = LPFC_MAX_SG_SEG_CNT_DIF;
4782
4783
4784 phba->cfg_total_seg_cnt = LPFC_MAX_SG_SEG_CNT;
4785 } else {
4786
4787
4788
4789
4790
4791 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
4792 sizeof(struct fcp_rsp) +
4793 ((phba->cfg_sg_seg_cnt + 2) * sizeof(struct ulp_bde64));
4794
4795
4796 phba->cfg_total_seg_cnt = phba->cfg_sg_seg_cnt + 2;
4797 }
4798
4799 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_FCP,
4800 "9088 sg_tablesize:%d dmabuf_size:%d total_bde:%d\n",
4801 phba->cfg_sg_seg_cnt, phba->cfg_sg_dma_buf_size,
4802 phba->cfg_total_seg_cnt);
4803
4804 phba->max_vpi = LPFC_MAX_VPI;
4805
4806 phba->max_vports = 0;
4807
4808
4809
4810
4811 lpfc_sli_setup(phba);
4812 lpfc_sli_queue_setup(phba);
4813
4814
4815 if (lpfc_mem_alloc(phba, BPL_ALIGN_SZ))
4816 return -ENOMEM;
4817
4818
4819
4820
4821
4822 if (phba->cfg_sriov_nr_virtfn > 0) {
4823 rc = lpfc_sli_probe_sriov_nr_virtfn(phba,
4824 phba->cfg_sriov_nr_virtfn);
4825 if (rc) {
4826 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
4827 "2808 Requested number of SR-IOV "
4828 "virtual functions (%d) is not "
4829 "supported\n",
4830 phba->cfg_sriov_nr_virtfn);
4831 phba->cfg_sriov_nr_virtfn = 0;
4832 }
4833 }
4834
4835 return 0;
4836}
4837
4838
4839
4840
4841
4842
4843
4844
4845static void
4846lpfc_sli_driver_resource_unset(struct lpfc_hba *phba)
4847{
4848
4849 lpfc_mem_free_all(phba);
4850
4851 return;
4852}
4853
4854
4855
4856
4857
4858
4859
4860
4861
4862
4863
4864
4865static int
4866lpfc_sli4_driver_resource_setup(struct lpfc_hba *phba)
4867{
4868 struct lpfc_vector_map_info *cpup;
4869 struct lpfc_sli *psli;
4870 LPFC_MBOXQ_t *mboxq;
4871 int rc, i, hbq_count, max_buf_size;
4872 uint8_t pn_page[LPFC_MAX_SUPPORTED_PAGES] = {0};
4873 struct lpfc_mqe *mqe;
4874 int longs;
4875
4876
4877 rc = lpfc_sli4_post_status_check(phba);
4878 if (rc)
4879 return -ENODEV;
4880
4881
4882
4883
4884
4885
4886 init_timer(&phba->hb_tmofunc);
4887 phba->hb_tmofunc.function = lpfc_hb_timeout;
4888 phba->hb_tmofunc.data = (unsigned long)phba;
4889 init_timer(&phba->rrq_tmr);
4890 phba->rrq_tmr.function = lpfc_rrq_timeout;
4891 phba->rrq_tmr.data = (unsigned long)phba;
4892
4893 psli = &phba->sli;
4894
4895 init_timer(&psli->mbox_tmo);
4896 psli->mbox_tmo.function = lpfc_mbox_timeout;
4897 psli->mbox_tmo.data = (unsigned long) phba;
4898
4899 init_timer(&phba->fabric_block_timer);
4900 phba->fabric_block_timer.function = lpfc_fabric_block_timeout;
4901 phba->fabric_block_timer.data = (unsigned long) phba;
4902
4903 init_timer(&phba->eratt_poll);
4904 phba->eratt_poll.function = lpfc_poll_eratt;
4905 phba->eratt_poll.data = (unsigned long) phba;
4906
4907 init_timer(&phba->fcf.redisc_wait);
4908 phba->fcf.redisc_wait.function = lpfc_sli4_fcf_redisc_wait_tmo;
4909 phba->fcf.redisc_wait.data = (unsigned long)phba;
4910
4911
4912
4913
4914
4915 memset((uint8_t *)&phba->mbox_ext_buf_ctx, 0,
4916 sizeof(struct lpfc_mbox_ext_buf_ctx));
4917 INIT_LIST_HEAD(&phba->mbox_ext_buf_ctx.ext_dmabuf_list);
4918
4919
4920
4921
4922
4923
4924
4925
4926
4927 lpfc_get_cfgparam(phba);
4928 phba->max_vpi = LPFC_MAX_VPI;
4929
4930
4931 phba->cfg_fcp_io_channel = phba->cfg_fcp_eq_count;
4932
4933
4934 phba->max_vports = 0;
4935
4936
4937 phba->valid_vlan = 0;
4938 phba->fc_map[0] = LPFC_FCOE_FCF_MAP0;
4939 phba->fc_map[1] = LPFC_FCOE_FCF_MAP1;
4940 phba->fc_map[2] = LPFC_FCOE_FCF_MAP2;
4941
4942
4943
4944
4945
4946 if (!phba->sli.ring)
4947 phba->sli.ring = kzalloc(
4948 (LPFC_SLI3_MAX_RING + phba->cfg_fcp_io_channel) *
4949 sizeof(struct lpfc_sli_ring), GFP_KERNEL);
4950 if (!phba->sli.ring)
4951 return -ENOMEM;
4952
4953
4954
4955
4956
4957
4958 max_buf_size = (2 * SLI4_PAGE_SIZE);
4959 if (phba->cfg_sg_seg_cnt > LPFC_MAX_SGL_SEG_CNT - 2)
4960 phba->cfg_sg_seg_cnt = LPFC_MAX_SGL_SEG_CNT - 2;
4961
4962
4963
4964
4965
4966
4967 if (phba->cfg_enable_bg) {
4968
4969
4970
4971
4972
4973
4974
4975
4976
4977 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
4978 sizeof(struct fcp_rsp) + max_buf_size;
4979
4980
4981 phba->cfg_total_seg_cnt = LPFC_MAX_SGL_SEG_CNT;
4982
4983 if (phba->cfg_sg_seg_cnt > LPFC_MAX_SG_SLI4_SEG_CNT_DIF)
4984 phba->cfg_sg_seg_cnt = LPFC_MAX_SG_SLI4_SEG_CNT_DIF;
4985 } else {
4986
4987
4988
4989
4990
4991 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
4992 sizeof(struct fcp_rsp) +
4993 ((phba->cfg_sg_seg_cnt + 2) * sizeof(struct sli4_sge));
4994
4995
4996 phba->cfg_total_seg_cnt = phba->cfg_sg_seg_cnt + 2;
4997
4998
4999
5000
5001 }
5002
5003
5004 lpfc_vport_template.sg_tablesize = phba->cfg_sg_seg_cnt;
5005 lpfc_template.sg_tablesize = phba->cfg_sg_seg_cnt;
5006
5007 if (phba->cfg_sg_dma_buf_size <= LPFC_MIN_SG_SLI4_BUF_SZ)
5008 phba->cfg_sg_dma_buf_size = LPFC_MIN_SG_SLI4_BUF_SZ;
5009 else
5010 phba->cfg_sg_dma_buf_size =
5011 SLI4_PAGE_ALIGN(phba->cfg_sg_dma_buf_size);
5012
5013 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_FCP,
5014 "9087 sg_tablesize:%d dmabuf_size:%d total_sge:%d\n",
5015 phba->cfg_sg_seg_cnt, phba->cfg_sg_dma_buf_size,
5016 phba->cfg_total_seg_cnt);
5017
5018
5019 hbq_count = lpfc_sli_hbq_count();
5020 for (i = 0; i < hbq_count; ++i)
5021 INIT_LIST_HEAD(&phba->hbqs[i].hbq_buffer_list);
5022 INIT_LIST_HEAD(&phba->rb_pend_list);
5023 phba->hbqs[LPFC_ELS_HBQ].hbq_alloc_buffer = lpfc_sli4_rb_alloc;
5024 phba->hbqs[LPFC_ELS_HBQ].hbq_free_buffer = lpfc_sli4_rb_free;
5025
5026
5027
5028
5029
5030 spin_lock_init(&phba->sli4_hba.abts_scsi_buf_list_lock);
5031 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_scsi_buf_list);
5032
5033 spin_lock_init(&phba->sli4_hba.abts_sgl_list_lock);
5034
5035
5036
5037
5038
5039
5040 INIT_LIST_HEAD(&phba->sli4_hba.sp_cqe_event_pool);
5041
5042 INIT_LIST_HEAD(&phba->sli4_hba.sp_queue_event);
5043
5044 INIT_LIST_HEAD(&phba->sli4_hba.sp_asynce_work_queue);
5045
5046 INIT_LIST_HEAD(&phba->sli4_hba.sp_fcp_xri_aborted_work_queue);
5047
5048 INIT_LIST_HEAD(&phba->sli4_hba.sp_els_xri_aborted_work_queue);
5049
5050 INIT_LIST_HEAD(&phba->sli4_hba.sp_unsol_work_queue);
5051
5052
5053 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_rpi_blk_list);
5054 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_xri_blk_list);
5055 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_vfi_blk_list);
5056 INIT_LIST_HEAD(&phba->lpfc_vpi_blk_list);
5057
5058
5059 lpfc_sli_setup(phba);
5060 lpfc_sli_queue_setup(phba);
5061
5062
5063 rc = lpfc_mem_alloc(phba, SGL_ALIGN_SZ);
5064 if (rc)
5065 return -ENOMEM;
5066
5067
5068 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
5069 LPFC_SLI_INTF_IF_TYPE_2) {
5070 rc = lpfc_pci_function_reset(phba);
5071 if (unlikely(rc))
5072 return -ENODEV;
5073 }
5074
5075
5076 rc = lpfc_create_bootstrap_mbox(phba);
5077 if (unlikely(rc))
5078 goto out_free_mem;
5079
5080
5081 rc = lpfc_setup_endian_order(phba);
5082 if (unlikely(rc))
5083 goto out_free_bsmbx;
5084
5085
5086 rc = lpfc_sli4_read_config(phba);
5087 if (unlikely(rc))
5088 goto out_free_bsmbx;
5089
5090
5091 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
5092 LPFC_SLI_INTF_IF_TYPE_0) {
5093 rc = lpfc_pci_function_reset(phba);
5094 if (unlikely(rc))
5095 goto out_free_bsmbx;
5096 }
5097
5098 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
5099 GFP_KERNEL);
5100 if (!mboxq) {
5101 rc = -ENOMEM;
5102 goto out_free_bsmbx;
5103 }
5104
5105
5106 lpfc_supported_pages(mboxq);
5107 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
5108 if (!rc) {
5109 mqe = &mboxq->u.mqe;
5110 memcpy(&pn_page[0], ((uint8_t *)&mqe->un.supp_pages.word3),
5111 LPFC_MAX_SUPPORTED_PAGES);
5112 for (i = 0; i < LPFC_MAX_SUPPORTED_PAGES; i++) {
5113 switch (pn_page[i]) {
5114 case LPFC_SLI4_PARAMETERS:
5115 phba->sli4_hba.pc_sli4_params.supported = 1;
5116 break;
5117 default:
5118 break;
5119 }
5120 }
5121
5122 if (phba->sli4_hba.pc_sli4_params.supported)
5123 rc = lpfc_pc_sli4_params_get(phba, mboxq);
5124 if (rc) {
5125 mempool_free(mboxq, phba->mbox_mem_pool);
5126 rc = -EIO;
5127 goto out_free_bsmbx;
5128 }
5129 }
5130
5131
5132
5133
5134
5135 rc = lpfc_get_sli4_parameters(phba, mboxq);
5136 if (rc) {
5137 if (phba->sli4_hba.extents_in_use &&
5138 phba->sli4_hba.rpi_hdrs_in_use) {
5139 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5140 "2999 Unsupported SLI4 Parameters "
5141 "Extents and RPI headers enabled.\n");
5142 goto out_free_bsmbx;
5143 }
5144 }
5145 mempool_free(mboxq, phba->mbox_mem_pool);
5146
5147 rc = lpfc_sli4_queue_verify(phba);
5148 if (rc)
5149 goto out_free_bsmbx;
5150
5151
5152 rc = lpfc_sli4_cq_event_pool_create(phba);
5153 if (rc)
5154 goto out_free_bsmbx;
5155
5156
5157 lpfc_init_sgl_list(phba);
5158
5159
5160 rc = lpfc_init_active_sgl_array(phba);
5161 if (rc) {
5162 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5163 "1430 Failed to initialize sgl list.\n");
5164 goto out_destroy_cq_event_pool;
5165 }
5166 rc = lpfc_sli4_init_rpi_hdrs(phba);
5167 if (rc) {
5168 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5169 "1432 Failed to initialize rpi headers.\n");
5170 goto out_free_active_sgl;
5171 }
5172
5173
5174 longs = (LPFC_SLI4_FCF_TBL_INDX_MAX + BITS_PER_LONG - 1)/BITS_PER_LONG;
5175 phba->fcf.fcf_rr_bmask = kzalloc(longs * sizeof(unsigned long),
5176 GFP_KERNEL);
5177 if (!phba->fcf.fcf_rr_bmask) {
5178 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5179 "2759 Failed allocate memory for FCF round "
5180 "robin failover bmask\n");
5181 rc = -ENOMEM;
5182 goto out_remove_rpi_hdrs;
5183 }
5184
5185 phba->sli4_hba.fcp_eq_hdl =
5186 kzalloc((sizeof(struct lpfc_fcp_eq_hdl) *
5187 phba->cfg_fcp_io_channel), GFP_KERNEL);
5188 if (!phba->sli4_hba.fcp_eq_hdl) {
5189 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5190 "2572 Failed allocate memory for "
5191 "fast-path per-EQ handle array\n");
5192 rc = -ENOMEM;
5193 goto out_free_fcf_rr_bmask;
5194 }
5195
5196 phba->sli4_hba.msix_entries = kzalloc((sizeof(struct msix_entry) *
5197 phba->cfg_fcp_io_channel), GFP_KERNEL);
5198 if (!phba->sli4_hba.msix_entries) {
5199 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5200 "2573 Failed allocate memory for msi-x "
5201 "interrupt vector entries\n");
5202 rc = -ENOMEM;
5203 goto out_free_fcp_eq_hdl;
5204 }
5205
5206 phba->sli4_hba.cpu_map = kzalloc((sizeof(struct lpfc_vector_map_info) *
5207 phba->sli4_hba.num_present_cpu),
5208 GFP_KERNEL);
5209 if (!phba->sli4_hba.cpu_map) {
5210 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5211 "3327 Failed allocate memory for msi-x "
5212 "interrupt vector mapping\n");
5213 rc = -ENOMEM;
5214 goto out_free_msix;
5215 }
5216
5217 cpup = phba->sli4_hba.cpu_map;
5218 rc = 0;
5219 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
5220 cpup->channel_id = rc;
5221 rc++;
5222 if (rc >= phba->cfg_fcp_io_channel)
5223 rc = 0;
5224 }
5225
5226
5227
5228
5229
5230 if (phba->cfg_sriov_nr_virtfn > 0) {
5231 rc = lpfc_sli_probe_sriov_nr_virtfn(phba,
5232 phba->cfg_sriov_nr_virtfn);
5233 if (rc) {
5234 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
5235 "3020 Requested number of SR-IOV "
5236 "virtual functions (%d) is not "
5237 "supported\n",
5238 phba->cfg_sriov_nr_virtfn);
5239 phba->cfg_sriov_nr_virtfn = 0;
5240 }
5241 }
5242
5243 return 0;
5244
5245out_free_msix:
5246 kfree(phba->sli4_hba.msix_entries);
5247out_free_fcp_eq_hdl:
5248 kfree(phba->sli4_hba.fcp_eq_hdl);
5249out_free_fcf_rr_bmask:
5250 kfree(phba->fcf.fcf_rr_bmask);
5251out_remove_rpi_hdrs:
5252 lpfc_sli4_remove_rpi_hdrs(phba);
5253out_free_active_sgl:
5254 lpfc_free_active_sgl(phba);
5255out_destroy_cq_event_pool:
5256 lpfc_sli4_cq_event_pool_destroy(phba);
5257out_free_bsmbx:
5258 lpfc_destroy_bootstrap_mbox(phba);
5259out_free_mem:
5260 lpfc_mem_free(phba);
5261 return rc;
5262}
5263
5264
5265
5266
5267
5268
5269
5270
5271static void
5272lpfc_sli4_driver_resource_unset(struct lpfc_hba *phba)
5273{
5274 struct lpfc_fcf_conn_entry *conn_entry, *next_conn_entry;
5275
5276
5277 kfree(phba->sli4_hba.cpu_map);
5278 phba->sli4_hba.num_present_cpu = 0;
5279 phba->sli4_hba.num_online_cpu = 0;
5280
5281
5282 kfree(phba->sli4_hba.msix_entries);
5283
5284
5285 kfree(phba->sli4_hba.fcp_eq_hdl);
5286
5287
5288 lpfc_sli4_remove_rpi_hdrs(phba);
5289 lpfc_sli4_remove_rpis(phba);
5290
5291
5292 kfree(phba->fcf.fcf_rr_bmask);
5293
5294
5295 lpfc_free_active_sgl(phba);
5296 lpfc_free_els_sgl_list(phba);
5297
5298
5299 lpfc_sli4_cq_event_release_all(phba);
5300 lpfc_sli4_cq_event_pool_destroy(phba);
5301
5302
5303 lpfc_sli4_dealloc_resource_identifiers(phba);
5304
5305
5306 lpfc_destroy_bootstrap_mbox(phba);
5307
5308
5309 lpfc_mem_free_all(phba);
5310
5311
5312 list_for_each_entry_safe(conn_entry, next_conn_entry,
5313 &phba->fcf_conn_rec_list, list) {
5314 list_del_init(&conn_entry->list);
5315 kfree(conn_entry);
5316 }
5317
5318 return;
5319}
5320
5321
5322
5323
5324
5325
5326
5327
5328
5329
5330
5331int
5332lpfc_init_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)
5333{
5334 phba->lpfc_hba_init_link = lpfc_hba_init_link;
5335 phba->lpfc_hba_down_link = lpfc_hba_down_link;
5336 phba->lpfc_selective_reset = lpfc_selective_reset;
5337 switch (dev_grp) {
5338 case LPFC_PCI_DEV_LP:
5339 phba->lpfc_hba_down_post = lpfc_hba_down_post_s3;
5340 phba->lpfc_handle_eratt = lpfc_handle_eratt_s3;
5341 phba->lpfc_stop_port = lpfc_stop_port_s3;
5342 break;
5343 case LPFC_PCI_DEV_OC:
5344 phba->lpfc_hba_down_post = lpfc_hba_down_post_s4;
5345 phba->lpfc_handle_eratt = lpfc_handle_eratt_s4;
5346 phba->lpfc_stop_port = lpfc_stop_port_s4;
5347 break;
5348 default:
5349 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5350 "1431 Invalid HBA PCI-device group: 0x%x\n",
5351 dev_grp);
5352 return -ENODEV;
5353 break;
5354 }
5355 return 0;
5356}
5357
5358
5359
5360
5361
5362
5363
5364
5365
5366
5367
5368
5369static int
5370lpfc_setup_driver_resource_phase1(struct lpfc_hba *phba)
5371{
5372
5373
5374
5375 atomic_set(&phba->fast_event_count, 0);
5376 spin_lock_init(&phba->hbalock);
5377
5378
5379 spin_lock_init(&phba->ndlp_lock);
5380
5381 INIT_LIST_HEAD(&phba->port_list);
5382 INIT_LIST_HEAD(&phba->work_list);
5383 init_waitqueue_head(&phba->wait_4_mlo_m_q);
5384
5385
5386 init_waitqueue_head(&phba->work_waitq);
5387
5388
5389 spin_lock_init(&phba->scsi_buf_list_get_lock);
5390 INIT_LIST_HEAD(&phba->lpfc_scsi_buf_list_get);
5391 spin_lock_init(&phba->scsi_buf_list_put_lock);
5392 INIT_LIST_HEAD(&phba->lpfc_scsi_buf_list_put);
5393
5394
5395 INIT_LIST_HEAD(&phba->fabric_iocb_list);
5396
5397
5398 INIT_LIST_HEAD(&phba->elsbuf);
5399
5400
5401 INIT_LIST_HEAD(&phba->fcf_conn_rec_list);
5402
5403 return 0;
5404}
5405
5406
5407
5408
5409
5410
5411
5412
5413
5414
5415
5416
5417static int
5418lpfc_setup_driver_resource_phase2(struct lpfc_hba *phba)
5419{
5420 int error;
5421
5422
5423 phba->worker_thread = kthread_run(lpfc_do_work, phba,
5424 "lpfc_worker_%d", phba->brd_no);
5425 if (IS_ERR(phba->worker_thread)) {
5426 error = PTR_ERR(phba->worker_thread);
5427 return error;
5428 }
5429
5430 return 0;
5431}
5432
5433
5434
5435
5436
5437
5438
5439
5440
5441static void
5442lpfc_unset_driver_resource_phase2(struct lpfc_hba *phba)
5443{
5444
5445 kthread_stop(phba->worker_thread);
5446}
5447
5448
5449
5450
5451
5452
5453
5454static void
5455lpfc_free_iocb_list(struct lpfc_hba *phba)
5456{
5457 struct lpfc_iocbq *iocbq_entry = NULL, *iocbq_next = NULL;
5458
5459 spin_lock_irq(&phba->hbalock);
5460 list_for_each_entry_safe(iocbq_entry, iocbq_next,
5461 &phba->lpfc_iocb_list, list) {
5462 list_del(&iocbq_entry->list);
5463 kfree(iocbq_entry);
5464 phba->total_iocbq_bufs--;
5465 }
5466 spin_unlock_irq(&phba->hbalock);
5467
5468 return;
5469}
5470
5471
5472
5473
5474
5475
5476
5477
5478
5479
5480
5481
5482static int
5483lpfc_init_iocb_list(struct lpfc_hba *phba, int iocb_count)
5484{
5485 struct lpfc_iocbq *iocbq_entry = NULL;
5486 uint16_t iotag;
5487 int i;
5488
5489
5490 INIT_LIST_HEAD(&phba->lpfc_iocb_list);
5491 for (i = 0; i < iocb_count; i++) {
5492 iocbq_entry = kzalloc(sizeof(struct lpfc_iocbq), GFP_KERNEL);
5493 if (iocbq_entry == NULL) {
5494 printk(KERN_ERR "%s: only allocated %d iocbs of "
5495 "expected %d count. Unloading driver.\n",
5496 __func__, i, LPFC_IOCB_LIST_CNT);
5497 goto out_free_iocbq;
5498 }
5499
5500 iotag = lpfc_sli_next_iotag(phba, iocbq_entry);
5501 if (iotag == 0) {
5502 kfree(iocbq_entry);
5503 printk(KERN_ERR "%s: failed to allocate IOTAG. "
5504 "Unloading driver.\n", __func__);
5505 goto out_free_iocbq;
5506 }
5507 iocbq_entry->sli4_lxritag = NO_XRI;
5508 iocbq_entry->sli4_xritag = NO_XRI;
5509
5510 spin_lock_irq(&phba->hbalock);
5511 list_add(&iocbq_entry->list, &phba->lpfc_iocb_list);
5512 phba->total_iocbq_bufs++;
5513 spin_unlock_irq(&phba->hbalock);
5514 }
5515
5516 return 0;
5517
5518out_free_iocbq:
5519 lpfc_free_iocb_list(phba);
5520
5521 return -ENOMEM;
5522}
5523
5524
5525
5526
5527
5528
5529
5530
5531void
5532lpfc_free_sgl_list(struct lpfc_hba *phba, struct list_head *sglq_list)
5533{
5534 struct lpfc_sglq *sglq_entry = NULL, *sglq_next = NULL;
5535
5536 list_for_each_entry_safe(sglq_entry, sglq_next, sglq_list, list) {
5537 list_del(&sglq_entry->list);
5538 lpfc_mbuf_free(phba, sglq_entry->virt, sglq_entry->phys);
5539 kfree(sglq_entry);
5540 }
5541}
5542
5543
5544
5545
5546
5547
5548
5549static void
5550lpfc_free_els_sgl_list(struct lpfc_hba *phba)
5551{
5552 LIST_HEAD(sglq_list);
5553
5554
5555 spin_lock_irq(&phba->hbalock);
5556 list_splice_init(&phba->sli4_hba.lpfc_sgl_list, &sglq_list);
5557 spin_unlock_irq(&phba->hbalock);
5558
5559
5560 lpfc_free_sgl_list(phba, &sglq_list);
5561}
5562
5563
5564
5565
5566
5567
5568
5569
5570static int
5571lpfc_init_active_sgl_array(struct lpfc_hba *phba)
5572{
5573 int size;
5574 size = sizeof(struct lpfc_sglq *);
5575 size *= phba->sli4_hba.max_cfg_param.max_xri;
5576
5577 phba->sli4_hba.lpfc_sglq_active_list =
5578 kzalloc(size, GFP_KERNEL);
5579 if (!phba->sli4_hba.lpfc_sglq_active_list)
5580 return -ENOMEM;
5581 return 0;
5582}
5583
5584
5585
5586
5587
5588
5589
5590
5591
5592static void
5593lpfc_free_active_sgl(struct lpfc_hba *phba)
5594{
5595 kfree(phba->sli4_hba.lpfc_sglq_active_list);
5596}
5597
5598
5599
5600
5601
5602
5603
5604
5605
5606static void
5607lpfc_init_sgl_list(struct lpfc_hba *phba)
5608{
5609
5610 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_sgl_list);
5611 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_els_sgl_list);
5612
5613
5614 phba->sli4_hba.els_xri_cnt = 0;
5615
5616
5617 phba->sli4_hba.scsi_xri_cnt = 0;
5618}
5619
5620
5621
5622
5623
5624
5625
5626
5627
5628
5629
5630
5631
5632
5633
5634int
5635lpfc_sli4_init_rpi_hdrs(struct lpfc_hba *phba)
5636{
5637 int rc = 0;
5638 struct lpfc_rpi_hdr *rpi_hdr;
5639
5640 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_rpi_hdr_list);
5641 if (!phba->sli4_hba.rpi_hdrs_in_use)
5642 return rc;
5643 if (phba->sli4_hba.extents_in_use)
5644 return -EIO;
5645
5646 rpi_hdr = lpfc_sli4_create_rpi_hdr(phba);
5647 if (!rpi_hdr) {
5648 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX | LOG_SLI,
5649 "0391 Error during rpi post operation\n");
5650 lpfc_sli4_remove_rpis(phba);
5651 rc = -ENODEV;
5652 }
5653
5654 return rc;
5655}
5656
5657
5658
5659
5660
5661
5662
5663
5664
5665
5666
5667
5668
5669
5670struct lpfc_rpi_hdr *
5671lpfc_sli4_create_rpi_hdr(struct lpfc_hba *phba)
5672{
5673 uint16_t rpi_limit, curr_rpi_range;
5674 struct lpfc_dmabuf *dmabuf;
5675 struct lpfc_rpi_hdr *rpi_hdr;
5676 uint32_t rpi_count;
5677
5678
5679
5680
5681
5682
5683 if (!phba->sli4_hba.rpi_hdrs_in_use)
5684 return NULL;
5685 if (phba->sli4_hba.extents_in_use)
5686 return NULL;
5687
5688
5689 rpi_limit = phba->sli4_hba.max_cfg_param.rpi_base +
5690 phba->sli4_hba.max_cfg_param.max_rpi - 1;
5691
5692 spin_lock_irq(&phba->hbalock);
5693
5694
5695
5696
5697
5698 curr_rpi_range = phba->sli4_hba.next_rpi;
5699 spin_unlock_irq(&phba->hbalock);
5700
5701
5702
5703
5704
5705
5706 if ((curr_rpi_range + (LPFC_RPI_HDR_COUNT - 1)) > rpi_limit)
5707 rpi_count = rpi_limit - curr_rpi_range;
5708 else
5709 rpi_count = LPFC_RPI_HDR_COUNT;
5710
5711 if (!rpi_count)
5712 return NULL;
5713
5714
5715
5716
5717 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
5718 if (!dmabuf)
5719 return NULL;
5720
5721 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev,
5722 LPFC_HDR_TEMPLATE_SIZE,
5723 &dmabuf->phys,
5724 GFP_KERNEL);
5725 if (!dmabuf->virt) {
5726 rpi_hdr = NULL;
5727 goto err_free_dmabuf;
5728 }
5729
5730 memset(dmabuf->virt, 0, LPFC_HDR_TEMPLATE_SIZE);
5731 if (!IS_ALIGNED(dmabuf->phys, LPFC_HDR_TEMPLATE_SIZE)) {
5732 rpi_hdr = NULL;
5733 goto err_free_coherent;
5734 }
5735
5736
5737 rpi_hdr = kzalloc(sizeof(struct lpfc_rpi_hdr), GFP_KERNEL);
5738 if (!rpi_hdr)
5739 goto err_free_coherent;
5740
5741 rpi_hdr->dmabuf = dmabuf;
5742 rpi_hdr->len = LPFC_HDR_TEMPLATE_SIZE;
5743 rpi_hdr->page_count = 1;
5744 spin_lock_irq(&phba->hbalock);
5745
5746
5747 rpi_hdr->start_rpi = curr_rpi_range;
5748 list_add_tail(&rpi_hdr->list, &phba->sli4_hba.lpfc_rpi_hdr_list);
5749
5750
5751
5752
5753
5754 phba->sli4_hba.next_rpi += rpi_count;
5755 spin_unlock_irq(&phba->hbalock);
5756 return rpi_hdr;
5757
5758 err_free_coherent:
5759 dma_free_coherent(&phba->pcidev->dev, LPFC_HDR_TEMPLATE_SIZE,
5760 dmabuf->virt, dmabuf->phys);
5761 err_free_dmabuf:
5762 kfree(dmabuf);
5763 return NULL;
5764}
5765
5766
5767
5768
5769
5770
5771
5772
5773
5774
5775void
5776lpfc_sli4_remove_rpi_hdrs(struct lpfc_hba *phba)
5777{
5778 struct lpfc_rpi_hdr *rpi_hdr, *next_rpi_hdr;
5779
5780 if (!phba->sli4_hba.rpi_hdrs_in_use)
5781 goto exit;
5782
5783 list_for_each_entry_safe(rpi_hdr, next_rpi_hdr,
5784 &phba->sli4_hba.lpfc_rpi_hdr_list, list) {
5785 list_del(&rpi_hdr->list);
5786 dma_free_coherent(&phba->pcidev->dev, rpi_hdr->len,
5787 rpi_hdr->dmabuf->virt, rpi_hdr->dmabuf->phys);
5788 kfree(rpi_hdr->dmabuf);
5789 kfree(rpi_hdr);
5790 }
5791 exit:
5792
5793 phba->sli4_hba.next_rpi = 0;
5794}
5795
5796
5797
5798
5799
5800
5801
5802
5803
5804
5805
5806
5807
5808static struct lpfc_hba *
5809lpfc_hba_alloc(struct pci_dev *pdev)
5810{
5811 struct lpfc_hba *phba;
5812
5813
5814 phba = kzalloc(sizeof(struct lpfc_hba), GFP_KERNEL);
5815 if (!phba) {
5816 dev_err(&pdev->dev, "failed to allocate hba struct\n");
5817 return NULL;
5818 }
5819
5820
5821 phba->pcidev = pdev;
5822
5823
5824 phba->brd_no = lpfc_get_instance();
5825 if (phba->brd_no < 0) {
5826 kfree(phba);
5827 return NULL;
5828 }
5829
5830 spin_lock_init(&phba->ct_ev_lock);
5831 INIT_LIST_HEAD(&phba->ct_ev_waiters);
5832
5833 return phba;
5834}
5835
5836
5837
5838
5839
5840
5841
5842
5843static void
5844lpfc_hba_free(struct lpfc_hba *phba)
5845{
5846
5847 idr_remove(&lpfc_hba_index, phba->brd_no);
5848
5849
5850 kfree(phba->sli.ring);
5851 phba->sli.ring = NULL;
5852
5853 kfree(phba);
5854 return;
5855}
5856
5857
5858
5859
5860
5861
5862
5863
5864
5865
5866
5867
5868static int
5869lpfc_create_shost(struct lpfc_hba *phba)
5870{
5871 struct lpfc_vport *vport;
5872 struct Scsi_Host *shost;
5873
5874
5875 phba->fc_edtov = FF_DEF_EDTOV;
5876 phba->fc_ratov = FF_DEF_RATOV;
5877 phba->fc_altov = FF_DEF_ALTOV;
5878 phba->fc_arbtov = FF_DEF_ARBTOV;
5879
5880 atomic_set(&phba->sdev_cnt, 0);
5881 vport = lpfc_create_port(phba, phba->brd_no, &phba->pcidev->dev);
5882 if (!vport)
5883 return -ENODEV;
5884
5885 shost = lpfc_shost_from_vport(vport);
5886 phba->pport = vport;
5887 lpfc_debugfs_initialize(vport);
5888
5889 pci_set_drvdata(phba->pcidev, shost);
5890
5891 return 0;
5892}
5893
5894
5895
5896
5897
5898
5899
5900
5901static void
5902lpfc_destroy_shost(struct lpfc_hba *phba)
5903{
5904 struct lpfc_vport *vport = phba->pport;
5905
5906
5907 destroy_port(vport);
5908
5909 return;
5910}
5911
5912
5913
5914
5915
5916
5917
5918
5919
5920static void
5921lpfc_setup_bg(struct lpfc_hba *phba, struct Scsi_Host *shost)
5922{
5923 uint32_t old_mask;
5924 uint32_t old_guard;
5925
5926 int pagecnt = 10;
5927 if (lpfc_prot_mask && lpfc_prot_guard) {
5928 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
5929 "1478 Registering BlockGuard with the "
5930 "SCSI layer\n");
5931
5932 old_mask = lpfc_prot_mask;
5933 old_guard = lpfc_prot_guard;
5934
5935
5936 lpfc_prot_mask &= (SHOST_DIF_TYPE1_PROTECTION |
5937 SHOST_DIX_TYPE0_PROTECTION |
5938 SHOST_DIX_TYPE1_PROTECTION);
5939 lpfc_prot_guard &= (SHOST_DIX_GUARD_IP | SHOST_DIX_GUARD_CRC);
5940
5941
5942 if (lpfc_prot_mask == SHOST_DIX_TYPE1_PROTECTION)
5943 lpfc_prot_mask |= SHOST_DIF_TYPE1_PROTECTION;
5944
5945 if (lpfc_prot_mask && lpfc_prot_guard) {
5946 if ((old_mask != lpfc_prot_mask) ||
5947 (old_guard != lpfc_prot_guard))
5948 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5949 "1475 Registering BlockGuard with the "
5950 "SCSI layer: mask %d guard %d\n",
5951 lpfc_prot_mask, lpfc_prot_guard);
5952
5953 scsi_host_set_prot(shost, lpfc_prot_mask);
5954 scsi_host_set_guard(shost, lpfc_prot_guard);
5955 } else
5956 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5957 "1479 Not Registering BlockGuard with the SCSI "
5958 "layer, Bad protection parameters: %d %d\n",
5959 old_mask, old_guard);
5960 }
5961
5962 if (!_dump_buf_data) {
5963 while (pagecnt) {
5964 spin_lock_init(&_dump_buf_lock);
5965 _dump_buf_data =
5966 (char *) __get_free_pages(GFP_KERNEL, pagecnt);
5967 if (_dump_buf_data) {
5968 lpfc_printf_log(phba, KERN_ERR, LOG_BG,
5969 "9043 BLKGRD: allocated %d pages for "
5970 "_dump_buf_data at 0x%p\n",
5971 (1 << pagecnt), _dump_buf_data);
5972 _dump_buf_data_order = pagecnt;
5973 memset(_dump_buf_data, 0,
5974 ((1 << PAGE_SHIFT) << pagecnt));
5975 break;
5976 } else
5977 --pagecnt;
5978 }
5979 if (!_dump_buf_data_order)
5980 lpfc_printf_log(phba, KERN_ERR, LOG_BG,
5981 "9044 BLKGRD: ERROR unable to allocate "
5982 "memory for hexdump\n");
5983 } else
5984 lpfc_printf_log(phba, KERN_ERR, LOG_BG,
5985 "9045 BLKGRD: already allocated _dump_buf_data=0x%p"
5986 "\n", _dump_buf_data);
5987 if (!_dump_buf_dif) {
5988 while (pagecnt) {
5989 _dump_buf_dif =
5990 (char *) __get_free_pages(GFP_KERNEL, pagecnt);
5991 if (_dump_buf_dif) {
5992 lpfc_printf_log(phba, KERN_ERR, LOG_BG,
5993 "9046 BLKGRD: allocated %d pages for "
5994 "_dump_buf_dif at 0x%p\n",
5995 (1 << pagecnt), _dump_buf_dif);
5996 _dump_buf_dif_order = pagecnt;
5997 memset(_dump_buf_dif, 0,
5998 ((1 << PAGE_SHIFT) << pagecnt));
5999 break;
6000 } else
6001 --pagecnt;
6002 }
6003 if (!_dump_buf_dif_order)
6004 lpfc_printf_log(phba, KERN_ERR, LOG_BG,
6005 "9047 BLKGRD: ERROR unable to allocate "
6006 "memory for hexdump\n");
6007 } else
6008 lpfc_printf_log(phba, KERN_ERR, LOG_BG,
6009 "9048 BLKGRD: already allocated _dump_buf_dif=0x%p\n",
6010 _dump_buf_dif);
6011}
6012
6013
6014
6015
6016
6017
6018
6019
6020static void
6021lpfc_post_init_setup(struct lpfc_hba *phba)
6022{
6023 struct Scsi_Host *shost;
6024 struct lpfc_adapter_event_header adapter_event;
6025
6026
6027 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
6028
6029
6030
6031
6032
6033 shost = pci_get_drvdata(phba->pcidev);
6034 shost->can_queue = phba->cfg_hba_queue_depth - 10;
6035 if (phba->sli3_options & LPFC_SLI3_BG_ENABLED)
6036 lpfc_setup_bg(phba, shost);
6037
6038 lpfc_host_attrib_init(shost);
6039
6040 if (phba->cfg_poll & DISABLE_FCP_RING_INT) {
6041 spin_lock_irq(shost->host_lock);
6042 lpfc_poll_start_timer(phba);
6043 spin_unlock_irq(shost->host_lock);
6044 }
6045
6046 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
6047 "0428 Perform SCSI scan\n");
6048
6049 adapter_event.event_type = FC_REG_ADAPTER_EVENT;
6050 adapter_event.subcategory = LPFC_EVENT_ARRIVAL;
6051 fc_host_post_vendor_event(shost, fc_get_event_number(),
6052 sizeof(adapter_event),
6053 (char *) &adapter_event,
6054 LPFC_NL_VENDOR_ID);
6055 return;
6056}
6057
6058
6059
6060
6061
6062
6063
6064
6065
6066
6067
6068
6069static int
6070lpfc_sli_pci_mem_setup(struct lpfc_hba *phba)
6071{
6072 struct pci_dev *pdev;
6073 unsigned long bar0map_len, bar2map_len;
6074 int i, hbq_count;
6075 void *ptr;
6076 int error = -ENODEV;
6077
6078
6079 if (!phba->pcidev)
6080 return error;
6081 else
6082 pdev = phba->pcidev;
6083
6084
6085 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0
6086 || pci_set_consistent_dma_mask(pdev,DMA_BIT_MASK(64)) != 0) {
6087 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0
6088 || pci_set_consistent_dma_mask(pdev,DMA_BIT_MASK(32)) != 0) {
6089 return error;
6090 }
6091 }
6092
6093
6094
6095
6096 phba->pci_bar0_map = pci_resource_start(pdev, 0);
6097 bar0map_len = pci_resource_len(pdev, 0);
6098
6099 phba->pci_bar2_map = pci_resource_start(pdev, 2);
6100 bar2map_len = pci_resource_len(pdev, 2);
6101
6102
6103 phba->slim_memmap_p = ioremap(phba->pci_bar0_map, bar0map_len);
6104 if (!phba->slim_memmap_p) {
6105 dev_printk(KERN_ERR, &pdev->dev,
6106 "ioremap failed for SLIM memory.\n");
6107 goto out;
6108 }
6109
6110
6111 phba->ctrl_regs_memmap_p = ioremap(phba->pci_bar2_map, bar2map_len);
6112 if (!phba->ctrl_regs_memmap_p) {
6113 dev_printk(KERN_ERR, &pdev->dev,
6114 "ioremap failed for HBA control registers.\n");
6115 goto out_iounmap_slim;
6116 }
6117
6118
6119 phba->slim2p.virt = dma_alloc_coherent(&pdev->dev,
6120 SLI2_SLIM_SIZE,
6121 &phba->slim2p.phys,
6122 GFP_KERNEL);
6123 if (!phba->slim2p.virt)
6124 goto out_iounmap;
6125
6126 memset(phba->slim2p.virt, 0, SLI2_SLIM_SIZE);
6127 phba->mbox = phba->slim2p.virt + offsetof(struct lpfc_sli2_slim, mbx);
6128 phba->mbox_ext = (phba->slim2p.virt +
6129 offsetof(struct lpfc_sli2_slim, mbx_ext_words));
6130 phba->pcb = (phba->slim2p.virt + offsetof(struct lpfc_sli2_slim, pcb));
6131 phba->IOCBs = (phba->slim2p.virt +
6132 offsetof(struct lpfc_sli2_slim, IOCBs));
6133
6134 phba->hbqslimp.virt = dma_alloc_coherent(&pdev->dev,
6135 lpfc_sli_hbq_size(),
6136 &phba->hbqslimp.phys,
6137 GFP_KERNEL);
6138 if (!phba->hbqslimp.virt)
6139 goto out_free_slim;
6140
6141 hbq_count = lpfc_sli_hbq_count();
6142 ptr = phba->hbqslimp.virt;
6143 for (i = 0; i < hbq_count; ++i) {
6144 phba->hbqs[i].hbq_virt = ptr;
6145 INIT_LIST_HEAD(&phba->hbqs[i].hbq_buffer_list);
6146 ptr += (lpfc_hbq_defs[i]->entry_count *
6147 sizeof(struct lpfc_hbq_entry));
6148 }
6149 phba->hbqs[LPFC_ELS_HBQ].hbq_alloc_buffer = lpfc_els_hbq_alloc;
6150 phba->hbqs[LPFC_ELS_HBQ].hbq_free_buffer = lpfc_els_hbq_free;
6151
6152 memset(phba->hbqslimp.virt, 0, lpfc_sli_hbq_size());
6153
6154 INIT_LIST_HEAD(&phba->rb_pend_list);
6155
6156 phba->MBslimaddr = phba->slim_memmap_p;
6157 phba->HAregaddr = phba->ctrl_regs_memmap_p + HA_REG_OFFSET;
6158 phba->CAregaddr = phba->ctrl_regs_memmap_p + CA_REG_OFFSET;
6159 phba->HSregaddr = phba->ctrl_regs_memmap_p + HS_REG_OFFSET;
6160 phba->HCregaddr = phba->ctrl_regs_memmap_p + HC_REG_OFFSET;
6161
6162 return 0;
6163
6164out_free_slim:
6165 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
6166 phba->slim2p.virt, phba->slim2p.phys);
6167out_iounmap:
6168 iounmap(phba->ctrl_regs_memmap_p);
6169out_iounmap_slim:
6170 iounmap(phba->slim_memmap_p);
6171out:
6172 return error;
6173}
6174
6175
6176
6177
6178
6179
6180
6181
6182static void
6183lpfc_sli_pci_mem_unset(struct lpfc_hba *phba)
6184{
6185 struct pci_dev *pdev;
6186
6187
6188 if (!phba->pcidev)
6189 return;
6190 else
6191 pdev = phba->pcidev;
6192
6193
6194 dma_free_coherent(&pdev->dev, lpfc_sli_hbq_size(),
6195 phba->hbqslimp.virt, phba->hbqslimp.phys);
6196 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
6197 phba->slim2p.virt, phba->slim2p.phys);
6198
6199
6200 iounmap(phba->ctrl_regs_memmap_p);
6201 iounmap(phba->slim_memmap_p);
6202
6203 return;
6204}
6205
6206
6207
6208
6209
6210
6211
6212
6213
6214
6215int
6216lpfc_sli4_post_status_check(struct lpfc_hba *phba)
6217{
6218 struct lpfc_register portsmphr_reg, uerrlo_reg, uerrhi_reg;
6219 struct lpfc_register reg_data;
6220 int i, port_error = 0;
6221 uint32_t if_type;
6222
6223 memset(&portsmphr_reg, 0, sizeof(portsmphr_reg));
6224 memset(®_data, 0, sizeof(reg_data));
6225 if (!phba->sli4_hba.PSMPHRregaddr)
6226 return -ENODEV;
6227
6228
6229 for (i = 0; i < 3000; i++) {
6230 if (lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
6231 &portsmphr_reg.word0) ||
6232 (bf_get(lpfc_port_smphr_perr, &portsmphr_reg))) {
6233
6234 port_error = -ENODEV;
6235 break;
6236 }
6237 if (LPFC_POST_STAGE_PORT_READY ==
6238 bf_get(lpfc_port_smphr_port_status, &portsmphr_reg))
6239 break;
6240 msleep(10);
6241 }
6242
6243
6244
6245
6246
6247 if (port_error) {
6248 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6249 "1408 Port Failed POST - portsmphr=0x%x, "
6250 "perr=x%x, sfi=x%x, nip=x%x, ipc=x%x, scr1=x%x, "
6251 "scr2=x%x, hscratch=x%x, pstatus=x%x\n",
6252 portsmphr_reg.word0,
6253 bf_get(lpfc_port_smphr_perr, &portsmphr_reg),
6254 bf_get(lpfc_port_smphr_sfi, &portsmphr_reg),
6255 bf_get(lpfc_port_smphr_nip, &portsmphr_reg),
6256 bf_get(lpfc_port_smphr_ipc, &portsmphr_reg),
6257 bf_get(lpfc_port_smphr_scr1, &portsmphr_reg),
6258 bf_get(lpfc_port_smphr_scr2, &portsmphr_reg),
6259 bf_get(lpfc_port_smphr_host_scratch, &portsmphr_reg),
6260 bf_get(lpfc_port_smphr_port_status, &portsmphr_reg));
6261 } else {
6262 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
6263 "2534 Device Info: SLIFamily=0x%x, "
6264 "SLIRev=0x%x, IFType=0x%x, SLIHint_1=0x%x, "
6265 "SLIHint_2=0x%x, FT=0x%x\n",
6266 bf_get(lpfc_sli_intf_sli_family,
6267 &phba->sli4_hba.sli_intf),
6268 bf_get(lpfc_sli_intf_slirev,
6269 &phba->sli4_hba.sli_intf),
6270 bf_get(lpfc_sli_intf_if_type,
6271 &phba->sli4_hba.sli_intf),
6272 bf_get(lpfc_sli_intf_sli_hint1,
6273 &phba->sli4_hba.sli_intf),
6274 bf_get(lpfc_sli_intf_sli_hint2,
6275 &phba->sli4_hba.sli_intf),
6276 bf_get(lpfc_sli_intf_func_type,
6277 &phba->sli4_hba.sli_intf));
6278
6279
6280
6281
6282
6283 if_type = bf_get(lpfc_sli_intf_if_type,
6284 &phba->sli4_hba.sli_intf);
6285 switch (if_type) {
6286 case LPFC_SLI_INTF_IF_TYPE_0:
6287 phba->sli4_hba.ue_mask_lo =
6288 readl(phba->sli4_hba.u.if_type0.UEMASKLOregaddr);
6289 phba->sli4_hba.ue_mask_hi =
6290 readl(phba->sli4_hba.u.if_type0.UEMASKHIregaddr);
6291 uerrlo_reg.word0 =
6292 readl(phba->sli4_hba.u.if_type0.UERRLOregaddr);
6293 uerrhi_reg.word0 =
6294 readl(phba->sli4_hba.u.if_type0.UERRHIregaddr);
6295 if ((~phba->sli4_hba.ue_mask_lo & uerrlo_reg.word0) ||
6296 (~phba->sli4_hba.ue_mask_hi & uerrhi_reg.word0)) {
6297 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6298 "1422 Unrecoverable Error "
6299 "Detected during POST "
6300 "uerr_lo_reg=0x%x, "
6301 "uerr_hi_reg=0x%x, "
6302 "ue_mask_lo_reg=0x%x, "
6303 "ue_mask_hi_reg=0x%x\n",
6304 uerrlo_reg.word0,
6305 uerrhi_reg.word0,
6306 phba->sli4_hba.ue_mask_lo,
6307 phba->sli4_hba.ue_mask_hi);
6308 port_error = -ENODEV;
6309 }
6310 break;
6311 case LPFC_SLI_INTF_IF_TYPE_2:
6312
6313 if (lpfc_readl(phba->sli4_hba.u.if_type2.STATUSregaddr,
6314 ®_data.word0) ||
6315 (bf_get(lpfc_sliport_status_err, ®_data) &&
6316 !bf_get(lpfc_sliport_status_rn, ®_data))) {
6317 phba->work_status[0] =
6318 readl(phba->sli4_hba.u.if_type2.
6319 ERR1regaddr);
6320 phba->work_status[1] =
6321 readl(phba->sli4_hba.u.if_type2.
6322 ERR2regaddr);
6323 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6324 "2888 Unrecoverable port error "
6325 "following POST: port status reg "
6326 "0x%x, port_smphr reg 0x%x, "
6327 "error 1=0x%x, error 2=0x%x\n",
6328 reg_data.word0,
6329 portsmphr_reg.word0,
6330 phba->work_status[0],
6331 phba->work_status[1]);
6332 port_error = -ENODEV;
6333 }
6334 break;
6335 case LPFC_SLI_INTF_IF_TYPE_1:
6336 default:
6337 break;
6338 }
6339 }
6340 return port_error;
6341}
6342
6343
6344
6345
6346
6347
6348
6349
6350
6351static void
6352lpfc_sli4_bar0_register_memmap(struct lpfc_hba *phba, uint32_t if_type)
6353{
6354 switch (if_type) {
6355 case LPFC_SLI_INTF_IF_TYPE_0:
6356 phba->sli4_hba.u.if_type0.UERRLOregaddr =
6357 phba->sli4_hba.conf_regs_memmap_p + LPFC_UERR_STATUS_LO;
6358 phba->sli4_hba.u.if_type0.UERRHIregaddr =
6359 phba->sli4_hba.conf_regs_memmap_p + LPFC_UERR_STATUS_HI;
6360 phba->sli4_hba.u.if_type0.UEMASKLOregaddr =
6361 phba->sli4_hba.conf_regs_memmap_p + LPFC_UE_MASK_LO;
6362 phba->sli4_hba.u.if_type0.UEMASKHIregaddr =
6363 phba->sli4_hba.conf_regs_memmap_p + LPFC_UE_MASK_HI;
6364 phba->sli4_hba.SLIINTFregaddr =
6365 phba->sli4_hba.conf_regs_memmap_p + LPFC_SLI_INTF;
6366 break;
6367 case LPFC_SLI_INTF_IF_TYPE_2:
6368 phba->sli4_hba.u.if_type2.ERR1regaddr =
6369 phba->sli4_hba.conf_regs_memmap_p +
6370 LPFC_CTL_PORT_ER1_OFFSET;
6371 phba->sli4_hba.u.if_type2.ERR2regaddr =
6372 phba->sli4_hba.conf_regs_memmap_p +
6373 LPFC_CTL_PORT_ER2_OFFSET;
6374 phba->sli4_hba.u.if_type2.CTRLregaddr =
6375 phba->sli4_hba.conf_regs_memmap_p +
6376 LPFC_CTL_PORT_CTL_OFFSET;
6377 phba->sli4_hba.u.if_type2.STATUSregaddr =
6378 phba->sli4_hba.conf_regs_memmap_p +
6379 LPFC_CTL_PORT_STA_OFFSET;
6380 phba->sli4_hba.SLIINTFregaddr =
6381 phba->sli4_hba.conf_regs_memmap_p + LPFC_SLI_INTF;
6382 phba->sli4_hba.PSMPHRregaddr =
6383 phba->sli4_hba.conf_regs_memmap_p +
6384 LPFC_CTL_PORT_SEM_OFFSET;
6385 phba->sli4_hba.RQDBregaddr =
6386 phba->sli4_hba.conf_regs_memmap_p +
6387 LPFC_ULP0_RQ_DOORBELL;
6388 phba->sli4_hba.WQDBregaddr =
6389 phba->sli4_hba.conf_regs_memmap_p +
6390 LPFC_ULP0_WQ_DOORBELL;
6391 phba->sli4_hba.EQCQDBregaddr =
6392 phba->sli4_hba.conf_regs_memmap_p + LPFC_EQCQ_DOORBELL;
6393 phba->sli4_hba.MQDBregaddr =
6394 phba->sli4_hba.conf_regs_memmap_p + LPFC_MQ_DOORBELL;
6395 phba->sli4_hba.BMBXregaddr =
6396 phba->sli4_hba.conf_regs_memmap_p + LPFC_BMBX;
6397 break;
6398 case LPFC_SLI_INTF_IF_TYPE_1:
6399 default:
6400 dev_printk(KERN_ERR, &phba->pcidev->dev,
6401 "FATAL - unsupported SLI4 interface type - %d\n",
6402 if_type);
6403 break;
6404 }
6405}
6406
6407
6408
6409
6410
6411
6412
6413
6414static void
6415lpfc_sli4_bar1_register_memmap(struct lpfc_hba *phba)
6416{
6417 phba->sli4_hba.PSMPHRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
6418 LPFC_SLIPORT_IF0_SMPHR;
6419 phba->sli4_hba.ISRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
6420 LPFC_HST_ISR0;
6421 phba->sli4_hba.IMRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
6422 LPFC_HST_IMR0;
6423 phba->sli4_hba.ISCRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
6424 LPFC_HST_ISCR0;
6425}
6426
6427
6428
6429
6430
6431
6432
6433
6434
6435
6436
6437static int
6438lpfc_sli4_bar2_register_memmap(struct lpfc_hba *phba, uint32_t vf)
6439{
6440 if (vf > LPFC_VIR_FUNC_MAX)
6441 return -ENODEV;
6442
6443 phba->sli4_hba.RQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
6444 vf * LPFC_VFR_PAGE_SIZE +
6445 LPFC_ULP0_RQ_DOORBELL);
6446 phba->sli4_hba.WQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
6447 vf * LPFC_VFR_PAGE_SIZE +
6448 LPFC_ULP0_WQ_DOORBELL);
6449 phba->sli4_hba.EQCQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
6450 vf * LPFC_VFR_PAGE_SIZE + LPFC_EQCQ_DOORBELL);
6451 phba->sli4_hba.MQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
6452 vf * LPFC_VFR_PAGE_SIZE + LPFC_MQ_DOORBELL);
6453 phba->sli4_hba.BMBXregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
6454 vf * LPFC_VFR_PAGE_SIZE + LPFC_BMBX);
6455 return 0;
6456}
6457
6458
6459
6460
6461
6462
6463
6464
6465
6466
6467
6468
6469
6470
6471
6472
6473static int
6474lpfc_create_bootstrap_mbox(struct lpfc_hba *phba)
6475{
6476 uint32_t bmbx_size;
6477 struct lpfc_dmabuf *dmabuf;
6478 struct dma_address *dma_address;
6479 uint32_t pa_addr;
6480 uint64_t phys_addr;
6481
6482 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
6483 if (!dmabuf)
6484 return -ENOMEM;
6485
6486
6487
6488
6489
6490 bmbx_size = sizeof(struct lpfc_bmbx_create) + (LPFC_ALIGN_16_BYTE - 1);
6491 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev,
6492 bmbx_size,
6493 &dmabuf->phys,
6494 GFP_KERNEL);
6495 if (!dmabuf->virt) {
6496 kfree(dmabuf);
6497 return -ENOMEM;
6498 }
6499 memset(dmabuf->virt, 0, bmbx_size);
6500
6501
6502
6503
6504
6505
6506
6507
6508 phba->sli4_hba.bmbx.dmabuf = dmabuf;
6509 phba->sli4_hba.bmbx.bmbx_size = bmbx_size;
6510
6511 phba->sli4_hba.bmbx.avirt = PTR_ALIGN(dmabuf->virt,
6512 LPFC_ALIGN_16_BYTE);
6513 phba->sli4_hba.bmbx.aphys = ALIGN(dmabuf->phys,
6514 LPFC_ALIGN_16_BYTE);
6515
6516
6517
6518
6519
6520
6521
6522
6523
6524 dma_address = &phba->sli4_hba.bmbx.dma_address;
6525 phys_addr = (uint64_t)phba->sli4_hba.bmbx.aphys;
6526 pa_addr = (uint32_t) ((phys_addr >> 34) & 0x3fffffff);
6527 dma_address->addr_hi = (uint32_t) ((pa_addr << 2) |
6528 LPFC_BMBX_BIT1_ADDR_HI);
6529
6530 pa_addr = (uint32_t) ((phba->sli4_hba.bmbx.aphys >> 4) & 0x3fffffff);
6531 dma_address->addr_lo = (uint32_t) ((pa_addr << 2) |
6532 LPFC_BMBX_BIT1_ADDR_LO);
6533 return 0;
6534}
6535
6536
6537
6538
6539
6540
6541
6542
6543
6544
6545
6546
6547static void
6548lpfc_destroy_bootstrap_mbox(struct lpfc_hba *phba)
6549{
6550 dma_free_coherent(&phba->pcidev->dev,
6551 phba->sli4_hba.bmbx.bmbx_size,
6552 phba->sli4_hba.bmbx.dmabuf->virt,
6553 phba->sli4_hba.bmbx.dmabuf->phys);
6554
6555 kfree(phba->sli4_hba.bmbx.dmabuf);
6556 memset(&phba->sli4_hba.bmbx, 0, sizeof(struct lpfc_bmbx));
6557}
6558
6559
6560
6561
6562
6563
6564
6565
6566
6567
6568
6569
6570
6571
6572
6573int
6574lpfc_sli4_read_config(struct lpfc_hba *phba)
6575{
6576 LPFC_MBOXQ_t *pmb;
6577 struct lpfc_mbx_read_config *rd_config;
6578 union lpfc_sli4_cfg_shdr *shdr;
6579 uint32_t shdr_status, shdr_add_status;
6580 struct lpfc_mbx_get_func_cfg *get_func_cfg;
6581 struct lpfc_rsrc_desc_fcfcoe *desc;
6582 char *pdesc_0;
6583 uint32_t desc_count;
6584 int length, i, rc = 0, rc2;
6585
6586 pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
6587 if (!pmb) {
6588 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
6589 "2011 Unable to allocate memory for issuing "
6590 "SLI_CONFIG_SPECIAL mailbox command\n");
6591 return -ENOMEM;
6592 }
6593
6594 lpfc_read_config(phba, pmb);
6595
6596 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
6597 if (rc != MBX_SUCCESS) {
6598 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
6599 "2012 Mailbox failed , mbxCmd x%x "
6600 "READ_CONFIG, mbxStatus x%x\n",
6601 bf_get(lpfc_mqe_command, &pmb->u.mqe),
6602 bf_get(lpfc_mqe_status, &pmb->u.mqe));
6603 rc = -EIO;
6604 } else {
6605 rd_config = &pmb->u.mqe.un.rd_config;
6606 if (bf_get(lpfc_mbx_rd_conf_lnk_ldv, rd_config)) {
6607 phba->sli4_hba.lnk_info.lnk_dv = LPFC_LNK_DAT_VAL;
6608 phba->sli4_hba.lnk_info.lnk_tp =
6609 bf_get(lpfc_mbx_rd_conf_lnk_type, rd_config);
6610 phba->sli4_hba.lnk_info.lnk_no =
6611 bf_get(lpfc_mbx_rd_conf_lnk_numb, rd_config);
6612 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
6613 "3081 lnk_type:%d, lnk_numb:%d\n",
6614 phba->sli4_hba.lnk_info.lnk_tp,
6615 phba->sli4_hba.lnk_info.lnk_no);
6616 } else
6617 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
6618 "3082 Mailbox (x%x) returned ldv:x0\n",
6619 bf_get(lpfc_mqe_command, &pmb->u.mqe));
6620 phba->sli4_hba.extents_in_use =
6621 bf_get(lpfc_mbx_rd_conf_extnts_inuse, rd_config);
6622 phba->sli4_hba.max_cfg_param.max_xri =
6623 bf_get(lpfc_mbx_rd_conf_xri_count, rd_config);
6624 phba->sli4_hba.max_cfg_param.xri_base =
6625 bf_get(lpfc_mbx_rd_conf_xri_base, rd_config);
6626 phba->sli4_hba.max_cfg_param.max_vpi =
6627 bf_get(lpfc_mbx_rd_conf_vpi_count, rd_config);
6628 phba->sli4_hba.max_cfg_param.vpi_base =
6629 bf_get(lpfc_mbx_rd_conf_vpi_base, rd_config);
6630 phba->sli4_hba.max_cfg_param.max_rpi =
6631 bf_get(lpfc_mbx_rd_conf_rpi_count, rd_config);
6632 phba->sli4_hba.max_cfg_param.rpi_base =
6633 bf_get(lpfc_mbx_rd_conf_rpi_base, rd_config);
6634 phba->sli4_hba.max_cfg_param.max_vfi =
6635 bf_get(lpfc_mbx_rd_conf_vfi_count, rd_config);
6636 phba->sli4_hba.max_cfg_param.vfi_base =
6637 bf_get(lpfc_mbx_rd_conf_vfi_base, rd_config);
6638 phba->sli4_hba.max_cfg_param.max_fcfi =
6639 bf_get(lpfc_mbx_rd_conf_fcfi_count, rd_config);
6640 phba->sli4_hba.max_cfg_param.max_eq =
6641 bf_get(lpfc_mbx_rd_conf_eq_count, rd_config);
6642 phba->sli4_hba.max_cfg_param.max_rq =
6643 bf_get(lpfc_mbx_rd_conf_rq_count, rd_config);
6644 phba->sli4_hba.max_cfg_param.max_wq =
6645 bf_get(lpfc_mbx_rd_conf_wq_count, rd_config);
6646 phba->sli4_hba.max_cfg_param.max_cq =
6647 bf_get(lpfc_mbx_rd_conf_cq_count, rd_config);
6648 phba->lmt = bf_get(lpfc_mbx_rd_conf_lmt, rd_config);
6649 phba->sli4_hba.next_xri = phba->sli4_hba.max_cfg_param.xri_base;
6650 phba->vpi_base = phba->sli4_hba.max_cfg_param.vpi_base;
6651 phba->vfi_base = phba->sli4_hba.max_cfg_param.vfi_base;
6652 phba->max_vpi = (phba->sli4_hba.max_cfg_param.max_vpi > 0) ?
6653 (phba->sli4_hba.max_cfg_param.max_vpi - 1) : 0;
6654 phba->max_vports = phba->max_vpi;
6655 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
6656 "2003 cfg params Extents? %d "
6657 "XRI(B:%d M:%d), "
6658 "VPI(B:%d M:%d) "
6659 "VFI(B:%d M:%d) "
6660 "RPI(B:%d M:%d) "
6661 "FCFI(Count:%d)\n",
6662 phba->sli4_hba.extents_in_use,
6663 phba->sli4_hba.max_cfg_param.xri_base,
6664 phba->sli4_hba.max_cfg_param.max_xri,
6665 phba->sli4_hba.max_cfg_param.vpi_base,
6666 phba->sli4_hba.max_cfg_param.max_vpi,
6667 phba->sli4_hba.max_cfg_param.vfi_base,
6668 phba->sli4_hba.max_cfg_param.max_vfi,
6669 phba->sli4_hba.max_cfg_param.rpi_base,
6670 phba->sli4_hba.max_cfg_param.max_rpi,
6671 phba->sli4_hba.max_cfg_param.max_fcfi);
6672 }
6673
6674 if (rc)
6675 goto read_cfg_out;
6676
6677
6678 if (phba->cfg_hba_queue_depth >
6679 (phba->sli4_hba.max_cfg_param.max_xri -
6680 lpfc_sli4_get_els_iocb_cnt(phba)))
6681 phba->cfg_hba_queue_depth =
6682 phba->sli4_hba.max_cfg_param.max_xri -
6683 lpfc_sli4_get_els_iocb_cnt(phba);
6684
6685 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) !=
6686 LPFC_SLI_INTF_IF_TYPE_2)
6687 goto read_cfg_out;
6688
6689
6690 length = (sizeof(struct lpfc_mbx_get_func_cfg) -
6691 sizeof(struct lpfc_sli4_cfg_mhdr));
6692 lpfc_sli4_config(phba, pmb, LPFC_MBOX_SUBSYSTEM_COMMON,
6693 LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG,
6694 length, LPFC_SLI4_MBX_EMBED);
6695
6696 rc2 = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
6697 shdr = (union lpfc_sli4_cfg_shdr *)
6698 &pmb->u.mqe.un.sli4_config.header.cfg_shdr;
6699 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
6700 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, &shdr->response);
6701 if (rc2 || shdr_status || shdr_add_status) {
6702 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
6703 "3026 Mailbox failed , mbxCmd x%x "
6704 "GET_FUNCTION_CONFIG, mbxStatus x%x\n",
6705 bf_get(lpfc_mqe_command, &pmb->u.mqe),
6706 bf_get(lpfc_mqe_status, &pmb->u.mqe));
6707 goto read_cfg_out;
6708 }
6709
6710
6711 get_func_cfg = &pmb->u.mqe.un.get_func_cfg;
6712 desc_count = get_func_cfg->func_cfg.rsrc_desc_count;
6713
6714 pdesc_0 = (char *)&get_func_cfg->func_cfg.desc[0];
6715 desc = (struct lpfc_rsrc_desc_fcfcoe *)pdesc_0;
6716 length = bf_get(lpfc_rsrc_desc_fcfcoe_length, desc);
6717 if (length == LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD)
6718 length = LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH;
6719 else if (length != LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH)
6720 goto read_cfg_out;
6721
6722 for (i = 0; i < LPFC_RSRC_DESC_MAX_NUM; i++) {
6723 desc = (struct lpfc_rsrc_desc_fcfcoe *)(pdesc_0 + length * i);
6724 if (LPFC_RSRC_DESC_TYPE_FCFCOE ==
6725 bf_get(lpfc_rsrc_desc_fcfcoe_type, desc)) {
6726 phba->sli4_hba.iov.pf_number =
6727 bf_get(lpfc_rsrc_desc_fcfcoe_pfnum, desc);
6728 phba->sli4_hba.iov.vf_number =
6729 bf_get(lpfc_rsrc_desc_fcfcoe_vfnum, desc);
6730 break;
6731 }
6732 }
6733
6734 if (i < LPFC_RSRC_DESC_MAX_NUM)
6735 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
6736 "3027 GET_FUNCTION_CONFIG: pf_number:%d, "
6737 "vf_number:%d\n", phba->sli4_hba.iov.pf_number,
6738 phba->sli4_hba.iov.vf_number);
6739 else
6740 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
6741 "3028 GET_FUNCTION_CONFIG: failed to find "
6742 "Resrouce Descriptor:x%x\n",
6743 LPFC_RSRC_DESC_TYPE_FCFCOE);
6744
6745read_cfg_out:
6746 mempool_free(pmb, phba->mbox_mem_pool);
6747 return rc;
6748}
6749
6750
6751
6752
6753
6754
6755
6756
6757
6758
6759
6760
6761
6762
6763static int
6764lpfc_setup_endian_order(struct lpfc_hba *phba)
6765{
6766 LPFC_MBOXQ_t *mboxq;
6767 uint32_t if_type, rc = 0;
6768 uint32_t endian_mb_data[2] = {HOST_ENDIAN_LOW_WORD0,
6769 HOST_ENDIAN_HIGH_WORD1};
6770
6771 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
6772 switch (if_type) {
6773 case LPFC_SLI_INTF_IF_TYPE_0:
6774 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
6775 GFP_KERNEL);
6776 if (!mboxq) {
6777 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6778 "0492 Unable to allocate memory for "
6779 "issuing SLI_CONFIG_SPECIAL mailbox "
6780 "command\n");
6781 return -ENOMEM;
6782 }
6783
6784
6785
6786
6787
6788 memset(mboxq, 0, sizeof(LPFC_MBOXQ_t));
6789 memcpy(&mboxq->u.mqe, &endian_mb_data, sizeof(endian_mb_data));
6790 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
6791 if (rc != MBX_SUCCESS) {
6792 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6793 "0493 SLI_CONFIG_SPECIAL mailbox "
6794 "failed with status x%x\n",
6795 rc);
6796 rc = -EIO;
6797 }
6798 mempool_free(mboxq, phba->mbox_mem_pool);
6799 break;
6800 case LPFC_SLI_INTF_IF_TYPE_2:
6801 case LPFC_SLI_INTF_IF_TYPE_1:
6802 default:
6803 break;
6804 }
6805 return rc;
6806}
6807
6808
6809
6810
6811
6812
6813
6814
6815
6816
6817
6818
6819
6820
6821static int
6822lpfc_sli4_queue_verify(struct lpfc_hba *phba)
6823{
6824 int cfg_fcp_io_channel;
6825 uint32_t cpu;
6826 uint32_t i = 0;
6827 uint32_t j = 0;
6828
6829
6830
6831
6832
6833
6834
6835
6836 cfg_fcp_io_channel = phba->cfg_fcp_io_channel;
6837
6838
6839 for_each_present_cpu(cpu) {
6840 if (cpu_online(cpu))
6841 i++;
6842 j++;
6843 }
6844 phba->sli4_hba.num_online_cpu = i;
6845 phba->sli4_hba.num_present_cpu = j;
6846
6847 if (i < cfg_fcp_io_channel) {
6848 lpfc_printf_log(phba,
6849 KERN_ERR, LOG_INIT,
6850 "3188 Reducing IO channels to match number of "
6851 "online CPUs: from %d to %d\n",
6852 cfg_fcp_io_channel, i);
6853 cfg_fcp_io_channel = i;
6854 }
6855
6856 if (cfg_fcp_io_channel >
6857 phba->sli4_hba.max_cfg_param.max_eq) {
6858 if (phba->sli4_hba.max_cfg_param.max_eq <
6859 LPFC_FCP_IO_CHAN_MIN) {
6860 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6861 "2574 Not enough EQs (%d) from the "
6862 "pci function for supporting FCP "
6863 "EQs (%d)\n",
6864 phba->sli4_hba.max_cfg_param.max_eq,
6865 phba->cfg_fcp_io_channel);
6866 goto out_error;
6867 }
6868 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6869 "2575 Reducing IO channels to match number of "
6870 "available EQs: from %d to %d\n",
6871 cfg_fcp_io_channel,
6872 phba->sli4_hba.max_cfg_param.max_eq);
6873 cfg_fcp_io_channel = phba->sli4_hba.max_cfg_param.max_eq;
6874 }
6875
6876
6877
6878
6879 phba->cfg_fcp_eq_count = cfg_fcp_io_channel;
6880 phba->cfg_fcp_wq_count = cfg_fcp_io_channel;
6881 phba->cfg_fcp_io_channel = cfg_fcp_io_channel;
6882
6883
6884 phba->sli4_hba.eq_esize = LPFC_EQE_SIZE_4B;
6885 phba->sli4_hba.eq_ecount = LPFC_EQE_DEF_COUNT;
6886
6887
6888 phba->sli4_hba.cq_esize = LPFC_CQE_SIZE;
6889 phba->sli4_hba.cq_ecount = LPFC_CQE_DEF_COUNT;
6890
6891 return 0;
6892out_error:
6893 return -ENOMEM;
6894}
6895
6896
6897
6898
6899
6900
6901
6902
6903
6904
6905
6906
6907
6908
6909
6910int
6911lpfc_sli4_queue_create(struct lpfc_hba *phba)
6912{
6913 struct lpfc_queue *qdesc;
6914 int idx;
6915
6916
6917
6918
6919 if (!phba->cfg_fcp_io_channel)
6920 return -ERANGE;
6921
6922 phba->sli4_hba.mq_esize = LPFC_MQE_SIZE;
6923 phba->sli4_hba.mq_ecount = LPFC_MQE_DEF_COUNT;
6924 phba->sli4_hba.wq_esize = LPFC_WQE_SIZE;
6925 phba->sli4_hba.wq_ecount = LPFC_WQE_DEF_COUNT;
6926 phba->sli4_hba.rq_esize = LPFC_RQE_SIZE;
6927 phba->sli4_hba.rq_ecount = LPFC_RQE_DEF_COUNT;
6928
6929 phba->sli4_hba.hba_eq = kzalloc((sizeof(struct lpfc_queue *) *
6930 phba->cfg_fcp_io_channel), GFP_KERNEL);
6931 if (!phba->sli4_hba.hba_eq) {
6932 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6933 "2576 Failed allocate memory for "
6934 "fast-path EQ record array\n");
6935 goto out_error;
6936 }
6937
6938 phba->sli4_hba.fcp_cq = kzalloc((sizeof(struct lpfc_queue *) *
6939 phba->cfg_fcp_io_channel), GFP_KERNEL);
6940 if (!phba->sli4_hba.fcp_cq) {
6941 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6942 "2577 Failed allocate memory for fast-path "
6943 "CQ record array\n");
6944 goto out_error;
6945 }
6946
6947 phba->sli4_hba.fcp_wq = kzalloc((sizeof(struct lpfc_queue *) *
6948 phba->cfg_fcp_io_channel), GFP_KERNEL);
6949 if (!phba->sli4_hba.fcp_wq) {
6950 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6951 "2578 Failed allocate memory for fast-path "
6952 "WQ record array\n");
6953 goto out_error;
6954 }
6955
6956
6957
6958
6959
6960
6961 phba->sli4_hba.fcp_cq_map = kzalloc((sizeof(uint16_t) *
6962 phba->cfg_fcp_io_channel), GFP_KERNEL);
6963 if (!phba->sli4_hba.fcp_cq_map) {
6964 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6965 "2545 Failed allocate memory for fast-path "
6966 "CQ map\n");
6967 goto out_error;
6968 }
6969
6970
6971
6972
6973
6974 for (idx = 0; idx < phba->cfg_fcp_io_channel; idx++) {
6975
6976
6977 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.eq_esize,
6978 phba->sli4_hba.eq_ecount);
6979 if (!qdesc) {
6980 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6981 "0497 Failed allocate EQ (%d)\n", idx);
6982 goto out_error;
6983 }
6984 phba->sli4_hba.hba_eq[idx] = qdesc;
6985
6986
6987 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.cq_esize,
6988 phba->sli4_hba.cq_ecount);
6989 if (!qdesc) {
6990 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6991 "0499 Failed allocate fast-path FCP "
6992 "CQ (%d)\n", idx);
6993 goto out_error;
6994 }
6995 phba->sli4_hba.fcp_cq[idx] = qdesc;
6996
6997
6998 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.wq_esize,
6999 phba->sli4_hba.wq_ecount);
7000 if (!qdesc) {
7001 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7002 "0503 Failed allocate fast-path FCP "
7003 "WQ (%d)\n", idx);
7004 goto out_error;
7005 }
7006 phba->sli4_hba.fcp_wq[idx] = qdesc;
7007 }
7008
7009
7010
7011
7012
7013
7014
7015 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.cq_esize,
7016 phba->sli4_hba.cq_ecount);
7017 if (!qdesc) {
7018 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7019 "0500 Failed allocate slow-path mailbox CQ\n");
7020 goto out_error;
7021 }
7022 phba->sli4_hba.mbx_cq = qdesc;
7023
7024
7025 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.cq_esize,
7026 phba->sli4_hba.cq_ecount);
7027 if (!qdesc) {
7028 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7029 "0501 Failed allocate slow-path ELS CQ\n");
7030 goto out_error;
7031 }
7032 phba->sli4_hba.els_cq = qdesc;
7033
7034
7035
7036
7037
7038
7039
7040
7041 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.mq_esize,
7042 phba->sli4_hba.mq_ecount);
7043 if (!qdesc) {
7044 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7045 "0505 Failed allocate slow-path MQ\n");
7046 goto out_error;
7047 }
7048 phba->sli4_hba.mbx_wq = qdesc;
7049
7050
7051
7052
7053
7054
7055 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.wq_esize,
7056 phba->sli4_hba.wq_ecount);
7057 if (!qdesc) {
7058 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7059 "0504 Failed allocate slow-path ELS WQ\n");
7060 goto out_error;
7061 }
7062 phba->sli4_hba.els_wq = qdesc;
7063
7064
7065
7066
7067
7068
7069 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.rq_esize,
7070 phba->sli4_hba.rq_ecount);
7071 if (!qdesc) {
7072 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7073 "0506 Failed allocate receive HRQ\n");
7074 goto out_error;
7075 }
7076 phba->sli4_hba.hdr_rq = qdesc;
7077
7078
7079 qdesc = lpfc_sli4_queue_alloc(phba, phba->sli4_hba.rq_esize,
7080 phba->sli4_hba.rq_ecount);
7081 if (!qdesc) {
7082 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7083 "0507 Failed allocate receive DRQ\n");
7084 goto out_error;
7085 }
7086 phba->sli4_hba.dat_rq = qdesc;
7087
7088 return 0;
7089
7090out_error:
7091 lpfc_sli4_queue_destroy(phba);
7092 return -ENOMEM;
7093}
7094
7095
7096
7097
7098
7099
7100
7101
7102
7103
7104
7105
7106
7107void
7108lpfc_sli4_queue_destroy(struct lpfc_hba *phba)
7109{
7110 int idx;
7111
7112 if (phba->sli4_hba.hba_eq != NULL) {
7113
7114 for (idx = 0; idx < phba->cfg_fcp_io_channel; idx++) {
7115 if (phba->sli4_hba.hba_eq[idx] != NULL) {
7116 lpfc_sli4_queue_free(
7117 phba->sli4_hba.hba_eq[idx]);
7118 phba->sli4_hba.hba_eq[idx] = NULL;
7119 }
7120 }
7121 kfree(phba->sli4_hba.hba_eq);
7122 phba->sli4_hba.hba_eq = NULL;
7123 }
7124
7125 if (phba->sli4_hba.fcp_cq != NULL) {
7126
7127 for (idx = 0; idx < phba->cfg_fcp_io_channel; idx++) {
7128 if (phba->sli4_hba.fcp_cq[idx] != NULL) {
7129 lpfc_sli4_queue_free(
7130 phba->sli4_hba.fcp_cq[idx]);
7131 phba->sli4_hba.fcp_cq[idx] = NULL;
7132 }
7133 }
7134 kfree(phba->sli4_hba.fcp_cq);
7135 phba->sli4_hba.fcp_cq = NULL;
7136 }
7137
7138 if (phba->sli4_hba.fcp_wq != NULL) {
7139
7140 for (idx = 0; idx < phba->cfg_fcp_io_channel; idx++) {
7141 if (phba->sli4_hba.fcp_wq[idx] != NULL) {
7142 lpfc_sli4_queue_free(
7143 phba->sli4_hba.fcp_wq[idx]);
7144 phba->sli4_hba.fcp_wq[idx] = NULL;
7145 }
7146 }
7147 kfree(phba->sli4_hba.fcp_wq);
7148 phba->sli4_hba.fcp_wq = NULL;
7149 }
7150
7151 if (phba->pci_bar0_memmap_p) {
7152 iounmap(phba->pci_bar0_memmap_p);
7153 phba->pci_bar0_memmap_p = NULL;
7154 }
7155 if (phba->pci_bar2_memmap_p) {
7156 iounmap(phba->pci_bar2_memmap_p);
7157 phba->pci_bar2_memmap_p = NULL;
7158 }
7159 if (phba->pci_bar4_memmap_p) {
7160 iounmap(phba->pci_bar4_memmap_p);
7161 phba->pci_bar4_memmap_p = NULL;
7162 }
7163
7164
7165 if (phba->sli4_hba.fcp_cq_map != NULL) {
7166 kfree(phba->sli4_hba.fcp_cq_map);
7167 phba->sli4_hba.fcp_cq_map = NULL;
7168 }
7169
7170
7171 if (phba->sli4_hba.mbx_wq != NULL) {
7172 lpfc_sli4_queue_free(phba->sli4_hba.mbx_wq);
7173 phba->sli4_hba.mbx_wq = NULL;
7174 }
7175
7176
7177 if (phba->sli4_hba.els_wq != NULL) {
7178 lpfc_sli4_queue_free(phba->sli4_hba.els_wq);
7179 phba->sli4_hba.els_wq = NULL;
7180 }
7181
7182
7183 if (phba->sli4_hba.hdr_rq != NULL) {
7184 lpfc_sli4_queue_free(phba->sli4_hba.hdr_rq);
7185 phba->sli4_hba.hdr_rq = NULL;
7186 }
7187 if (phba->sli4_hba.dat_rq != NULL) {
7188 lpfc_sli4_queue_free(phba->sli4_hba.dat_rq);
7189 phba->sli4_hba.dat_rq = NULL;
7190 }
7191
7192
7193 if (phba->sli4_hba.els_cq != NULL) {
7194 lpfc_sli4_queue_free(phba->sli4_hba.els_cq);
7195 phba->sli4_hba.els_cq = NULL;
7196 }
7197
7198
7199 if (phba->sli4_hba.mbx_cq != NULL) {
7200 lpfc_sli4_queue_free(phba->sli4_hba.mbx_cq);
7201 phba->sli4_hba.mbx_cq = NULL;
7202 }
7203
7204 return;
7205}
7206
7207
7208
7209
7210
7211
7212
7213
7214
7215
7216
7217
7218
7219int
7220lpfc_sli4_queue_setup(struct lpfc_hba *phba)
7221{
7222 struct lpfc_sli *psli = &phba->sli;
7223 struct lpfc_sli_ring *pring;
7224 int rc = -ENOMEM;
7225 int fcp_eqidx, fcp_cqidx, fcp_wqidx;
7226 int fcp_cq_index = 0;
7227 uint32_t shdr_status, shdr_add_status;
7228 union lpfc_sli4_cfg_shdr *shdr;
7229 LPFC_MBOXQ_t *mboxq;
7230 uint32_t length;
7231
7232
7233 mboxq = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
7234 if (!mboxq) {
7235 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7236 "3249 Unable to allocate memory for "
7237 "QUERY_FW_CFG mailbox command\n");
7238 return -ENOMEM;
7239 }
7240 length = (sizeof(struct lpfc_mbx_query_fw_config) -
7241 sizeof(struct lpfc_sli4_cfg_mhdr));
7242 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
7243 LPFC_MBOX_OPCODE_QUERY_FW_CFG,
7244 length, LPFC_SLI4_MBX_EMBED);
7245
7246 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
7247
7248 shdr = (union lpfc_sli4_cfg_shdr *)
7249 &mboxq->u.mqe.un.sli4_config.header.cfg_shdr;
7250 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
7251 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, &shdr->response);
7252 if (shdr_status || shdr_add_status || rc) {
7253 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7254 "3250 QUERY_FW_CFG mailbox failed with status "
7255 "x%x add_status x%x, mbx status x%x\n",
7256 shdr_status, shdr_add_status, rc);
7257 if (rc != MBX_TIMEOUT)
7258 mempool_free(mboxq, phba->mbox_mem_pool);
7259 rc = -ENXIO;
7260 goto out_error;
7261 }
7262
7263 phba->sli4_hba.fw_func_mode =
7264 mboxq->u.mqe.un.query_fw_cfg.rsp.function_mode;
7265 phba->sli4_hba.ulp0_mode = mboxq->u.mqe.un.query_fw_cfg.rsp.ulp0_mode;
7266 phba->sli4_hba.ulp1_mode = mboxq->u.mqe.un.query_fw_cfg.rsp.ulp1_mode;
7267 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7268 "3251 QUERY_FW_CFG: func_mode:x%x, ulp0_mode:x%x, "
7269 "ulp1_mode:x%x\n", phba->sli4_hba.fw_func_mode,
7270 phba->sli4_hba.ulp0_mode, phba->sli4_hba.ulp1_mode);
7271
7272 if (rc != MBX_TIMEOUT)
7273 mempool_free(mboxq, phba->mbox_mem_pool);
7274
7275
7276
7277
7278
7279
7280 if (phba->cfg_fcp_io_channel && !phba->sli4_hba.hba_eq) {
7281 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7282 "3147 Fast-path EQs not allocated\n");
7283 rc = -ENOMEM;
7284 goto out_error;
7285 }
7286 for (fcp_eqidx = 0; fcp_eqidx < phba->cfg_fcp_io_channel; fcp_eqidx++) {
7287 if (!phba->sli4_hba.hba_eq[fcp_eqidx]) {
7288 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7289 "0522 Fast-path EQ (%d) not "
7290 "allocated\n", fcp_eqidx);
7291 rc = -ENOMEM;
7292 goto out_destroy_hba_eq;
7293 }
7294 rc = lpfc_eq_create(phba, phba->sli4_hba.hba_eq[fcp_eqidx],
7295 (phba->cfg_fcp_imax / phba->cfg_fcp_io_channel));
7296 if (rc) {
7297 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7298 "0523 Failed setup of fast-path EQ "
7299 "(%d), rc = 0x%x\n", fcp_eqidx, rc);
7300 goto out_destroy_hba_eq;
7301 }
7302 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7303 "2584 HBA EQ setup: "
7304 "queue[%d]-id=%d\n", fcp_eqidx,
7305 phba->sli4_hba.hba_eq[fcp_eqidx]->queue_id);
7306 }
7307
7308
7309 if (!phba->sli4_hba.fcp_cq) {
7310 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7311 "3148 Fast-path FCP CQ array not "
7312 "allocated\n");
7313 rc = -ENOMEM;
7314 goto out_destroy_hba_eq;
7315 }
7316
7317 for (fcp_cqidx = 0; fcp_cqidx < phba->cfg_fcp_io_channel; fcp_cqidx++) {
7318 if (!phba->sli4_hba.fcp_cq[fcp_cqidx]) {
7319 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7320 "0526 Fast-path FCP CQ (%d) not "
7321 "allocated\n", fcp_cqidx);
7322 rc = -ENOMEM;
7323 goto out_destroy_fcp_cq;
7324 }
7325 rc = lpfc_cq_create(phba, phba->sli4_hba.fcp_cq[fcp_cqidx],
7326 phba->sli4_hba.hba_eq[fcp_cqidx], LPFC_WCQ, LPFC_FCP);
7327 if (rc) {
7328 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7329 "0527 Failed setup of fast-path FCP "
7330 "CQ (%d), rc = 0x%x\n", fcp_cqidx, rc);
7331 goto out_destroy_fcp_cq;
7332 }
7333
7334
7335 phba->sli4_hba.fcp_cq_map[fcp_cqidx] =
7336 phba->sli4_hba.fcp_cq[fcp_cqidx]->queue_id;
7337
7338 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7339 "2588 FCP CQ setup: cq[%d]-id=%d, "
7340 "parent seq[%d]-id=%d\n",
7341 fcp_cqidx,
7342 phba->sli4_hba.fcp_cq[fcp_cqidx]->queue_id,
7343 fcp_cqidx,
7344 phba->sli4_hba.hba_eq[fcp_cqidx]->queue_id);
7345 }
7346
7347
7348 if (!phba->sli4_hba.fcp_wq) {
7349 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7350 "3149 Fast-path FCP WQ array not "
7351 "allocated\n");
7352 rc = -ENOMEM;
7353 goto out_destroy_fcp_cq;
7354 }
7355
7356 for (fcp_wqidx = 0; fcp_wqidx < phba->cfg_fcp_io_channel; fcp_wqidx++) {
7357 if (!phba->sli4_hba.fcp_wq[fcp_wqidx]) {
7358 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7359 "0534 Fast-path FCP WQ (%d) not "
7360 "allocated\n", fcp_wqidx);
7361 rc = -ENOMEM;
7362 goto out_destroy_fcp_wq;
7363 }
7364 rc = lpfc_wq_create(phba, phba->sli4_hba.fcp_wq[fcp_wqidx],
7365 phba->sli4_hba.fcp_cq[fcp_wqidx],
7366 LPFC_FCP);
7367 if (rc) {
7368 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7369 "0535 Failed setup of fast-path FCP "
7370 "WQ (%d), rc = 0x%x\n", fcp_wqidx, rc);
7371 goto out_destroy_fcp_wq;
7372 }
7373
7374
7375 pring = &psli->ring[MAX_SLI3_CONFIGURED_RINGS + fcp_wqidx];
7376 pring->sli.sli4.wqp = (void *)phba->sli4_hba.fcp_wq[fcp_wqidx];
7377 phba->sli4_hba.fcp_cq[fcp_wqidx]->pring = pring;
7378
7379 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7380 "2591 FCP WQ setup: wq[%d]-id=%d, "
7381 "parent cq[%d]-id=%d\n",
7382 fcp_wqidx,
7383 phba->sli4_hba.fcp_wq[fcp_wqidx]->queue_id,
7384 fcp_cq_index,
7385 phba->sli4_hba.fcp_cq[fcp_wqidx]->queue_id);
7386 }
7387
7388
7389
7390
7391
7392 if (!phba->sli4_hba.mbx_cq) {
7393 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7394 "0528 Mailbox CQ not allocated\n");
7395 rc = -ENOMEM;
7396 goto out_destroy_fcp_wq;
7397 }
7398 rc = lpfc_cq_create(phba, phba->sli4_hba.mbx_cq,
7399 phba->sli4_hba.hba_eq[0], LPFC_MCQ, LPFC_MBOX);
7400 if (rc) {
7401 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7402 "0529 Failed setup of slow-path mailbox CQ: "
7403 "rc = 0x%x\n", rc);
7404 goto out_destroy_fcp_wq;
7405 }
7406 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7407 "2585 MBX CQ setup: cq-id=%d, parent eq-id=%d\n",
7408 phba->sli4_hba.mbx_cq->queue_id,
7409 phba->sli4_hba.hba_eq[0]->queue_id);
7410
7411
7412 if (!phba->sli4_hba.els_cq) {
7413 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7414 "0530 ELS CQ not allocated\n");
7415 rc = -ENOMEM;
7416 goto out_destroy_mbx_cq;
7417 }
7418 rc = lpfc_cq_create(phba, phba->sli4_hba.els_cq,
7419 phba->sli4_hba.hba_eq[0], LPFC_WCQ, LPFC_ELS);
7420 if (rc) {
7421 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7422 "0531 Failed setup of slow-path ELS CQ: "
7423 "rc = 0x%x\n", rc);
7424 goto out_destroy_mbx_cq;
7425 }
7426 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7427 "2586 ELS CQ setup: cq-id=%d, parent eq-id=%d\n",
7428 phba->sli4_hba.els_cq->queue_id,
7429 phba->sli4_hba.hba_eq[0]->queue_id);
7430
7431
7432
7433
7434
7435
7436 if (!phba->sli4_hba.mbx_wq) {
7437 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7438 "0538 Slow-path MQ not allocated\n");
7439 rc = -ENOMEM;
7440 goto out_destroy_els_cq;
7441 }
7442 rc = lpfc_mq_create(phba, phba->sli4_hba.mbx_wq,
7443 phba->sli4_hba.mbx_cq, LPFC_MBOX);
7444 if (rc) {
7445 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7446 "0539 Failed setup of slow-path MQ: "
7447 "rc = 0x%x\n", rc);
7448 goto out_destroy_els_cq;
7449 }
7450 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7451 "2589 MBX MQ setup: wq-id=%d, parent cq-id=%d\n",
7452 phba->sli4_hba.mbx_wq->queue_id,
7453 phba->sli4_hba.mbx_cq->queue_id);
7454
7455
7456 if (!phba->sli4_hba.els_wq) {
7457 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7458 "0536 Slow-path ELS WQ not allocated\n");
7459 rc = -ENOMEM;
7460 goto out_destroy_mbx_wq;
7461 }
7462 rc = lpfc_wq_create(phba, phba->sli4_hba.els_wq,
7463 phba->sli4_hba.els_cq, LPFC_ELS);
7464 if (rc) {
7465 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7466 "0537 Failed setup of slow-path ELS WQ: "
7467 "rc = 0x%x\n", rc);
7468 goto out_destroy_mbx_wq;
7469 }
7470
7471
7472 pring = &psli->ring[LPFC_ELS_RING];
7473 pring->sli.sli4.wqp = (void *)phba->sli4_hba.els_wq;
7474 phba->sli4_hba.els_cq->pring = pring;
7475
7476 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7477 "2590 ELS WQ setup: wq-id=%d, parent cq-id=%d\n",
7478 phba->sli4_hba.els_wq->queue_id,
7479 phba->sli4_hba.els_cq->queue_id);
7480
7481
7482
7483
7484 if (!phba->sli4_hba.hdr_rq || !phba->sli4_hba.dat_rq) {
7485 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7486 "0540 Receive Queue not allocated\n");
7487 rc = -ENOMEM;
7488 goto out_destroy_els_wq;
7489 }
7490
7491 lpfc_rq_adjust_repost(phba, phba->sli4_hba.hdr_rq, LPFC_ELS_HBQ);
7492 lpfc_rq_adjust_repost(phba, phba->sli4_hba.dat_rq, LPFC_ELS_HBQ);
7493
7494 rc = lpfc_rq_create(phba, phba->sli4_hba.hdr_rq, phba->sli4_hba.dat_rq,
7495 phba->sli4_hba.els_cq, LPFC_USOL);
7496 if (rc) {
7497 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7498 "0541 Failed setup of Receive Queue: "
7499 "rc = 0x%x\n", rc);
7500 goto out_destroy_fcp_wq;
7501 }
7502
7503 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7504 "2592 USL RQ setup: hdr-rq-id=%d, dat-rq-id=%d "
7505 "parent cq-id=%d\n",
7506 phba->sli4_hba.hdr_rq->queue_id,
7507 phba->sli4_hba.dat_rq->queue_id,
7508 phba->sli4_hba.els_cq->queue_id);
7509 return 0;
7510
7511out_destroy_els_wq:
7512 lpfc_wq_destroy(phba, phba->sli4_hba.els_wq);
7513out_destroy_mbx_wq:
7514 lpfc_mq_destroy(phba, phba->sli4_hba.mbx_wq);
7515out_destroy_els_cq:
7516 lpfc_cq_destroy(phba, phba->sli4_hba.els_cq);
7517out_destroy_mbx_cq:
7518 lpfc_cq_destroy(phba, phba->sli4_hba.mbx_cq);
7519out_destroy_fcp_wq:
7520 for (--fcp_wqidx; fcp_wqidx >= 0; fcp_wqidx--)
7521 lpfc_wq_destroy(phba, phba->sli4_hba.fcp_wq[fcp_wqidx]);
7522out_destroy_fcp_cq:
7523 for (--fcp_cqidx; fcp_cqidx >= 0; fcp_cqidx--)
7524 lpfc_cq_destroy(phba, phba->sli4_hba.fcp_cq[fcp_cqidx]);
7525out_destroy_hba_eq:
7526 for (--fcp_eqidx; fcp_eqidx >= 0; fcp_eqidx--)
7527 lpfc_eq_destroy(phba, phba->sli4_hba.hba_eq[fcp_eqidx]);
7528out_error:
7529 return rc;
7530}
7531
7532
7533
7534
7535
7536
7537
7538
7539
7540
7541
7542
7543
7544void
7545lpfc_sli4_queue_unset(struct lpfc_hba *phba)
7546{
7547 int fcp_qidx;
7548
7549
7550 lpfc_mq_destroy(phba, phba->sli4_hba.mbx_wq);
7551
7552 lpfc_wq_destroy(phba, phba->sli4_hba.els_wq);
7553
7554 lpfc_rq_destroy(phba, phba->sli4_hba.hdr_rq, phba->sli4_hba.dat_rq);
7555
7556 if (phba->sli4_hba.fcp_wq) {
7557 for (fcp_qidx = 0; fcp_qidx < phba->cfg_fcp_io_channel;
7558 fcp_qidx++)
7559 lpfc_wq_destroy(phba, phba->sli4_hba.fcp_wq[fcp_qidx]);
7560 }
7561
7562 lpfc_cq_destroy(phba, phba->sli4_hba.mbx_cq);
7563
7564 lpfc_cq_destroy(phba, phba->sli4_hba.els_cq);
7565
7566 if (phba->sli4_hba.fcp_cq) {
7567 for (fcp_qidx = 0; fcp_qidx < phba->cfg_fcp_io_channel;
7568 fcp_qidx++)
7569 lpfc_cq_destroy(phba, phba->sli4_hba.fcp_cq[fcp_qidx]);
7570 }
7571
7572 if (phba->sli4_hba.hba_eq) {
7573 for (fcp_qidx = 0; fcp_qidx < phba->cfg_fcp_io_channel;
7574 fcp_qidx++)
7575 lpfc_eq_destroy(phba, phba->sli4_hba.hba_eq[fcp_qidx]);
7576 }
7577}
7578
7579
7580
7581
7582
7583
7584
7585
7586
7587
7588
7589
7590
7591
7592
7593
7594
7595static int
7596lpfc_sli4_cq_event_pool_create(struct lpfc_hba *phba)
7597{
7598 struct lpfc_cq_event *cq_event;
7599 int i;
7600
7601 for (i = 0; i < (4 * phba->sli4_hba.cq_ecount); i++) {
7602 cq_event = kmalloc(sizeof(struct lpfc_cq_event), GFP_KERNEL);
7603 if (!cq_event)
7604 goto out_pool_create_fail;
7605 list_add_tail(&cq_event->list,
7606 &phba->sli4_hba.sp_cqe_event_pool);
7607 }
7608 return 0;
7609
7610out_pool_create_fail:
7611 lpfc_sli4_cq_event_pool_destroy(phba);
7612 return -ENOMEM;
7613}
7614
7615
7616
7617
7618
7619
7620
7621
7622
7623
7624
7625static void
7626lpfc_sli4_cq_event_pool_destroy(struct lpfc_hba *phba)
7627{
7628 struct lpfc_cq_event *cq_event, *next_cq_event;
7629
7630 list_for_each_entry_safe(cq_event, next_cq_event,
7631 &phba->sli4_hba.sp_cqe_event_pool, list) {
7632 list_del(&cq_event->list);
7633 kfree(cq_event);
7634 }
7635}
7636
7637
7638
7639
7640
7641
7642
7643
7644
7645
7646
7647struct lpfc_cq_event *
7648__lpfc_sli4_cq_event_alloc(struct lpfc_hba *phba)
7649{
7650 struct lpfc_cq_event *cq_event = NULL;
7651
7652 list_remove_head(&phba->sli4_hba.sp_cqe_event_pool, cq_event,
7653 struct lpfc_cq_event, list);
7654 return cq_event;
7655}
7656
7657
7658
7659
7660
7661
7662
7663
7664
7665
7666
7667struct lpfc_cq_event *
7668lpfc_sli4_cq_event_alloc(struct lpfc_hba *phba)
7669{
7670 struct lpfc_cq_event *cq_event;
7671 unsigned long iflags;
7672
7673 spin_lock_irqsave(&phba->hbalock, iflags);
7674 cq_event = __lpfc_sli4_cq_event_alloc(phba);
7675 spin_unlock_irqrestore(&phba->hbalock, iflags);
7676 return cq_event;
7677}
7678
7679
7680
7681
7682
7683
7684
7685
7686
7687void
7688__lpfc_sli4_cq_event_release(struct lpfc_hba *phba,
7689 struct lpfc_cq_event *cq_event)
7690{
7691 list_add_tail(&cq_event->list, &phba->sli4_hba.sp_cqe_event_pool);
7692}
7693
7694
7695
7696
7697
7698
7699
7700
7701
7702void
7703lpfc_sli4_cq_event_release(struct lpfc_hba *phba,
7704 struct lpfc_cq_event *cq_event)
7705{
7706 unsigned long iflags;
7707 spin_lock_irqsave(&phba->hbalock, iflags);
7708 __lpfc_sli4_cq_event_release(phba, cq_event);
7709 spin_unlock_irqrestore(&phba->hbalock, iflags);
7710}
7711
7712
7713
7714
7715
7716
7717
7718
7719static void
7720lpfc_sli4_cq_event_release_all(struct lpfc_hba *phba)
7721{
7722 LIST_HEAD(cqelist);
7723 struct lpfc_cq_event *cqe;
7724 unsigned long iflags;
7725
7726
7727 spin_lock_irqsave(&phba->hbalock, iflags);
7728
7729 list_splice_init(&phba->sli4_hba.sp_fcp_xri_aborted_work_queue,
7730 &cqelist);
7731
7732 list_splice_init(&phba->sli4_hba.sp_els_xri_aborted_work_queue,
7733 &cqelist);
7734
7735 list_splice_init(&phba->sli4_hba.sp_asynce_work_queue,
7736 &cqelist);
7737 spin_unlock_irqrestore(&phba->hbalock, iflags);
7738
7739 while (!list_empty(&cqelist)) {
7740 list_remove_head(&cqelist, cqe, struct lpfc_cq_event, list);
7741 lpfc_sli4_cq_event_release(phba, cqe);
7742 }
7743}
7744
7745
7746
7747
7748
7749
7750
7751
7752
7753
7754
7755
7756
7757int
7758lpfc_pci_function_reset(struct lpfc_hba *phba)
7759{
7760 LPFC_MBOXQ_t *mboxq;
7761 uint32_t rc = 0, if_type;
7762 uint32_t shdr_status, shdr_add_status;
7763 uint32_t rdy_chk, num_resets = 0, reset_again = 0;
7764 union lpfc_sli4_cfg_shdr *shdr;
7765 struct lpfc_register reg_data;
7766 uint16_t devid;
7767
7768 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
7769 switch (if_type) {
7770 case LPFC_SLI_INTF_IF_TYPE_0:
7771 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
7772 GFP_KERNEL);
7773 if (!mboxq) {
7774 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7775 "0494 Unable to allocate memory for "
7776 "issuing SLI_FUNCTION_RESET mailbox "
7777 "command\n");
7778 return -ENOMEM;
7779 }
7780
7781
7782 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
7783 LPFC_MBOX_OPCODE_FUNCTION_RESET, 0,
7784 LPFC_SLI4_MBX_EMBED);
7785 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
7786 shdr = (union lpfc_sli4_cfg_shdr *)
7787 &mboxq->u.mqe.un.sli4_config.header.cfg_shdr;
7788 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
7789 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status,
7790 &shdr->response);
7791 if (rc != MBX_TIMEOUT)
7792 mempool_free(mboxq, phba->mbox_mem_pool);
7793 if (shdr_status || shdr_add_status || rc) {
7794 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7795 "0495 SLI_FUNCTION_RESET mailbox "
7796 "failed with status x%x add_status x%x,"
7797 " mbx status x%x\n",
7798 shdr_status, shdr_add_status, rc);
7799 rc = -ENXIO;
7800 }
7801 break;
7802 case LPFC_SLI_INTF_IF_TYPE_2:
7803 for (num_resets = 0;
7804 num_resets < MAX_IF_TYPE_2_RESETS;
7805 num_resets++) {
7806 reg_data.word0 = 0;
7807 bf_set(lpfc_sliport_ctrl_end, ®_data,
7808 LPFC_SLIPORT_LITTLE_ENDIAN);
7809 bf_set(lpfc_sliport_ctrl_ip, ®_data,
7810 LPFC_SLIPORT_INIT_PORT);
7811 writel(reg_data.word0, phba->sli4_hba.u.if_type2.
7812 CTRLregaddr);
7813
7814 pci_read_config_word(phba->pcidev,
7815 PCI_DEVICE_ID, &devid);
7816
7817
7818
7819
7820
7821
7822 for (rdy_chk = 0; rdy_chk < 1000; rdy_chk++) {
7823 msleep(10);
7824 if (lpfc_readl(phba->sli4_hba.u.if_type2.
7825 STATUSregaddr, ®_data.word0)) {
7826 rc = -ENODEV;
7827 goto out;
7828 }
7829 if (bf_get(lpfc_sliport_status_rn, ®_data))
7830 reset_again++;
7831 if (bf_get(lpfc_sliport_status_rdy, ®_data))
7832 break;
7833 }
7834
7835
7836
7837
7838
7839 if (reset_again && (rdy_chk < 1000)) {
7840 msleep(10);
7841 reset_again = 0;
7842 continue;
7843 }
7844
7845
7846 if ((bf_get(lpfc_sliport_status_err, ®_data)) ||
7847 (rdy_chk >= 1000)) {
7848 phba->work_status[0] = readl(
7849 phba->sli4_hba.u.if_type2.ERR1regaddr);
7850 phba->work_status[1] = readl(
7851 phba->sli4_hba.u.if_type2.ERR2regaddr);
7852 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7853 "2890 Port error detected during port "
7854 "reset(%d): wait_tmo:%d ms, "
7855 "port status reg 0x%x, "
7856 "error 1=0x%x, error 2=0x%x\n",
7857 num_resets, rdy_chk*10,
7858 reg_data.word0,
7859 phba->work_status[0],
7860 phba->work_status[1]);
7861 rc = -ENODEV;
7862 }
7863
7864
7865
7866
7867
7868 if (rdy_chk < 1000)
7869 break;
7870 }
7871
7872 msleep(100);
7873 break;
7874 case LPFC_SLI_INTF_IF_TYPE_1:
7875 default:
7876 break;
7877 }
7878
7879out:
7880
7881 if (num_resets >= MAX_IF_TYPE_2_RESETS) {
7882 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7883 "3317 HBA not functional: IP Reset Failed "
7884 "after (%d) retries, try: "
7885 "echo fw_reset > board_mode\n", num_resets);
7886 rc = -ENODEV;
7887 }
7888
7889 return rc;
7890}
7891
7892
7893
7894
7895
7896
7897
7898
7899
7900
7901
7902
7903static int
7904lpfc_sli4_pci_mem_setup(struct lpfc_hba *phba)
7905{
7906 struct pci_dev *pdev;
7907 unsigned long bar0map_len, bar1map_len, bar2map_len;
7908 int error = -ENODEV;
7909 uint32_t if_type;
7910
7911
7912 if (!phba->pcidev)
7913 return error;
7914 else
7915 pdev = phba->pcidev;
7916
7917
7918 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0
7919 || pci_set_consistent_dma_mask(pdev,DMA_BIT_MASK(64)) != 0) {
7920 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0
7921 || pci_set_consistent_dma_mask(pdev,DMA_BIT_MASK(32)) != 0) {
7922 return error;
7923 }
7924 }
7925
7926
7927
7928
7929
7930 if (pci_read_config_dword(pdev, LPFC_SLI_INTF,
7931 &phba->sli4_hba.sli_intf.word0)) {
7932 return error;
7933 }
7934
7935
7936 if (bf_get(lpfc_sli_intf_valid, &phba->sli4_hba.sli_intf) !=
7937 LPFC_SLI_INTF_VALID) {
7938 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7939 "2894 SLI_INTF reg contents invalid "
7940 "sli_intf reg 0x%x\n",
7941 phba->sli4_hba.sli_intf.word0);
7942 return error;
7943 }
7944
7945 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
7946
7947
7948
7949
7950
7951
7952 if (pci_resource_start(pdev, 0)) {
7953 phba->pci_bar0_map = pci_resource_start(pdev, 0);
7954 bar0map_len = pci_resource_len(pdev, 0);
7955
7956
7957
7958
7959
7960 phba->sli4_hba.conf_regs_memmap_p =
7961 ioremap(phba->pci_bar0_map, bar0map_len);
7962 if (!phba->sli4_hba.conf_regs_memmap_p) {
7963 dev_printk(KERN_ERR, &pdev->dev,
7964 "ioremap failed for SLI4 PCI config "
7965 "registers.\n");
7966 goto out;
7967 }
7968
7969 lpfc_sli4_bar0_register_memmap(phba, if_type);
7970 } else {
7971 phba->pci_bar0_map = pci_resource_start(pdev, 1);
7972 bar0map_len = pci_resource_len(pdev, 1);
7973 if (if_type == LPFC_SLI_INTF_IF_TYPE_2) {
7974 dev_printk(KERN_ERR, &pdev->dev,
7975 "FATAL - No BAR0 mapping for SLI4, if_type 2\n");
7976 goto out;
7977 }
7978 phba->sli4_hba.conf_regs_memmap_p =
7979 ioremap(phba->pci_bar0_map, bar0map_len);
7980 if (!phba->sli4_hba.conf_regs_memmap_p) {
7981 dev_printk(KERN_ERR, &pdev->dev,
7982 "ioremap failed for SLI4 PCI config "
7983 "registers.\n");
7984 goto out;
7985 }
7986 lpfc_sli4_bar0_register_memmap(phba, if_type);
7987 }
7988
7989 if ((if_type == LPFC_SLI_INTF_IF_TYPE_0) &&
7990 (pci_resource_start(pdev, 2))) {
7991
7992
7993
7994
7995 phba->pci_bar1_map = pci_resource_start(pdev, 2);
7996 bar1map_len = pci_resource_len(pdev, 2);
7997 phba->sli4_hba.ctrl_regs_memmap_p =
7998 ioremap(phba->pci_bar1_map, bar1map_len);
7999 if (!phba->sli4_hba.ctrl_regs_memmap_p) {
8000 dev_printk(KERN_ERR, &pdev->dev,
8001 "ioremap failed for SLI4 HBA control registers.\n");
8002 goto out_iounmap_conf;
8003 }
8004 lpfc_sli4_bar1_register_memmap(phba);
8005 }
8006
8007 if ((if_type == LPFC_SLI_INTF_IF_TYPE_0) &&
8008 (pci_resource_start(pdev, 4))) {
8009
8010
8011
8012
8013 phba->pci_bar2_map = pci_resource_start(pdev, 4);
8014 bar2map_len = pci_resource_len(pdev, 4);
8015 phba->sli4_hba.drbl_regs_memmap_p =
8016 ioremap(phba->pci_bar2_map, bar2map_len);
8017 if (!phba->sli4_hba.drbl_regs_memmap_p) {
8018 dev_printk(KERN_ERR, &pdev->dev,
8019 "ioremap failed for SLI4 HBA doorbell registers.\n");
8020 goto out_iounmap_ctrl;
8021 }
8022 error = lpfc_sli4_bar2_register_memmap(phba, LPFC_VF0);
8023 if (error)
8024 goto out_iounmap_all;
8025 }
8026
8027 return 0;
8028
8029out_iounmap_all:
8030 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
8031out_iounmap_ctrl:
8032 iounmap(phba->sli4_hba.ctrl_regs_memmap_p);
8033out_iounmap_conf:
8034 iounmap(phba->sli4_hba.conf_regs_memmap_p);
8035out:
8036 return error;
8037}
8038
8039
8040
8041
8042
8043
8044
8045
8046static void
8047lpfc_sli4_pci_mem_unset(struct lpfc_hba *phba)
8048{
8049 uint32_t if_type;
8050 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
8051
8052 switch (if_type) {
8053 case LPFC_SLI_INTF_IF_TYPE_0:
8054 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
8055 iounmap(phba->sli4_hba.ctrl_regs_memmap_p);
8056 iounmap(phba->sli4_hba.conf_regs_memmap_p);
8057 break;
8058 case LPFC_SLI_INTF_IF_TYPE_2:
8059 iounmap(phba->sli4_hba.conf_regs_memmap_p);
8060 break;
8061 case LPFC_SLI_INTF_IF_TYPE_1:
8062 default:
8063 dev_printk(KERN_ERR, &phba->pcidev->dev,
8064 "FATAL - unsupported SLI4 interface type - %d\n",
8065 if_type);
8066 break;
8067 }
8068}
8069
8070
8071
8072
8073
8074
8075
8076
8077
8078
8079
8080
8081
8082
8083
8084
8085
8086
8087
8088
8089
8090static int
8091lpfc_sli_enable_msix(struct lpfc_hba *phba)
8092{
8093 int rc, i;
8094 LPFC_MBOXQ_t *pmb;
8095
8096
8097 for (i = 0; i < LPFC_MSIX_VECTORS; i++)
8098 phba->msix_entries[i].entry = i;
8099
8100
8101 rc = pci_enable_msix(phba->pcidev, phba->msix_entries,
8102 ARRAY_SIZE(phba->msix_entries));
8103 if (rc) {
8104 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8105 "0420 PCI enable MSI-X failed (%d)\n", rc);
8106 goto msi_fail_out;
8107 }
8108 for (i = 0; i < LPFC_MSIX_VECTORS; i++)
8109 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8110 "0477 MSI-X entry[%d]: vector=x%x "
8111 "message=%d\n", i,
8112 phba->msix_entries[i].vector,
8113 phba->msix_entries[i].entry);
8114
8115
8116
8117
8118
8119 rc = request_irq(phba->msix_entries[0].vector,
8120 &lpfc_sli_sp_intr_handler, IRQF_SHARED,
8121 LPFC_SP_DRIVER_HANDLER_NAME, phba);
8122 if (rc) {
8123 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
8124 "0421 MSI-X slow-path request_irq failed "
8125 "(%d)\n", rc);
8126 goto msi_fail_out;
8127 }
8128
8129
8130 rc = request_irq(phba->msix_entries[1].vector,
8131 &lpfc_sli_fp_intr_handler, IRQF_SHARED,
8132 LPFC_FP_DRIVER_HANDLER_NAME, phba);
8133
8134 if (rc) {
8135 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
8136 "0429 MSI-X fast-path request_irq failed "
8137 "(%d)\n", rc);
8138 goto irq_fail_out;
8139 }
8140
8141
8142
8143
8144 pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
8145
8146 if (!pmb) {
8147 rc = -ENOMEM;
8148 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8149 "0474 Unable to allocate memory for issuing "
8150 "MBOX_CONFIG_MSI command\n");
8151 goto mem_fail_out;
8152 }
8153 rc = lpfc_config_msi(phba, pmb);
8154 if (rc)
8155 goto mbx_fail_out;
8156 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
8157 if (rc != MBX_SUCCESS) {
8158 lpfc_printf_log(phba, KERN_WARNING, LOG_MBOX,
8159 "0351 Config MSI mailbox command failed, "
8160 "mbxCmd x%x, mbxStatus x%x\n",
8161 pmb->u.mb.mbxCommand, pmb->u.mb.mbxStatus);
8162 goto mbx_fail_out;
8163 }
8164
8165
8166 mempool_free(pmb, phba->mbox_mem_pool);
8167 return rc;
8168
8169mbx_fail_out:
8170
8171 mempool_free(pmb, phba->mbox_mem_pool);
8172
8173mem_fail_out:
8174
8175 free_irq(phba->msix_entries[1].vector, phba);
8176
8177irq_fail_out:
8178
8179 free_irq(phba->msix_entries[0].vector, phba);
8180
8181msi_fail_out:
8182
8183 pci_disable_msix(phba->pcidev);
8184 return rc;
8185}
8186
8187
8188
8189
8190
8191
8192
8193
8194static void
8195lpfc_sli_disable_msix(struct lpfc_hba *phba)
8196{
8197 int i;
8198
8199
8200 for (i = 0; i < LPFC_MSIX_VECTORS; i++)
8201 free_irq(phba->msix_entries[i].vector, phba);
8202
8203 pci_disable_msix(phba->pcidev);
8204
8205 return;
8206}
8207
8208
8209
8210
8211
8212
8213
8214
8215
8216
8217
8218
8219
8220
8221
8222static int
8223lpfc_sli_enable_msi(struct lpfc_hba *phba)
8224{
8225 int rc;
8226
8227 rc = pci_enable_msi(phba->pcidev);
8228 if (!rc)
8229 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8230 "0462 PCI enable MSI mode success.\n");
8231 else {
8232 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8233 "0471 PCI enable MSI mode failed (%d)\n", rc);
8234 return rc;
8235 }
8236
8237 rc = request_irq(phba->pcidev->irq, lpfc_sli_intr_handler,
8238 IRQF_SHARED, LPFC_DRIVER_NAME, phba);
8239 if (rc) {
8240 pci_disable_msi(phba->pcidev);
8241 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
8242 "0478 MSI request_irq failed (%d)\n", rc);
8243 }
8244 return rc;
8245}
8246
8247
8248
8249
8250
8251
8252
8253
8254
8255
8256
8257static void
8258lpfc_sli_disable_msi(struct lpfc_hba *phba)
8259{
8260 free_irq(phba->pcidev->irq, phba);
8261 pci_disable_msi(phba->pcidev);
8262 return;
8263}
8264
8265
8266
8267
8268
8269
8270
8271
8272
8273
8274
8275
8276
8277
8278
8279
8280
8281static uint32_t
8282lpfc_sli_enable_intr(struct lpfc_hba *phba, uint32_t cfg_mode)
8283{
8284 uint32_t intr_mode = LPFC_INTR_ERROR;
8285 int retval;
8286
8287 if (cfg_mode == 2) {
8288
8289 retval = lpfc_sli_config_port(phba, LPFC_SLI_REV3);
8290 if (!retval) {
8291
8292 retval = lpfc_sli_enable_msix(phba);
8293 if (!retval) {
8294
8295 phba->intr_type = MSIX;
8296 intr_mode = 2;
8297 }
8298 }
8299 }
8300
8301
8302 if (cfg_mode >= 1 && phba->intr_type == NONE) {
8303 retval = lpfc_sli_enable_msi(phba);
8304 if (!retval) {
8305
8306 phba->intr_type = MSI;
8307 intr_mode = 1;
8308 }
8309 }
8310
8311
8312 if (phba->intr_type == NONE) {
8313 retval = request_irq(phba->pcidev->irq, lpfc_sli_intr_handler,
8314 IRQF_SHARED, LPFC_DRIVER_NAME, phba);
8315 if (!retval) {
8316
8317 phba->intr_type = INTx;
8318 intr_mode = 0;
8319 }
8320 }
8321 return intr_mode;
8322}
8323
8324
8325
8326
8327
8328
8329
8330
8331
8332
8333static void
8334lpfc_sli_disable_intr(struct lpfc_hba *phba)
8335{
8336
8337 if (phba->intr_type == MSIX)
8338 lpfc_sli_disable_msix(phba);
8339 else if (phba->intr_type == MSI)
8340 lpfc_sli_disable_msi(phba);
8341 else if (phba->intr_type == INTx)
8342 free_irq(phba->pcidev->irq, phba);
8343
8344
8345 phba->intr_type = NONE;
8346 phba->sli.slistat.sli_intr = 0;
8347
8348 return;
8349}
8350
8351
8352
8353
8354
8355
8356
8357static int
8358lpfc_find_next_cpu(struct lpfc_hba *phba, uint32_t phys_id)
8359{
8360 struct lpfc_vector_map_info *cpup;
8361 int cpu;
8362
8363 cpup = phba->sli4_hba.cpu_map;
8364 for (cpu = 0; cpu < phba->sli4_hba.num_present_cpu; cpu++) {
8365
8366 if (cpu_online(cpu)) {
8367 if ((cpup->irq == LPFC_VECTOR_MAP_EMPTY) &&
8368 (lpfc_used_cpu[cpu] == LPFC_VECTOR_MAP_EMPTY) &&
8369 (cpup->phys_id == phys_id)) {
8370 return cpu;
8371 }
8372 }
8373 cpup++;
8374 }
8375
8376
8377
8378
8379
8380
8381
8382 for (cpu = 0; cpu < phba->sli4_hba.num_present_cpu; cpu++) {
8383 if (lpfc_used_cpu[cpu] == phys_id)
8384 lpfc_used_cpu[cpu] = LPFC_VECTOR_MAP_EMPTY;
8385 }
8386
8387 cpup = phba->sli4_hba.cpu_map;
8388 for (cpu = 0; cpu < phba->sli4_hba.num_present_cpu; cpu++) {
8389
8390 if (cpu_online(cpu)) {
8391 if ((cpup->irq == LPFC_VECTOR_MAP_EMPTY) &&
8392 (cpup->phys_id == phys_id)) {
8393 return cpu;
8394 }
8395 }
8396 cpup++;
8397 }
8398 return LPFC_VECTOR_MAP_EMPTY;
8399}
8400
8401
8402
8403
8404
8405
8406
8407
8408
8409
8410
8411static int
8412lpfc_sli4_set_affinity(struct lpfc_hba *phba, int vectors)
8413{
8414 int i, idx, saved_chann, used_chann, cpu, phys_id;
8415 int max_phys_id, num_io_channel, first_cpu;
8416 struct lpfc_vector_map_info *cpup;
8417#ifdef CONFIG_X86
8418 struct cpuinfo_x86 *cpuinfo;
8419#endif
8420 struct cpumask *mask;
8421 uint8_t chann[LPFC_FCP_IO_CHAN_MAX+1];
8422
8423
8424 if (!phba->cfg_fcp_cpu_map)
8425 return 1;
8426
8427
8428 memset(phba->sli4_hba.cpu_map, 0xff,
8429 (sizeof(struct lpfc_vector_map_info) *
8430 phba->sli4_hba.num_present_cpu));
8431
8432 max_phys_id = 0;
8433 phys_id = 0;
8434 num_io_channel = 0;
8435 first_cpu = LPFC_VECTOR_MAP_EMPTY;
8436
8437
8438 cpup = phba->sli4_hba.cpu_map;
8439 for (cpu = 0; cpu < phba->sli4_hba.num_present_cpu; cpu++) {
8440#ifdef CONFIG_X86
8441 cpuinfo = &cpu_data(cpu);
8442 cpup->phys_id = cpuinfo->phys_proc_id;
8443 cpup->core_id = cpuinfo->cpu_core_id;
8444#else
8445
8446 cpup->phys_id = 0;
8447 cpup->core_id = 0;
8448#endif
8449
8450 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8451 "3328 CPU physid %d coreid %d\n",
8452 cpup->phys_id, cpup->core_id);
8453
8454 if (cpup->phys_id > max_phys_id)
8455 max_phys_id = cpup->phys_id;
8456 cpup++;
8457 }
8458
8459
8460 for (idx = 0; idx < vectors; idx++) {
8461 cpup = phba->sli4_hba.cpu_map;
8462 cpu = lpfc_find_next_cpu(phba, phys_id);
8463 if (cpu == LPFC_VECTOR_MAP_EMPTY) {
8464
8465
8466 for (i = 1; i < max_phys_id; i++) {
8467 phys_id++;
8468 if (phys_id > max_phys_id)
8469 phys_id = 0;
8470 cpu = lpfc_find_next_cpu(phba, phys_id);
8471 if (cpu == LPFC_VECTOR_MAP_EMPTY)
8472 continue;
8473 goto found;
8474 }
8475
8476 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8477 "3329 Cannot set affinity:"
8478 "Error mapping vector %d (%d)\n",
8479 idx, vectors);
8480 return 0;
8481 }
8482found:
8483 cpup += cpu;
8484 if (phba->cfg_fcp_cpu_map == LPFC_DRIVER_CPU_MAP)
8485 lpfc_used_cpu[cpu] = phys_id;
8486
8487
8488 cpup->irq = phba->sli4_hba.msix_entries[idx].vector;
8489
8490
8491 cpup->channel_id = idx;
8492 num_io_channel++;
8493
8494 if (first_cpu == LPFC_VECTOR_MAP_EMPTY)
8495 first_cpu = cpu;
8496
8497
8498 mask = &cpup->maskbits;
8499 cpumask_clear(mask);
8500 cpumask_set_cpu(cpu, mask);
8501 i = irq_set_affinity_hint(phba->sli4_hba.msix_entries[idx].
8502 vector, mask);
8503
8504 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8505 "3330 Set Affinity: CPU %d channel %d "
8506 "irq %d (%x)\n",
8507 cpu, cpup->channel_id,
8508 phba->sli4_hba.msix_entries[idx].vector, i);
8509
8510
8511 phys_id++;
8512 if (phys_id > max_phys_id)
8513 phys_id = 0;
8514 }
8515
8516
8517
8518
8519
8520
8521
8522
8523 for (i = 0; i <= max_phys_id; i++) {
8524
8525
8526
8527
8528
8529 for (idx = 0; idx < phba->cfg_fcp_io_channel; idx++)
8530 chann[idx] = idx;
8531
8532 saved_chann = 0;
8533 used_chann = 0;
8534
8535
8536
8537
8538
8539
8540 cpup = phba->sli4_hba.cpu_map;
8541 cpu = first_cpu;
8542 cpup += cpu;
8543 for (idx = 0; idx < phba->sli4_hba.num_present_cpu;
8544 idx++) {
8545 if (cpup->phys_id == i) {
8546
8547
8548
8549
8550 if (cpup->irq != LPFC_VECTOR_MAP_EMPTY) {
8551 chann[saved_chann] =
8552 cpup->channel_id;
8553 saved_chann++;
8554 goto out;
8555 }
8556
8557
8558 if (saved_chann == 0)
8559 saved_chann =
8560 phba->cfg_fcp_io_channel;
8561
8562
8563 cpup->channel_id = chann[used_chann];
8564 num_io_channel++;
8565 used_chann++;
8566 if (used_chann == saved_chann)
8567 used_chann = 0;
8568
8569 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8570 "3331 Set IO_CHANN "
8571 "CPU %d channel %d\n",
8572 idx, cpup->channel_id);
8573 }
8574out:
8575 cpu++;
8576 if (cpu >= phba->sli4_hba.num_present_cpu) {
8577 cpup = phba->sli4_hba.cpu_map;
8578 cpu = 0;
8579 } else {
8580 cpup++;
8581 }
8582 }
8583 }
8584
8585 if (phba->sli4_hba.num_online_cpu != phba->sli4_hba.num_present_cpu) {
8586 cpup = phba->sli4_hba.cpu_map;
8587 for (idx = 0; idx < phba->sli4_hba.num_present_cpu; idx++) {
8588 if (cpup->channel_id == LPFC_VECTOR_MAP_EMPTY) {
8589 cpup->channel_id = 0;
8590 num_io_channel++;
8591
8592 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8593 "3332 Assign IO_CHANN "
8594 "CPU %d channel %d\n",
8595 idx, cpup->channel_id);
8596 }
8597 cpup++;
8598 }
8599 }
8600
8601
8602 if (num_io_channel != phba->sli4_hba.num_present_cpu)
8603 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8604 "3333 Set affinity mismatch:"
8605 "%d chann != %d cpus: %d vactors\n",
8606 num_io_channel, phba->sli4_hba.num_present_cpu,
8607 vectors);
8608
8609 phba->cfg_fcp_io_sched = LPFC_FCP_SCHED_BY_CPU;
8610 return 1;
8611}
8612
8613
8614
8615
8616
8617
8618
8619
8620
8621
8622
8623
8624
8625
8626
8627
8628
8629
8630
8631
8632
8633
8634static int
8635lpfc_sli4_enable_msix(struct lpfc_hba *phba)
8636{
8637 int vectors, rc, index;
8638
8639
8640 for (index = 0; index < phba->cfg_fcp_io_channel; index++)
8641 phba->sli4_hba.msix_entries[index].entry = index;
8642
8643
8644 vectors = phba->cfg_fcp_io_channel;
8645enable_msix_vectors:
8646 rc = pci_enable_msix(phba->pcidev, phba->sli4_hba.msix_entries,
8647 vectors);
8648 if (rc > 1) {
8649 vectors = rc;
8650 goto enable_msix_vectors;
8651 } else if (rc) {
8652 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8653 "0484 PCI enable MSI-X failed (%d)\n", rc);
8654 goto msi_fail_out;
8655 }
8656
8657
8658 for (index = 0; index < vectors; index++)
8659 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8660 "0489 MSI-X entry[%d]: vector=x%x "
8661 "message=%d\n", index,
8662 phba->sli4_hba.msix_entries[index].vector,
8663 phba->sli4_hba.msix_entries[index].entry);
8664
8665
8666 for (index = 0; index < vectors; index++) {
8667 memset(&phba->sli4_hba.handler_name[index], 0, 16);
8668 sprintf((char *)&phba->sli4_hba.handler_name[index],
8669 LPFC_DRIVER_HANDLER_NAME"%d", index);
8670
8671 phba->sli4_hba.fcp_eq_hdl[index].idx = index;
8672 phba->sli4_hba.fcp_eq_hdl[index].phba = phba;
8673 atomic_set(&phba->sli4_hba.fcp_eq_hdl[index].fcp_eq_in_use, 1);
8674 rc = request_irq(phba->sli4_hba.msix_entries[index].vector,
8675 &lpfc_sli4_hba_intr_handler, IRQF_SHARED,
8676 (char *)&phba->sli4_hba.handler_name[index],
8677 &phba->sli4_hba.fcp_eq_hdl[index]);
8678 if (rc) {
8679 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
8680 "0486 MSI-X fast-path (%d) "
8681 "request_irq failed (%d)\n", index, rc);
8682 goto cfg_fail_out;
8683 }
8684 }
8685
8686 if (vectors != phba->cfg_fcp_io_channel) {
8687 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8688 "3238 Reducing IO channels to match number of "
8689 "MSI-X vectors, requested %d got %d\n",
8690 phba->cfg_fcp_io_channel, vectors);
8691 phba->cfg_fcp_io_channel = vectors;
8692 }
8693
8694 lpfc_sli4_set_affinity(phba, vectors);
8695 return rc;
8696
8697cfg_fail_out:
8698
8699 for (--index; index >= 0; index--)
8700 free_irq(phba->sli4_hba.msix_entries[index].vector,
8701 &phba->sli4_hba.fcp_eq_hdl[index]);
8702
8703msi_fail_out:
8704
8705 pci_disable_msix(phba->pcidev);
8706 return rc;
8707}
8708
8709
8710
8711
8712
8713
8714
8715
8716static void
8717lpfc_sli4_disable_msix(struct lpfc_hba *phba)
8718{
8719 int index;
8720
8721
8722 for (index = 0; index < phba->cfg_fcp_io_channel; index++)
8723 free_irq(phba->sli4_hba.msix_entries[index].vector,
8724 &phba->sli4_hba.fcp_eq_hdl[index]);
8725
8726
8727 pci_disable_msix(phba->pcidev);
8728
8729 return;
8730}
8731
8732
8733
8734
8735
8736
8737
8738
8739
8740
8741
8742
8743
8744
8745
8746static int
8747lpfc_sli4_enable_msi(struct lpfc_hba *phba)
8748{
8749 int rc, index;
8750
8751 rc = pci_enable_msi(phba->pcidev);
8752 if (!rc)
8753 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8754 "0487 PCI enable MSI mode success.\n");
8755 else {
8756 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
8757 "0488 PCI enable MSI mode failed (%d)\n", rc);
8758 return rc;
8759 }
8760
8761 rc = request_irq(phba->pcidev->irq, lpfc_sli4_intr_handler,
8762 IRQF_SHARED, LPFC_DRIVER_NAME, phba);
8763 if (rc) {
8764 pci_disable_msi(phba->pcidev);
8765 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
8766 "0490 MSI request_irq failed (%d)\n", rc);
8767 return rc;
8768 }
8769
8770 for (index = 0; index < phba->cfg_fcp_io_channel; index++) {
8771 phba->sli4_hba.fcp_eq_hdl[index].idx = index;
8772 phba->sli4_hba.fcp_eq_hdl[index].phba = phba;
8773 }
8774
8775 return 0;
8776}
8777
8778
8779
8780
8781
8782
8783
8784
8785
8786
8787
8788static void
8789lpfc_sli4_disable_msi(struct lpfc_hba *phba)
8790{
8791 free_irq(phba->pcidev->irq, phba);
8792 pci_disable_msi(phba->pcidev);
8793 return;
8794}
8795
8796
8797
8798
8799
8800
8801
8802
8803
8804
8805
8806
8807
8808
8809
8810
8811
8812static uint32_t
8813lpfc_sli4_enable_intr(struct lpfc_hba *phba, uint32_t cfg_mode)
8814{
8815 uint32_t intr_mode = LPFC_INTR_ERROR;
8816 int retval, index;
8817
8818 if (cfg_mode == 2) {
8819
8820 retval = 0;
8821 if (!retval) {
8822
8823 retval = lpfc_sli4_enable_msix(phba);
8824 if (!retval) {
8825
8826 phba->intr_type = MSIX;
8827 intr_mode = 2;
8828 }
8829 }
8830 }
8831
8832
8833 if (cfg_mode >= 1 && phba->intr_type == NONE) {
8834 retval = lpfc_sli4_enable_msi(phba);
8835 if (!retval) {
8836
8837 phba->intr_type = MSI;
8838 intr_mode = 1;
8839 }
8840 }
8841
8842
8843 if (phba->intr_type == NONE) {
8844 retval = request_irq(phba->pcidev->irq, lpfc_sli4_intr_handler,
8845 IRQF_SHARED, LPFC_DRIVER_NAME, phba);
8846 if (!retval) {
8847
8848 phba->intr_type = INTx;
8849 intr_mode = 0;
8850 for (index = 0; index < phba->cfg_fcp_io_channel;
8851 index++) {
8852 phba->sli4_hba.fcp_eq_hdl[index].idx = index;
8853 phba->sli4_hba.fcp_eq_hdl[index].phba = phba;
8854 atomic_set(&phba->sli4_hba.fcp_eq_hdl[index].
8855 fcp_eq_in_use, 1);
8856 }
8857 }
8858 }
8859 return intr_mode;
8860}
8861
8862
8863
8864
8865
8866
8867
8868
8869
8870
8871static void
8872lpfc_sli4_disable_intr(struct lpfc_hba *phba)
8873{
8874
8875 if (phba->intr_type == MSIX)
8876 lpfc_sli4_disable_msix(phba);
8877 else if (phba->intr_type == MSI)
8878 lpfc_sli4_disable_msi(phba);
8879 else if (phba->intr_type == INTx)
8880 free_irq(phba->pcidev->irq, phba);
8881
8882
8883 phba->intr_type = NONE;
8884 phba->sli.slistat.sli_intr = 0;
8885
8886 return;
8887}
8888
8889
8890
8891
8892
8893
8894
8895
8896static void
8897lpfc_unset_hba(struct lpfc_hba *phba)
8898{
8899 struct lpfc_vport *vport = phba->pport;
8900 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
8901
8902 spin_lock_irq(shost->host_lock);
8903 vport->load_flag |= FC_UNLOADING;
8904 spin_unlock_irq(shost->host_lock);
8905
8906 kfree(phba->vpi_bmask);
8907 kfree(phba->vpi_ids);
8908
8909 lpfc_stop_hba_timers(phba);
8910
8911 phba->pport->work_port_events = 0;
8912
8913 lpfc_sli_hba_down(phba);
8914
8915 lpfc_sli_brdrestart(phba);
8916
8917 lpfc_sli_disable_intr(phba);
8918
8919 return;
8920}
8921
8922
8923
8924
8925
8926
8927
8928
8929
8930
8931
8932
8933
8934
8935static void
8936lpfc_sli4_xri_exchange_busy_wait(struct lpfc_hba *phba)
8937{
8938 int wait_time = 0;
8939 int fcp_xri_cmpl = list_empty(&phba->sli4_hba.lpfc_abts_scsi_buf_list);
8940 int els_xri_cmpl = list_empty(&phba->sli4_hba.lpfc_abts_els_sgl_list);
8941
8942 while (!fcp_xri_cmpl || !els_xri_cmpl) {
8943 if (wait_time > LPFC_XRI_EXCH_BUSY_WAIT_TMO) {
8944 if (!fcp_xri_cmpl)
8945 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8946 "2877 FCP XRI exchange busy "
8947 "wait time: %d seconds.\n",
8948 wait_time/1000);
8949 if (!els_xri_cmpl)
8950 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8951 "2878 ELS XRI exchange busy "
8952 "wait time: %d seconds.\n",
8953 wait_time/1000);
8954 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T2);
8955 wait_time += LPFC_XRI_EXCH_BUSY_WAIT_T2;
8956 } else {
8957 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T1);
8958 wait_time += LPFC_XRI_EXCH_BUSY_WAIT_T1;
8959 }
8960 fcp_xri_cmpl =
8961 list_empty(&phba->sli4_hba.lpfc_abts_scsi_buf_list);
8962 els_xri_cmpl =
8963 list_empty(&phba->sli4_hba.lpfc_abts_els_sgl_list);
8964 }
8965}
8966
8967
8968
8969
8970
8971
8972
8973
8974
8975
8976
8977static void
8978lpfc_sli4_hba_unset(struct lpfc_hba *phba)
8979{
8980 int wait_cnt = 0;
8981 LPFC_MBOXQ_t *mboxq;
8982 struct pci_dev *pdev = phba->pcidev;
8983
8984 lpfc_stop_hba_timers(phba);
8985 phba->sli4_hba.intr_enable = 0;
8986
8987
8988
8989
8990
8991
8992
8993 spin_lock_irq(&phba->hbalock);
8994 phba->sli.sli_flag |= LPFC_SLI_ASYNC_MBX_BLK;
8995 spin_unlock_irq(&phba->hbalock);
8996
8997 while (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) {
8998 msleep(10);
8999 if (++wait_cnt > LPFC_ACTIVE_MBOX_WAIT_CNT)
9000 break;
9001 }
9002
9003 if (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) {
9004 spin_lock_irq(&phba->hbalock);
9005 mboxq = phba->sli.mbox_active;
9006 mboxq->u.mb.mbxStatus = MBX_NOT_FINISHED;
9007 __lpfc_mbox_cmpl_put(phba, mboxq);
9008 phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
9009 phba->sli.mbox_active = NULL;
9010 spin_unlock_irq(&phba->hbalock);
9011 }
9012
9013
9014 lpfc_sli_hba_iocb_abort(phba);
9015
9016
9017 lpfc_sli4_xri_exchange_busy_wait(phba);
9018
9019
9020 lpfc_sli4_disable_intr(phba);
9021
9022
9023 if (phba->cfg_sriov_nr_virtfn)
9024 pci_disable_sriov(pdev);
9025
9026
9027 kthread_stop(phba->worker_thread);
9028
9029
9030 lpfc_pci_function_reset(phba);
9031 lpfc_sli4_queue_destroy(phba);
9032
9033
9034 phba->pport->work_port_events = 0;
9035}
9036
9037
9038
9039
9040
9041
9042
9043
9044
9045
9046
9047
9048
9049int
9050lpfc_pc_sli4_params_get(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq)
9051{
9052 int rc;
9053 struct lpfc_mqe *mqe;
9054 struct lpfc_pc_sli4_params *sli4_params;
9055 uint32_t mbox_tmo;
9056
9057 rc = 0;
9058 mqe = &mboxq->u.mqe;
9059
9060
9061 lpfc_pc_sli4_params(mboxq);
9062 if (!phba->sli4_hba.intr_enable)
9063 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
9064 else {
9065 mbox_tmo = lpfc_mbox_tmo_val(phba, mboxq);
9066 rc = lpfc_sli_issue_mbox_wait(phba, mboxq, mbox_tmo);
9067 }
9068
9069 if (unlikely(rc))
9070 return 1;
9071
9072 sli4_params = &phba->sli4_hba.pc_sli4_params;
9073 sli4_params->if_type = bf_get(if_type, &mqe->un.sli4_params);
9074 sli4_params->sli_rev = bf_get(sli_rev, &mqe->un.sli4_params);
9075 sli4_params->sli_family = bf_get(sli_family, &mqe->un.sli4_params);
9076 sli4_params->featurelevel_1 = bf_get(featurelevel_1,
9077 &mqe->un.sli4_params);
9078 sli4_params->featurelevel_2 = bf_get(featurelevel_2,
9079 &mqe->un.sli4_params);
9080 sli4_params->proto_types = mqe->un.sli4_params.word3;
9081 sli4_params->sge_supp_len = mqe->un.sli4_params.sge_supp_len;
9082 sli4_params->if_page_sz = bf_get(if_page_sz, &mqe->un.sli4_params);
9083 sli4_params->rq_db_window = bf_get(rq_db_window, &mqe->un.sli4_params);
9084 sli4_params->loopbk_scope = bf_get(loopbk_scope, &mqe->un.sli4_params);
9085 sli4_params->eq_pages_max = bf_get(eq_pages, &mqe->un.sli4_params);
9086 sli4_params->eqe_size = bf_get(eqe_size, &mqe->un.sli4_params);
9087 sli4_params->cq_pages_max = bf_get(cq_pages, &mqe->un.sli4_params);
9088 sli4_params->cqe_size = bf_get(cqe_size, &mqe->un.sli4_params);
9089 sli4_params->mq_pages_max = bf_get(mq_pages, &mqe->un.sli4_params);
9090 sli4_params->mqe_size = bf_get(mqe_size, &mqe->un.sli4_params);
9091 sli4_params->mq_elem_cnt = bf_get(mq_elem_cnt, &mqe->un.sli4_params);
9092 sli4_params->wq_pages_max = bf_get(wq_pages, &mqe->un.sli4_params);
9093 sli4_params->wqe_size = bf_get(wqe_size, &mqe->un.sli4_params);
9094 sli4_params->rq_pages_max = bf_get(rq_pages, &mqe->un.sli4_params);
9095 sli4_params->rqe_size = bf_get(rqe_size, &mqe->un.sli4_params);
9096 sli4_params->hdr_pages_max = bf_get(hdr_pages, &mqe->un.sli4_params);
9097 sli4_params->hdr_size = bf_get(hdr_size, &mqe->un.sli4_params);
9098 sli4_params->hdr_pp_align = bf_get(hdr_pp_align, &mqe->un.sli4_params);
9099 sli4_params->sgl_pages_max = bf_get(sgl_pages, &mqe->un.sli4_params);
9100 sli4_params->sgl_pp_align = bf_get(sgl_pp_align, &mqe->un.sli4_params);
9101
9102
9103 if (sli4_params->sge_supp_len > LPFC_MAX_SGE_SIZE)
9104 sli4_params->sge_supp_len = LPFC_MAX_SGE_SIZE;
9105
9106 return rc;
9107}
9108
9109
9110
9111
9112
9113
9114
9115
9116
9117
9118
9119
9120
9121int
9122lpfc_get_sli4_parameters(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq)
9123{
9124 int rc;
9125 struct lpfc_mqe *mqe = &mboxq->u.mqe;
9126 struct lpfc_pc_sli4_params *sli4_params;
9127 uint32_t mbox_tmo;
9128 int length;
9129 struct lpfc_sli4_parameters *mbx_sli4_parameters;
9130
9131
9132
9133
9134
9135
9136 phba->sli4_hba.rpi_hdrs_in_use = 1;
9137
9138
9139 length = (sizeof(struct lpfc_mbx_get_sli4_parameters) -
9140 sizeof(struct lpfc_sli4_cfg_mhdr));
9141 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
9142 LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS,
9143 length, LPFC_SLI4_MBX_EMBED);
9144 if (!phba->sli4_hba.intr_enable)
9145 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
9146 else {
9147 mbox_tmo = lpfc_mbox_tmo_val(phba, mboxq);
9148 rc = lpfc_sli_issue_mbox_wait(phba, mboxq, mbox_tmo);
9149 }
9150 if (unlikely(rc))
9151 return rc;
9152 sli4_params = &phba->sli4_hba.pc_sli4_params;
9153 mbx_sli4_parameters = &mqe->un.get_sli4_parameters.sli4_parameters;
9154 sli4_params->if_type = bf_get(cfg_if_type, mbx_sli4_parameters);
9155 sli4_params->sli_rev = bf_get(cfg_sli_rev, mbx_sli4_parameters);
9156 sli4_params->sli_family = bf_get(cfg_sli_family, mbx_sli4_parameters);
9157 sli4_params->featurelevel_1 = bf_get(cfg_sli_hint_1,
9158 mbx_sli4_parameters);
9159 sli4_params->featurelevel_2 = bf_get(cfg_sli_hint_2,
9160 mbx_sli4_parameters);
9161 if (bf_get(cfg_phwq, mbx_sli4_parameters))
9162 phba->sli3_options |= LPFC_SLI4_PHWQ_ENABLED;
9163 else
9164 phba->sli3_options &= ~LPFC_SLI4_PHWQ_ENABLED;
9165 sli4_params->sge_supp_len = mbx_sli4_parameters->sge_supp_len;
9166 sli4_params->loopbk_scope = bf_get(loopbk_scope, mbx_sli4_parameters);
9167 sli4_params->cqv = bf_get(cfg_cqv, mbx_sli4_parameters);
9168 sli4_params->mqv = bf_get(cfg_mqv, mbx_sli4_parameters);
9169 sli4_params->wqv = bf_get(cfg_wqv, mbx_sli4_parameters);
9170 sli4_params->rqv = bf_get(cfg_rqv, mbx_sli4_parameters);
9171 sli4_params->sgl_pages_max = bf_get(cfg_sgl_page_cnt,
9172 mbx_sli4_parameters);
9173 sli4_params->sgl_pp_align = bf_get(cfg_sgl_pp_align,
9174 mbx_sli4_parameters);
9175 phba->sli4_hba.extents_in_use = bf_get(cfg_ext, mbx_sli4_parameters);
9176 phba->sli4_hba.rpi_hdrs_in_use = bf_get(cfg_hdrr, mbx_sli4_parameters);
9177
9178
9179 if (sli4_params->sge_supp_len > LPFC_MAX_SGE_SIZE)
9180 sli4_params->sge_supp_len = LPFC_MAX_SGE_SIZE;
9181
9182 return 0;
9183}
9184
9185
9186
9187
9188
9189
9190
9191
9192
9193
9194
9195
9196
9197
9198
9199
9200
9201
9202static int
9203lpfc_pci_probe_one_s3(struct pci_dev *pdev, const struct pci_device_id *pid)
9204{
9205 struct lpfc_hba *phba;
9206 struct lpfc_vport *vport = NULL;
9207 struct Scsi_Host *shost = NULL;
9208 int error;
9209 uint32_t cfg_mode, intr_mode;
9210
9211
9212 phba = lpfc_hba_alloc(pdev);
9213 if (!phba)
9214 return -ENOMEM;
9215
9216
9217 error = lpfc_enable_pci_dev(phba);
9218 if (error)
9219 goto out_free_phba;
9220
9221
9222 error = lpfc_api_table_setup(phba, LPFC_PCI_DEV_LP);
9223 if (error)
9224 goto out_disable_pci_dev;
9225
9226
9227 error = lpfc_sli_pci_mem_setup(phba);
9228 if (error) {
9229 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9230 "1402 Failed to set up pci memory space.\n");
9231 goto out_disable_pci_dev;
9232 }
9233
9234
9235 error = lpfc_setup_driver_resource_phase1(phba);
9236 if (error) {
9237 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9238 "1403 Failed to set up driver resource.\n");
9239 goto out_unset_pci_mem_s3;
9240 }
9241
9242
9243 error = lpfc_sli_driver_resource_setup(phba);
9244 if (error) {
9245 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9246 "1404 Failed to set up driver resource.\n");
9247 goto out_unset_pci_mem_s3;
9248 }
9249
9250
9251 error = lpfc_init_iocb_list(phba, LPFC_IOCB_LIST_CNT);
9252 if (error) {
9253 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9254 "1405 Failed to initialize iocb list.\n");
9255 goto out_unset_driver_resource_s3;
9256 }
9257
9258
9259 error = lpfc_setup_driver_resource_phase2(phba);
9260 if (error) {
9261 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9262 "1406 Failed to set up driver resource.\n");
9263 goto out_free_iocb_list;
9264 }
9265
9266
9267 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
9268
9269
9270 error = lpfc_create_shost(phba);
9271 if (error) {
9272 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9273 "1407 Failed to create scsi host.\n");
9274 goto out_unset_driver_resource;
9275 }
9276
9277
9278 vport = phba->pport;
9279 error = lpfc_alloc_sysfs_attr(vport);
9280 if (error) {
9281 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9282 "1476 Failed to allocate sysfs attr\n");
9283 goto out_destroy_shost;
9284 }
9285
9286 shost = lpfc_shost_from_vport(vport);
9287
9288 cfg_mode = phba->cfg_use_msi;
9289 while (true) {
9290
9291 lpfc_stop_port(phba);
9292
9293 intr_mode = lpfc_sli_enable_intr(phba, cfg_mode);
9294 if (intr_mode == LPFC_INTR_ERROR) {
9295 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9296 "0431 Failed to enable interrupt.\n");
9297 error = -ENODEV;
9298 goto out_free_sysfs_attr;
9299 }
9300
9301 if (lpfc_sli_hba_setup(phba)) {
9302 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9303 "1477 Failed to set up hba\n");
9304 error = -ENODEV;
9305 goto out_remove_device;
9306 }
9307
9308
9309 msleep(50);
9310
9311 if (intr_mode == 0 ||
9312 phba->sli.slistat.sli_intr > LPFC_MSIX_VECTORS) {
9313
9314 phba->intr_mode = intr_mode;
9315 lpfc_log_intr_mode(phba, intr_mode);
9316 break;
9317 } else {
9318 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9319 "0447 Configure interrupt mode (%d) "
9320 "failed active interrupt test.\n",
9321 intr_mode);
9322
9323 lpfc_sli_disable_intr(phba);
9324
9325 cfg_mode = --intr_mode;
9326 }
9327 }
9328
9329
9330 lpfc_post_init_setup(phba);
9331
9332
9333 lpfc_create_static_vport(phba);
9334
9335 return 0;
9336
9337out_remove_device:
9338 lpfc_unset_hba(phba);
9339out_free_sysfs_attr:
9340 lpfc_free_sysfs_attr(vport);
9341out_destroy_shost:
9342 lpfc_destroy_shost(phba);
9343out_unset_driver_resource:
9344 lpfc_unset_driver_resource_phase2(phba);
9345out_free_iocb_list:
9346 lpfc_free_iocb_list(phba);
9347out_unset_driver_resource_s3:
9348 lpfc_sli_driver_resource_unset(phba);
9349out_unset_pci_mem_s3:
9350 lpfc_sli_pci_mem_unset(phba);
9351out_disable_pci_dev:
9352 lpfc_disable_pci_dev(phba);
9353 if (shost)
9354 scsi_host_put(shost);
9355out_free_phba:
9356 lpfc_hba_free(phba);
9357 return error;
9358}
9359
9360
9361
9362
9363
9364
9365
9366
9367
9368
9369static void
9370lpfc_pci_remove_one_s3(struct pci_dev *pdev)
9371{
9372 struct Scsi_Host *shost = pci_get_drvdata(pdev);
9373 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
9374 struct lpfc_vport **vports;
9375 struct lpfc_hba *phba = vport->phba;
9376 int i;
9377 int bars = pci_select_bars(pdev, IORESOURCE_MEM);
9378
9379 spin_lock_irq(&phba->hbalock);
9380 vport->load_flag |= FC_UNLOADING;
9381 spin_unlock_irq(&phba->hbalock);
9382
9383 lpfc_free_sysfs_attr(vport);
9384
9385
9386 vports = lpfc_create_vport_work_array(phba);
9387 if (vports != NULL)
9388 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
9389 if (vports[i]->port_type == LPFC_PHYSICAL_PORT)
9390 continue;
9391 fc_vport_terminate(vports[i]->fc_vport);
9392 }
9393 lpfc_destroy_vport_work_array(phba, vports);
9394
9395
9396 fc_remove_host(shost);
9397 scsi_remove_host(shost);
9398 lpfc_cleanup(vport);
9399
9400
9401
9402
9403
9404
9405
9406
9407 lpfc_sli_hba_down(phba);
9408
9409 kthread_stop(phba->worker_thread);
9410
9411 lpfc_sli_brdrestart(phba);
9412
9413 kfree(phba->vpi_bmask);
9414 kfree(phba->vpi_ids);
9415
9416 lpfc_stop_hba_timers(phba);
9417 spin_lock_irq(&phba->hbalock);
9418 list_del_init(&vport->listentry);
9419 spin_unlock_irq(&phba->hbalock);
9420
9421 lpfc_debugfs_terminate(vport);
9422
9423
9424 if (phba->cfg_sriov_nr_virtfn)
9425 pci_disable_sriov(pdev);
9426
9427
9428 lpfc_sli_disable_intr(phba);
9429
9430 pci_set_drvdata(pdev, NULL);
9431 scsi_host_put(shost);
9432
9433
9434
9435
9436
9437 lpfc_scsi_free(phba);
9438 lpfc_mem_free_all(phba);
9439
9440 dma_free_coherent(&pdev->dev, lpfc_sli_hbq_size(),
9441 phba->hbqslimp.virt, phba->hbqslimp.phys);
9442
9443
9444 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
9445 phba->slim2p.virt, phba->slim2p.phys);
9446
9447
9448 iounmap(phba->ctrl_regs_memmap_p);
9449 iounmap(phba->slim_memmap_p);
9450
9451 lpfc_hba_free(phba);
9452
9453 pci_release_selected_regions(pdev, bars);
9454 pci_disable_device(pdev);
9455}
9456
9457
9458
9459
9460
9461
9462
9463
9464
9465
9466
9467
9468
9469
9470
9471
9472
9473
9474
9475
9476
9477
9478static int
9479lpfc_pci_suspend_one_s3(struct pci_dev *pdev, pm_message_t msg)
9480{
9481 struct Scsi_Host *shost = pci_get_drvdata(pdev);
9482 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
9483
9484 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9485 "0473 PCI device Power Management suspend.\n");
9486
9487
9488 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
9489 lpfc_offline(phba);
9490 kthread_stop(phba->worker_thread);
9491
9492
9493 lpfc_sli_disable_intr(phba);
9494
9495
9496 pci_save_state(pdev);
9497 pci_set_power_state(pdev, PCI_D3hot);
9498
9499 return 0;
9500}
9501
9502
9503
9504
9505
9506
9507
9508
9509
9510
9511
9512
9513
9514
9515
9516
9517
9518
9519
9520
9521static int
9522lpfc_pci_resume_one_s3(struct pci_dev *pdev)
9523{
9524 struct Scsi_Host *shost = pci_get_drvdata(pdev);
9525 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
9526 uint32_t intr_mode;
9527 int error;
9528
9529 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9530 "0452 PCI device Power Management resume.\n");
9531
9532
9533 pci_set_power_state(pdev, PCI_D0);
9534 pci_restore_state(pdev);
9535
9536
9537
9538
9539
9540 pci_save_state(pdev);
9541
9542 if (pdev->is_busmaster)
9543 pci_set_master(pdev);
9544
9545
9546 phba->worker_thread = kthread_run(lpfc_do_work, phba,
9547 "lpfc_worker_%d", phba->brd_no);
9548 if (IS_ERR(phba->worker_thread)) {
9549 error = PTR_ERR(phba->worker_thread);
9550 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9551 "0434 PM resume failed to start worker "
9552 "thread: error=x%x.\n", error);
9553 return error;
9554 }
9555
9556
9557 intr_mode = lpfc_sli_enable_intr(phba, phba->intr_mode);
9558 if (intr_mode == LPFC_INTR_ERROR) {
9559 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9560 "0430 PM resume Failed to enable interrupt\n");
9561 return -EIO;
9562 } else
9563 phba->intr_mode = intr_mode;
9564
9565
9566 lpfc_sli_brdrestart(phba);
9567 lpfc_online(phba);
9568
9569
9570 lpfc_log_intr_mode(phba, phba->intr_mode);
9571
9572 return 0;
9573}
9574
9575
9576
9577
9578
9579
9580
9581
9582static void
9583lpfc_sli_prep_dev_for_recover(struct lpfc_hba *phba)
9584{
9585 struct lpfc_sli *psli = &phba->sli;
9586 struct lpfc_sli_ring *pring;
9587
9588 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9589 "2723 PCI channel I/O abort preparing for recovery\n");
9590
9591
9592
9593
9594
9595 pring = &psli->ring[psli->fcp_ring];
9596 lpfc_sli_abort_iocb_ring(phba, pring);
9597}
9598
9599
9600
9601
9602
9603
9604
9605
9606
9607static void
9608lpfc_sli_prep_dev_for_reset(struct lpfc_hba *phba)
9609{
9610 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9611 "2710 PCI channel disable preparing for reset\n");
9612
9613
9614 lpfc_block_mgmt_io(phba, LPFC_MBX_WAIT);
9615
9616
9617 lpfc_scsi_dev_block(phba);
9618
9619
9620 lpfc_sli_flush_fcp_rings(phba);
9621
9622
9623 lpfc_stop_hba_timers(phba);
9624
9625
9626 lpfc_sli_disable_intr(phba);
9627 pci_disable_device(phba->pcidev);
9628}
9629
9630
9631
9632
9633
9634
9635
9636
9637
9638static void
9639lpfc_sli_prep_dev_for_perm_failure(struct lpfc_hba *phba)
9640{
9641 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9642 "2711 PCI channel permanent disable for failure\n");
9643
9644 lpfc_scsi_dev_block(phba);
9645
9646
9647 lpfc_stop_hba_timers(phba);
9648
9649
9650 lpfc_sli_flush_fcp_rings(phba);
9651}
9652
9653
9654
9655
9656
9657
9658
9659
9660
9661
9662
9663
9664
9665
9666
9667
9668
9669
9670
9671static pci_ers_result_t
9672lpfc_io_error_detected_s3(struct pci_dev *pdev, pci_channel_state_t state)
9673{
9674 struct Scsi_Host *shost = pci_get_drvdata(pdev);
9675 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
9676
9677 switch (state) {
9678 case pci_channel_io_normal:
9679
9680 lpfc_sli_prep_dev_for_recover(phba);
9681 return PCI_ERS_RESULT_CAN_RECOVER;
9682 case pci_channel_io_frozen:
9683
9684 lpfc_sli_prep_dev_for_reset(phba);
9685 return PCI_ERS_RESULT_NEED_RESET;
9686 case pci_channel_io_perm_failure:
9687
9688 lpfc_sli_prep_dev_for_perm_failure(phba);
9689 return PCI_ERS_RESULT_DISCONNECT;
9690 default:
9691
9692 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9693 "0472 Unknown PCI error state: x%x\n", state);
9694 lpfc_sli_prep_dev_for_reset(phba);
9695 return PCI_ERS_RESULT_NEED_RESET;
9696 }
9697}
9698
9699
9700
9701
9702
9703
9704
9705
9706
9707
9708
9709
9710
9711
9712
9713
9714
9715
9716
9717static pci_ers_result_t
9718lpfc_io_slot_reset_s3(struct pci_dev *pdev)
9719{
9720 struct Scsi_Host *shost = pci_get_drvdata(pdev);
9721 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
9722 struct lpfc_sli *psli = &phba->sli;
9723 uint32_t intr_mode;
9724
9725 dev_printk(KERN_INFO, &pdev->dev, "recovering from a slot reset.\n");
9726 if (pci_enable_device_mem(pdev)) {
9727 printk(KERN_ERR "lpfc: Cannot re-enable "
9728 "PCI device after reset.\n");
9729 return PCI_ERS_RESULT_DISCONNECT;
9730 }
9731
9732 pci_restore_state(pdev);
9733
9734
9735
9736
9737
9738 pci_save_state(pdev);
9739
9740 if (pdev->is_busmaster)
9741 pci_set_master(pdev);
9742
9743 spin_lock_irq(&phba->hbalock);
9744 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
9745 spin_unlock_irq(&phba->hbalock);
9746
9747
9748 intr_mode = lpfc_sli_enable_intr(phba, phba->intr_mode);
9749 if (intr_mode == LPFC_INTR_ERROR) {
9750 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9751 "0427 Cannot re-enable interrupt after "
9752 "slot reset.\n");
9753 return PCI_ERS_RESULT_DISCONNECT;
9754 } else
9755 phba->intr_mode = intr_mode;
9756
9757
9758 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
9759 lpfc_offline(phba);
9760 lpfc_sli_brdrestart(phba);
9761
9762
9763 lpfc_log_intr_mode(phba, phba->intr_mode);
9764
9765 return PCI_ERS_RESULT_RECOVERED;
9766}
9767
9768
9769
9770
9771
9772
9773
9774
9775
9776
9777
9778static void
9779lpfc_io_resume_s3(struct pci_dev *pdev)
9780{
9781 struct Scsi_Host *shost = pci_get_drvdata(pdev);
9782 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
9783
9784
9785 lpfc_online(phba);
9786
9787
9788 if (phba->hba_flag & HBA_AER_ENABLED)
9789 pci_cleanup_aer_uncorrect_error_status(pdev);
9790}
9791
9792
9793
9794
9795
9796
9797
9798int
9799lpfc_sli4_get_els_iocb_cnt(struct lpfc_hba *phba)
9800{
9801 int max_xri = phba->sli4_hba.max_cfg_param.max_xri;
9802
9803 if (phba->sli_rev == LPFC_SLI_REV4) {
9804 if (max_xri <= 100)
9805 return 10;
9806 else if (max_xri <= 256)
9807 return 25;
9808 else if (max_xri <= 512)
9809 return 50;
9810 else if (max_xri <= 1024)
9811 return 100;
9812 else if (max_xri <= 1536)
9813 return 150;
9814 else if (max_xri <= 2048)
9815 return 200;
9816 else
9817 return 250;
9818 } else
9819 return 0;
9820}
9821
9822
9823
9824
9825
9826
9827
9828static void
9829lpfc_write_firmware(const struct firmware *fw, void *context)
9830{
9831 struct lpfc_hba *phba = (struct lpfc_hba *)context;
9832 char fwrev[FW_REV_STR_SIZE];
9833 struct lpfc_grp_hdr *image;
9834 struct list_head dma_buffer_list;
9835 int i, rc = 0;
9836 struct lpfc_dmabuf *dmabuf, *next;
9837 uint32_t offset = 0, temp_offset = 0;
9838
9839
9840 if (!fw) {
9841 rc = -ENXIO;
9842 goto out;
9843 }
9844 image = (struct lpfc_grp_hdr *)fw->data;
9845
9846 INIT_LIST_HEAD(&dma_buffer_list);
9847 if ((be32_to_cpu(image->magic_number) != LPFC_GROUP_OJECT_MAGIC_NUM) ||
9848 (bf_get_be32(lpfc_grp_hdr_file_type, image) !=
9849 LPFC_FILE_TYPE_GROUP) ||
9850 (bf_get_be32(lpfc_grp_hdr_id, image) != LPFC_FILE_ID_GROUP) ||
9851 (be32_to_cpu(image->size) != fw->size)) {
9852 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9853 "3022 Invalid FW image found. "
9854 "Magic:%x Type:%x ID:%x\n",
9855 be32_to_cpu(image->magic_number),
9856 bf_get_be32(lpfc_grp_hdr_file_type, image),
9857 bf_get_be32(lpfc_grp_hdr_id, image));
9858 rc = -EINVAL;
9859 goto release_out;
9860 }
9861 lpfc_decode_firmware_rev(phba, fwrev, 1);
9862 if (strncmp(fwrev, image->revision, strnlen(image->revision, 16))) {
9863 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9864 "3023 Updating Firmware, Current Version:%s "
9865 "New Version:%s\n",
9866 fwrev, image->revision);
9867 for (i = 0; i < LPFC_MBX_WR_CONFIG_MAX_BDE; i++) {
9868 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf),
9869 GFP_KERNEL);
9870 if (!dmabuf) {
9871 rc = -ENOMEM;
9872 goto release_out;
9873 }
9874 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev,
9875 SLI4_PAGE_SIZE,
9876 &dmabuf->phys,
9877 GFP_KERNEL);
9878 if (!dmabuf->virt) {
9879 kfree(dmabuf);
9880 rc = -ENOMEM;
9881 goto release_out;
9882 }
9883 list_add_tail(&dmabuf->list, &dma_buffer_list);
9884 }
9885 while (offset < fw->size) {
9886 temp_offset = offset;
9887 list_for_each_entry(dmabuf, &dma_buffer_list, list) {
9888 if (temp_offset + SLI4_PAGE_SIZE > fw->size) {
9889 memcpy(dmabuf->virt,
9890 fw->data + temp_offset,
9891 fw->size - temp_offset);
9892 temp_offset = fw->size;
9893 break;
9894 }
9895 memcpy(dmabuf->virt, fw->data + temp_offset,
9896 SLI4_PAGE_SIZE);
9897 temp_offset += SLI4_PAGE_SIZE;
9898 }
9899 rc = lpfc_wr_object(phba, &dma_buffer_list,
9900 (fw->size - offset), &offset);
9901 if (rc)
9902 goto release_out;
9903 }
9904 rc = offset;
9905 }
9906
9907release_out:
9908 list_for_each_entry_safe(dmabuf, next, &dma_buffer_list, list) {
9909 list_del(&dmabuf->list);
9910 dma_free_coherent(&phba->pcidev->dev, SLI4_PAGE_SIZE,
9911 dmabuf->virt, dmabuf->phys);
9912 kfree(dmabuf);
9913 }
9914 release_firmware(fw);
9915out:
9916 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9917 "3024 Firmware update done: %d.\n", rc);
9918 return;
9919}
9920
9921
9922
9923
9924
9925
9926
9927
9928int
9929lpfc_sli4_request_firmware_update(struct lpfc_hba *phba, uint8_t fw_upgrade)
9930{
9931 uint8_t file_name[ELX_MODEL_NAME_SIZE];
9932 int ret;
9933 const struct firmware *fw;
9934
9935
9936 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) !=
9937 LPFC_SLI_INTF_IF_TYPE_2)
9938 return -EPERM;
9939
9940 snprintf(file_name, ELX_MODEL_NAME_SIZE, "%s.grp", phba->ModelName);
9941
9942 if (fw_upgrade == INT_FW_UPGRADE) {
9943 ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
9944 file_name, &phba->pcidev->dev,
9945 GFP_KERNEL, (void *)phba,
9946 lpfc_write_firmware);
9947 } else if (fw_upgrade == RUN_FW_UPGRADE) {
9948 ret = request_firmware(&fw, file_name, &phba->pcidev->dev);
9949 if (!ret)
9950 lpfc_write_firmware(fw, (void *)phba);
9951 } else {
9952 ret = -EINVAL;
9953 }
9954
9955 return ret;
9956}
9957
9958
9959
9960
9961
9962
9963
9964
9965
9966
9967
9968
9969
9970
9971
9972
9973
9974
9975
9976static int
9977lpfc_pci_probe_one_s4(struct pci_dev *pdev, const struct pci_device_id *pid)
9978{
9979 struct lpfc_hba *phba;
9980 struct lpfc_vport *vport = NULL;
9981 struct Scsi_Host *shost = NULL;
9982 int error, ret;
9983 uint32_t cfg_mode, intr_mode;
9984 int adjusted_fcp_io_channel;
9985
9986
9987 phba = lpfc_hba_alloc(pdev);
9988 if (!phba)
9989 return -ENOMEM;
9990
9991
9992 error = lpfc_enable_pci_dev(phba);
9993 if (error)
9994 goto out_free_phba;
9995
9996
9997 error = lpfc_api_table_setup(phba, LPFC_PCI_DEV_OC);
9998 if (error)
9999 goto out_disable_pci_dev;
10000
10001
10002 error = lpfc_sli4_pci_mem_setup(phba);
10003 if (error) {
10004 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10005 "1410 Failed to set up pci memory space.\n");
10006 goto out_disable_pci_dev;
10007 }
10008
10009
10010 error = lpfc_setup_driver_resource_phase1(phba);
10011 if (error) {
10012 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10013 "1411 Failed to set up driver resource.\n");
10014 goto out_unset_pci_mem_s4;
10015 }
10016
10017
10018 error = lpfc_sli4_driver_resource_setup(phba);
10019 if (error) {
10020 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10021 "1412 Failed to set up driver resource.\n");
10022 goto out_unset_pci_mem_s4;
10023 }
10024
10025
10026
10027 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10028 "2821 initialize iocb list %d.\n",
10029 phba->cfg_iocb_cnt*1024);
10030 error = lpfc_init_iocb_list(phba, phba->cfg_iocb_cnt*1024);
10031
10032 if (error) {
10033 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10034 "1413 Failed to initialize iocb list.\n");
10035 goto out_unset_driver_resource_s4;
10036 }
10037
10038 INIT_LIST_HEAD(&phba->active_rrq_list);
10039 INIT_LIST_HEAD(&phba->fcf.fcf_pri_list);
10040
10041
10042 error = lpfc_setup_driver_resource_phase2(phba);
10043 if (error) {
10044 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10045 "1414 Failed to set up driver resource.\n");
10046 goto out_free_iocb_list;
10047 }
10048
10049
10050 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
10051
10052
10053 error = lpfc_create_shost(phba);
10054 if (error) {
10055 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10056 "1415 Failed to create scsi host.\n");
10057 goto out_unset_driver_resource;
10058 }
10059
10060
10061 vport = phba->pport;
10062 error = lpfc_alloc_sysfs_attr(vport);
10063 if (error) {
10064 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10065 "1416 Failed to allocate sysfs attr\n");
10066 goto out_destroy_shost;
10067 }
10068
10069 shost = lpfc_shost_from_vport(vport);
10070
10071 cfg_mode = phba->cfg_use_msi;
10072
10073
10074 lpfc_stop_port(phba);
10075
10076 intr_mode = lpfc_sli4_enable_intr(phba, cfg_mode);
10077 if (intr_mode == LPFC_INTR_ERROR) {
10078 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10079 "0426 Failed to enable interrupt.\n");
10080 error = -ENODEV;
10081 goto out_free_sysfs_attr;
10082 }
10083
10084 if (phba->intr_type != MSIX)
10085 adjusted_fcp_io_channel = 1;
10086 else
10087 adjusted_fcp_io_channel = phba->cfg_fcp_io_channel;
10088 phba->cfg_fcp_io_channel = adjusted_fcp_io_channel;
10089
10090 if (lpfc_sli4_hba_setup(phba)) {
10091 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10092 "1421 Failed to set up hba\n");
10093 error = -ENODEV;
10094 goto out_disable_intr;
10095 }
10096
10097
10098 phba->intr_mode = intr_mode;
10099 lpfc_log_intr_mode(phba, intr_mode);
10100
10101
10102 lpfc_post_init_setup(phba);
10103
10104
10105 if (phba->cfg_request_firmware_upgrade)
10106 ret = lpfc_sli4_request_firmware_update(phba, INT_FW_UPGRADE);
10107
10108
10109 lpfc_create_static_vport(phba);
10110 return 0;
10111
10112out_disable_intr:
10113 lpfc_sli4_disable_intr(phba);
10114out_free_sysfs_attr:
10115 lpfc_free_sysfs_attr(vport);
10116out_destroy_shost:
10117 lpfc_destroy_shost(phba);
10118out_unset_driver_resource:
10119 lpfc_unset_driver_resource_phase2(phba);
10120out_free_iocb_list:
10121 lpfc_free_iocb_list(phba);
10122out_unset_driver_resource_s4:
10123 lpfc_sli4_driver_resource_unset(phba);
10124out_unset_pci_mem_s4:
10125 lpfc_sli4_pci_mem_unset(phba);
10126out_disable_pci_dev:
10127 lpfc_disable_pci_dev(phba);
10128 if (shost)
10129 scsi_host_put(shost);
10130out_free_phba:
10131 lpfc_hba_free(phba);
10132 return error;
10133}
10134
10135
10136
10137
10138
10139
10140
10141
10142
10143
10144static void
10145lpfc_pci_remove_one_s4(struct pci_dev *pdev)
10146{
10147 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10148 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
10149 struct lpfc_vport **vports;
10150 struct lpfc_hba *phba = vport->phba;
10151 int i;
10152
10153
10154 spin_lock_irq(&phba->hbalock);
10155 vport->load_flag |= FC_UNLOADING;
10156 spin_unlock_irq(&phba->hbalock);
10157
10158
10159 lpfc_free_sysfs_attr(vport);
10160
10161
10162 vports = lpfc_create_vport_work_array(phba);
10163 if (vports != NULL)
10164 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
10165 if (vports[i]->port_type == LPFC_PHYSICAL_PORT)
10166 continue;
10167 fc_vport_terminate(vports[i]->fc_vport);
10168 }
10169 lpfc_destroy_vport_work_array(phba, vports);
10170
10171
10172 fc_remove_host(shost);
10173 scsi_remove_host(shost);
10174
10175
10176 lpfc_cleanup(vport);
10177
10178
10179
10180
10181
10182
10183 lpfc_debugfs_terminate(vport);
10184 lpfc_sli4_hba_unset(phba);
10185
10186 spin_lock_irq(&phba->hbalock);
10187 list_del_init(&vport->listentry);
10188 spin_unlock_irq(&phba->hbalock);
10189
10190
10191
10192
10193 lpfc_scsi_free(phba);
10194
10195 lpfc_sli4_driver_resource_unset(phba);
10196
10197
10198 lpfc_sli4_pci_mem_unset(phba);
10199
10200
10201 scsi_host_put(shost);
10202 lpfc_disable_pci_dev(phba);
10203
10204
10205 lpfc_hba_free(phba);
10206
10207 return;
10208}
10209
10210
10211
10212
10213
10214
10215
10216
10217
10218
10219
10220
10221
10222
10223
10224
10225
10226
10227
10228
10229
10230
10231static int
10232lpfc_pci_suspend_one_s4(struct pci_dev *pdev, pm_message_t msg)
10233{
10234 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10235 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
10236
10237 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10238 "2843 PCI device Power Management suspend.\n");
10239
10240
10241 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
10242 lpfc_offline(phba);
10243 kthread_stop(phba->worker_thread);
10244
10245
10246 lpfc_sli4_disable_intr(phba);
10247 lpfc_sli4_queue_destroy(phba);
10248
10249
10250 pci_save_state(pdev);
10251 pci_set_power_state(pdev, PCI_D3hot);
10252
10253 return 0;
10254}
10255
10256
10257
10258
10259
10260
10261
10262
10263
10264
10265
10266
10267
10268
10269
10270
10271
10272
10273
10274
10275static int
10276lpfc_pci_resume_one_s4(struct pci_dev *pdev)
10277{
10278 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10279 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
10280 uint32_t intr_mode;
10281 int error;
10282
10283 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10284 "0292 PCI device Power Management resume.\n");
10285
10286
10287 pci_set_power_state(pdev, PCI_D0);
10288 pci_restore_state(pdev);
10289
10290
10291
10292
10293
10294 pci_save_state(pdev);
10295
10296 if (pdev->is_busmaster)
10297 pci_set_master(pdev);
10298
10299
10300 phba->worker_thread = kthread_run(lpfc_do_work, phba,
10301 "lpfc_worker_%d", phba->brd_no);
10302 if (IS_ERR(phba->worker_thread)) {
10303 error = PTR_ERR(phba->worker_thread);
10304 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10305 "0293 PM resume failed to start worker "
10306 "thread: error=x%x.\n", error);
10307 return error;
10308 }
10309
10310
10311 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
10312 if (intr_mode == LPFC_INTR_ERROR) {
10313 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10314 "0294 PM resume Failed to enable interrupt\n");
10315 return -EIO;
10316 } else
10317 phba->intr_mode = intr_mode;
10318
10319
10320 lpfc_sli_brdrestart(phba);
10321 lpfc_online(phba);
10322
10323
10324 lpfc_log_intr_mode(phba, phba->intr_mode);
10325
10326 return 0;
10327}
10328
10329
10330
10331
10332
10333
10334
10335
10336static void
10337lpfc_sli4_prep_dev_for_recover(struct lpfc_hba *phba)
10338{
10339 struct lpfc_sli *psli = &phba->sli;
10340 struct lpfc_sli_ring *pring;
10341
10342 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10343 "2828 PCI channel I/O abort preparing for recovery\n");
10344
10345
10346
10347
10348 pring = &psli->ring[psli->fcp_ring];
10349 lpfc_sli_abort_iocb_ring(phba, pring);
10350}
10351
10352
10353
10354
10355
10356
10357
10358
10359
10360static void
10361lpfc_sli4_prep_dev_for_reset(struct lpfc_hba *phba)
10362{
10363 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10364 "2826 PCI channel disable preparing for reset\n");
10365
10366
10367 lpfc_block_mgmt_io(phba, LPFC_MBX_NO_WAIT);
10368
10369
10370 lpfc_scsi_dev_block(phba);
10371
10372
10373 lpfc_sli_flush_fcp_rings(phba);
10374
10375
10376 lpfc_stop_hba_timers(phba);
10377
10378
10379 lpfc_sli4_disable_intr(phba);
10380 lpfc_sli4_queue_destroy(phba);
10381 pci_disable_device(phba->pcidev);
10382}
10383
10384
10385
10386
10387
10388
10389
10390
10391
10392static void
10393lpfc_sli4_prep_dev_for_perm_failure(struct lpfc_hba *phba)
10394{
10395 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10396 "2827 PCI channel permanent disable for failure\n");
10397
10398
10399 lpfc_scsi_dev_block(phba);
10400
10401
10402 lpfc_stop_hba_timers(phba);
10403
10404
10405 lpfc_sli_flush_fcp_rings(phba);
10406}
10407
10408
10409
10410
10411
10412
10413
10414
10415
10416
10417
10418
10419
10420
10421
10422
10423
10424static pci_ers_result_t
10425lpfc_io_error_detected_s4(struct pci_dev *pdev, pci_channel_state_t state)
10426{
10427 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10428 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
10429
10430 switch (state) {
10431 case pci_channel_io_normal:
10432
10433 lpfc_sli4_prep_dev_for_recover(phba);
10434 return PCI_ERS_RESULT_CAN_RECOVER;
10435 case pci_channel_io_frozen:
10436
10437 lpfc_sli4_prep_dev_for_reset(phba);
10438 return PCI_ERS_RESULT_NEED_RESET;
10439 case pci_channel_io_perm_failure:
10440
10441 lpfc_sli4_prep_dev_for_perm_failure(phba);
10442 return PCI_ERS_RESULT_DISCONNECT;
10443 default:
10444
10445 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10446 "2825 Unknown PCI error state: x%x\n", state);
10447 lpfc_sli4_prep_dev_for_reset(phba);
10448 return PCI_ERS_RESULT_NEED_RESET;
10449 }
10450}
10451
10452
10453
10454
10455
10456
10457
10458
10459
10460
10461
10462
10463
10464
10465
10466
10467
10468
10469
10470static pci_ers_result_t
10471lpfc_io_slot_reset_s4(struct pci_dev *pdev)
10472{
10473 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10474 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
10475 struct lpfc_sli *psli = &phba->sli;
10476 uint32_t intr_mode;
10477
10478 dev_printk(KERN_INFO, &pdev->dev, "recovering from a slot reset.\n");
10479 if (pci_enable_device_mem(pdev)) {
10480 printk(KERN_ERR "lpfc: Cannot re-enable "
10481 "PCI device after reset.\n");
10482 return PCI_ERS_RESULT_DISCONNECT;
10483 }
10484
10485 pci_restore_state(pdev);
10486
10487
10488
10489
10490
10491 pci_save_state(pdev);
10492
10493 if (pdev->is_busmaster)
10494 pci_set_master(pdev);
10495
10496 spin_lock_irq(&phba->hbalock);
10497 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
10498 spin_unlock_irq(&phba->hbalock);
10499
10500
10501 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
10502 if (intr_mode == LPFC_INTR_ERROR) {
10503 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10504 "2824 Cannot re-enable interrupt after "
10505 "slot reset.\n");
10506 return PCI_ERS_RESULT_DISCONNECT;
10507 } else
10508 phba->intr_mode = intr_mode;
10509
10510
10511 lpfc_log_intr_mode(phba, phba->intr_mode);
10512
10513 return PCI_ERS_RESULT_RECOVERED;
10514}
10515
10516
10517
10518
10519
10520
10521
10522
10523
10524
10525
10526static void
10527lpfc_io_resume_s4(struct pci_dev *pdev)
10528{
10529 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10530 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
10531
10532
10533
10534
10535
10536
10537
10538 if (!(phba->sli.sli_flag & LPFC_SLI_ACTIVE)) {
10539
10540 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
10541 lpfc_offline(phba);
10542 lpfc_sli_brdrestart(phba);
10543
10544 lpfc_online(phba);
10545 }
10546
10547
10548 if (phba->hba_flag & HBA_AER_ENABLED)
10549 pci_cleanup_aer_uncorrect_error_status(pdev);
10550}
10551
10552
10553
10554
10555
10556
10557
10558
10559
10560
10561
10562
10563
10564
10565
10566
10567
10568
10569
10570static int
10571lpfc_pci_probe_one(struct pci_dev *pdev, const struct pci_device_id *pid)
10572{
10573 int rc;
10574 struct lpfc_sli_intf intf;
10575
10576 if (pci_read_config_dword(pdev, LPFC_SLI_INTF, &intf.word0))
10577 return -ENODEV;
10578
10579 if ((bf_get(lpfc_sli_intf_valid, &intf) == LPFC_SLI_INTF_VALID) &&
10580 (bf_get(lpfc_sli_intf_slirev, &intf) == LPFC_SLI_INTF_REV_SLI4))
10581 rc = lpfc_pci_probe_one_s4(pdev, pid);
10582 else
10583 rc = lpfc_pci_probe_one_s3(pdev, pid);
10584
10585 return rc;
10586}
10587
10588
10589
10590
10591
10592
10593
10594
10595
10596
10597
10598static void
10599lpfc_pci_remove_one(struct pci_dev *pdev)
10600{
10601 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10602 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
10603
10604 switch (phba->pci_dev_grp) {
10605 case LPFC_PCI_DEV_LP:
10606 lpfc_pci_remove_one_s3(pdev);
10607 break;
10608 case LPFC_PCI_DEV_OC:
10609 lpfc_pci_remove_one_s4(pdev);
10610 break;
10611 default:
10612 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10613 "1424 Invalid PCI device group: 0x%x\n",
10614 phba->pci_dev_grp);
10615 break;
10616 }
10617 return;
10618}
10619
10620
10621
10622
10623
10624
10625
10626
10627
10628
10629
10630
10631
10632
10633
10634static int
10635lpfc_pci_suspend_one(struct pci_dev *pdev, pm_message_t msg)
10636{
10637 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10638 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
10639 int rc = -ENODEV;
10640
10641 switch (phba->pci_dev_grp) {
10642 case LPFC_PCI_DEV_LP:
10643 rc = lpfc_pci_suspend_one_s3(pdev, msg);
10644 break;
10645 case LPFC_PCI_DEV_OC:
10646 rc = lpfc_pci_suspend_one_s4(pdev, msg);
10647 break;
10648 default:
10649 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10650 "1425 Invalid PCI device group: 0x%x\n",
10651 phba->pci_dev_grp);
10652 break;
10653 }
10654 return rc;
10655}
10656
10657
10658
10659
10660
10661
10662
10663
10664
10665
10666
10667
10668
10669
10670static int
10671lpfc_pci_resume_one(struct pci_dev *pdev)
10672{
10673 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10674 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
10675 int rc = -ENODEV;
10676
10677 switch (phba->pci_dev_grp) {
10678 case LPFC_PCI_DEV_LP:
10679 rc = lpfc_pci_resume_one_s3(pdev);
10680 break;
10681 case LPFC_PCI_DEV_OC:
10682 rc = lpfc_pci_resume_one_s4(pdev);
10683 break;
10684 default:
10685 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10686 "1426 Invalid PCI device group: 0x%x\n",
10687 phba->pci_dev_grp);
10688 break;
10689 }
10690 return rc;
10691}
10692
10693
10694
10695
10696
10697
10698
10699
10700
10701
10702
10703
10704
10705
10706
10707
10708static pci_ers_result_t
10709lpfc_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
10710{
10711 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10712 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
10713 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
10714
10715 switch (phba->pci_dev_grp) {
10716 case LPFC_PCI_DEV_LP:
10717 rc = lpfc_io_error_detected_s3(pdev, state);
10718 break;
10719 case LPFC_PCI_DEV_OC:
10720 rc = lpfc_io_error_detected_s4(pdev, state);
10721 break;
10722 default:
10723 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10724 "1427 Invalid PCI device group: 0x%x\n",
10725 phba->pci_dev_grp);
10726 break;
10727 }
10728 return rc;
10729}
10730
10731
10732
10733
10734
10735
10736
10737
10738
10739
10740
10741
10742
10743
10744
10745static pci_ers_result_t
10746lpfc_io_slot_reset(struct pci_dev *pdev)
10747{
10748 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10749 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
10750 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
10751
10752 switch (phba->pci_dev_grp) {
10753 case LPFC_PCI_DEV_LP:
10754 rc = lpfc_io_slot_reset_s3(pdev);
10755 break;
10756 case LPFC_PCI_DEV_OC:
10757 rc = lpfc_io_slot_reset_s4(pdev);
10758 break;
10759 default:
10760 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10761 "1428 Invalid PCI device group: 0x%x\n",
10762 phba->pci_dev_grp);
10763 break;
10764 }
10765 return rc;
10766}
10767
10768
10769
10770
10771
10772
10773
10774
10775
10776
10777
10778static void
10779lpfc_io_resume(struct pci_dev *pdev)
10780{
10781 struct Scsi_Host *shost = pci_get_drvdata(pdev);
10782 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
10783
10784 switch (phba->pci_dev_grp) {
10785 case LPFC_PCI_DEV_LP:
10786 lpfc_io_resume_s3(pdev);
10787 break;
10788 case LPFC_PCI_DEV_OC:
10789 lpfc_io_resume_s4(pdev);
10790 break;
10791 default:
10792 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10793 "1429 Invalid PCI device group: 0x%x\n",
10794 phba->pci_dev_grp);
10795 break;
10796 }
10797 return;
10798}
10799
10800static struct pci_device_id lpfc_id_table[] = {
10801 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_VIPER,
10802 PCI_ANY_ID, PCI_ANY_ID, },
10803 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_FIREFLY,
10804 PCI_ANY_ID, PCI_ANY_ID, },
10805 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_THOR,
10806 PCI_ANY_ID, PCI_ANY_ID, },
10807 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_PEGASUS,
10808 PCI_ANY_ID, PCI_ANY_ID, },
10809 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_CENTAUR,
10810 PCI_ANY_ID, PCI_ANY_ID, },
10811 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_DRAGONFLY,
10812 PCI_ANY_ID, PCI_ANY_ID, },
10813 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_SUPERFLY,
10814 PCI_ANY_ID, PCI_ANY_ID, },
10815 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_RFLY,
10816 PCI_ANY_ID, PCI_ANY_ID, },
10817 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_PFLY,
10818 PCI_ANY_ID, PCI_ANY_ID, },
10819 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_NEPTUNE,
10820 PCI_ANY_ID, PCI_ANY_ID, },
10821 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_NEPTUNE_SCSP,
10822 PCI_ANY_ID, PCI_ANY_ID, },
10823 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_NEPTUNE_DCSP,
10824 PCI_ANY_ID, PCI_ANY_ID, },
10825 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_HELIOS,
10826 PCI_ANY_ID, PCI_ANY_ID, },
10827 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_HELIOS_SCSP,
10828 PCI_ANY_ID, PCI_ANY_ID, },
10829 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_HELIOS_DCSP,
10830 PCI_ANY_ID, PCI_ANY_ID, },
10831 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_BMID,
10832 PCI_ANY_ID, PCI_ANY_ID, },
10833 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_BSMB,
10834 PCI_ANY_ID, PCI_ANY_ID, },
10835 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_ZEPHYR,
10836 PCI_ANY_ID, PCI_ANY_ID, },
10837 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_HORNET,
10838 PCI_ANY_ID, PCI_ANY_ID, },
10839 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_ZEPHYR_SCSP,
10840 PCI_ANY_ID, PCI_ANY_ID, },
10841 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_ZEPHYR_DCSP,
10842 PCI_ANY_ID, PCI_ANY_ID, },
10843 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_ZMID,
10844 PCI_ANY_ID, PCI_ANY_ID, },
10845 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_ZSMB,
10846 PCI_ANY_ID, PCI_ANY_ID, },
10847 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_TFLY,
10848 PCI_ANY_ID, PCI_ANY_ID, },
10849 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LP101,
10850 PCI_ANY_ID, PCI_ANY_ID, },
10851 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LP10000S,
10852 PCI_ANY_ID, PCI_ANY_ID, },
10853 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LP11000S,
10854 PCI_ANY_ID, PCI_ANY_ID, },
10855 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LPE11000S,
10856 PCI_ANY_ID, PCI_ANY_ID, },
10857 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_SAT,
10858 PCI_ANY_ID, PCI_ANY_ID, },
10859 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_SAT_MID,
10860 PCI_ANY_ID, PCI_ANY_ID, },
10861 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_SAT_SMB,
10862 PCI_ANY_ID, PCI_ANY_ID, },
10863 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_SAT_DCSP,
10864 PCI_ANY_ID, PCI_ANY_ID, },
10865 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_SAT_SCSP,
10866 PCI_ANY_ID, PCI_ANY_ID, },
10867 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_SAT_S,
10868 PCI_ANY_ID, PCI_ANY_ID, },
10869 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_PROTEUS_VF,
10870 PCI_ANY_ID, PCI_ANY_ID, },
10871 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_PROTEUS_PF,
10872 PCI_ANY_ID, PCI_ANY_ID, },
10873 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_PROTEUS_S,
10874 PCI_ANY_ID, PCI_ANY_ID, },
10875 {PCI_VENDOR_ID_SERVERENGINE, PCI_DEVICE_ID_TIGERSHARK,
10876 PCI_ANY_ID, PCI_ANY_ID, },
10877 {PCI_VENDOR_ID_SERVERENGINE, PCI_DEVICE_ID_TOMCAT,
10878 PCI_ANY_ID, PCI_ANY_ID, },
10879 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_FALCON,
10880 PCI_ANY_ID, PCI_ANY_ID, },
10881 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_BALIUS,
10882 PCI_ANY_ID, PCI_ANY_ID, },
10883 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LANCER_FC,
10884 PCI_ANY_ID, PCI_ANY_ID, },
10885 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LANCER_FCOE,
10886 PCI_ANY_ID, PCI_ANY_ID, },
10887 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LANCER_FC_VF,
10888 PCI_ANY_ID, PCI_ANY_ID, },
10889 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LANCER_FCOE_VF,
10890 PCI_ANY_ID, PCI_ANY_ID, },
10891 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_SKYHAWK,
10892 PCI_ANY_ID, PCI_ANY_ID, },
10893 {PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_SKYHAWK_VF,
10894 PCI_ANY_ID, PCI_ANY_ID, },
10895 { 0 }
10896};
10897
10898MODULE_DEVICE_TABLE(pci, lpfc_id_table);
10899
10900static const struct pci_error_handlers lpfc_err_handler = {
10901 .error_detected = lpfc_io_error_detected,
10902 .slot_reset = lpfc_io_slot_reset,
10903 .resume = lpfc_io_resume,
10904};
10905
10906static struct pci_driver lpfc_driver = {
10907 .name = LPFC_DRIVER_NAME,
10908 .id_table = lpfc_id_table,
10909 .probe = lpfc_pci_probe_one,
10910 .remove = lpfc_pci_remove_one,
10911 .suspend = lpfc_pci_suspend_one,
10912 .resume = lpfc_pci_resume_one,
10913 .err_handler = &lpfc_err_handler,
10914};
10915
10916static const struct file_operations lpfc_mgmt_fop = {
10917 .owner = THIS_MODULE,
10918};
10919
10920static struct miscdevice lpfc_mgmt_dev = {
10921 .minor = MISC_DYNAMIC_MINOR,
10922 .name = "lpfcmgmt",
10923 .fops = &lpfc_mgmt_fop,
10924};
10925
10926
10927
10928
10929
10930
10931
10932
10933
10934
10935
10936
10937
10938static int __init
10939lpfc_init(void)
10940{
10941 int cpu;
10942 int error = 0;
10943
10944 printk(LPFC_MODULE_DESC "\n");
10945 printk(LPFC_COPYRIGHT "\n");
10946
10947 error = misc_register(&lpfc_mgmt_dev);
10948 if (error)
10949 printk(KERN_ERR "Could not register lpfcmgmt device, "
10950 "misc_register returned with status %d", error);
10951
10952 if (lpfc_enable_npiv) {
10953 lpfc_transport_functions.vport_create = lpfc_vport_create;
10954 lpfc_transport_functions.vport_delete = lpfc_vport_delete;
10955 }
10956 lpfc_transport_template =
10957 fc_attach_transport(&lpfc_transport_functions);
10958 if (lpfc_transport_template == NULL)
10959 return -ENOMEM;
10960 if (lpfc_enable_npiv) {
10961 lpfc_vport_transport_template =
10962 fc_attach_transport(&lpfc_vport_transport_functions);
10963 if (lpfc_vport_transport_template == NULL) {
10964 fc_release_transport(lpfc_transport_template);
10965 return -ENOMEM;
10966 }
10967 }
10968
10969
10970 for (cpu = 0; cpu < LPFC_MAX_CPU; cpu++)
10971 lpfc_used_cpu[cpu] = LPFC_VECTOR_MAP_EMPTY;
10972
10973 error = pci_register_driver(&lpfc_driver);
10974 if (error) {
10975 fc_release_transport(lpfc_transport_template);
10976 if (lpfc_enable_npiv)
10977 fc_release_transport(lpfc_vport_transport_template);
10978 }
10979
10980 return error;
10981}
10982
10983
10984
10985
10986
10987
10988
10989
10990static void __exit
10991lpfc_exit(void)
10992{
10993 misc_deregister(&lpfc_mgmt_dev);
10994 pci_unregister_driver(&lpfc_driver);
10995 fc_release_transport(lpfc_transport_template);
10996 if (lpfc_enable_npiv)
10997 fc_release_transport(lpfc_vport_transport_template);
10998 if (_dump_buf_data) {
10999 printk(KERN_ERR "9062 BLKGRD: freeing %lu pages for "
11000 "_dump_buf_data at 0x%p\n",
11001 (1L << _dump_buf_data_order), _dump_buf_data);
11002 free_pages((unsigned long)_dump_buf_data, _dump_buf_data_order);
11003 }
11004
11005 if (_dump_buf_dif) {
11006 printk(KERN_ERR "9049 BLKGRD: freeing %lu pages for "
11007 "_dump_buf_dif at 0x%p\n",
11008 (1L << _dump_buf_dif_order), _dump_buf_dif);
11009 free_pages((unsigned long)_dump_buf_dif, _dump_buf_dif_order);
11010 }
11011}
11012
11013module_init(lpfc_init);
11014module_exit(lpfc_exit);
11015MODULE_LICENSE("GPL");
11016MODULE_DESCRIPTION(LPFC_MODULE_DESC);
11017MODULE_AUTHOR("Emulex Corporation - tech.support@emulex.com");
11018MODULE_VERSION("0:" LPFC_DRIVER_VERSION);
11019