1
2
3
4
5
6
7#include "qla_def.h"
8#include "qla_gbl.h"
9
10#include <linux/delay.h>
11#include <linux/slab.h>
12#include <linux/vmalloc.h>
13
14#include "qla_devtbl.h"
15
16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
18#endif
19
20#include <target/target_core_base.h>
21#include "qla_target.h"
22
23
24
25
26static int qla2x00_isp_firmware(scsi_qla_host_t *);
27static int qla2x00_setup_chip(scsi_qla_host_t *);
28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
32static int qla2x00_configure_fabric(scsi_qla_host_t *);
33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
34static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
35 uint16_t *);
36
37static int qla2x00_restart_isp(scsi_qla_host_t *);
38
39static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
40static int qla84xx_init_chip(scsi_qla_host_t *);
41static int qla25xx_init_queues(struct qla_hw_data *);
42
43
44
45void
46qla2x00_sp_timeout(unsigned long __data)
47{
48 srb_t *sp = (srb_t *)__data;
49 struct srb_iocb *iocb;
50 fc_port_t *fcport = sp->fcport;
51 struct qla_hw_data *ha = fcport->vha->hw;
52 struct req_que *req;
53 unsigned long flags;
54
55 spin_lock_irqsave(&ha->hardware_lock, flags);
56 req = ha->req_q_map[0];
57 req->outstanding_cmds[sp->handle] = NULL;
58 iocb = &sp->u.iocb_cmd;
59 iocb->timeout(sp);
60 sp->free(fcport->vha, sp);
61 spin_unlock_irqrestore(&ha->hardware_lock, flags);
62}
63
64void
65qla2x00_sp_free(void *data, void *ptr)
66{
67 srb_t *sp = (srb_t *)ptr;
68 struct srb_iocb *iocb = &sp->u.iocb_cmd;
69 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
70
71 del_timer(&iocb->timer);
72 qla2x00_rel_sp(vha, sp);
73}
74
75
76
77unsigned long
78qla2x00_get_async_timeout(struct scsi_qla_host *vha)
79{
80 unsigned long tmo;
81 struct qla_hw_data *ha = vha->hw;
82
83
84 tmo = ha->r_a_tov / 10 * 2;
85 if (IS_QLAFX00(ha)) {
86 tmo = FX00_DEF_RATOV * 2;
87 } else if (!IS_FWI2_CAPABLE(ha)) {
88
89
90
91
92 tmo = ha->login_timeout;
93 }
94 return tmo;
95}
96
97static void
98qla2x00_async_iocb_timeout(void *data)
99{
100 srb_t *sp = (srb_t *)data;
101 fc_port_t *fcport = sp->fcport;
102
103 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
104 "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
105 sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
106 fcport->d_id.b.al_pa);
107
108 fcport->flags &= ~FCF_ASYNC_SENT;
109 if (sp->type == SRB_LOGIN_CMD) {
110 struct srb_iocb *lio = &sp->u.iocb_cmd;
111 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
112
113 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
114 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
115 QLA_LOGIO_LOGIN_RETRIED : 0;
116 qla2x00_post_async_login_done_work(fcport->vha, fcport,
117 lio->u.logio.data);
118 }
119}
120
121static void
122qla2x00_async_login_sp_done(void *data, void *ptr, int res)
123{
124 srb_t *sp = (srb_t *)ptr;
125 struct srb_iocb *lio = &sp->u.iocb_cmd;
126 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
127
128 if (!test_bit(UNLOADING, &vha->dpc_flags))
129 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
130 lio->u.logio.data);
131 sp->free(sp->fcport->vha, sp);
132}
133
134int
135qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
136 uint16_t *data)
137{
138 srb_t *sp;
139 struct srb_iocb *lio;
140 int rval;
141
142 rval = QLA_FUNCTION_FAILED;
143 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
144 if (!sp)
145 goto done;
146
147 sp->type = SRB_LOGIN_CMD;
148 sp->name = "login";
149 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
150
151 lio = &sp->u.iocb_cmd;
152 lio->timeout = qla2x00_async_iocb_timeout;
153 sp->done = qla2x00_async_login_sp_done;
154 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
155 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
156 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
157 rval = qla2x00_start_sp(sp);
158 if (rval != QLA_SUCCESS)
159 goto done_free_sp;
160
161 ql_dbg(ql_dbg_disc, vha, 0x2072,
162 "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
163 "retries=%d.\n", sp->handle, fcport->loop_id,
164 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
165 fcport->login_retry);
166 return rval;
167
168done_free_sp:
169 sp->free(fcport->vha, sp);
170done:
171 return rval;
172}
173
174static void
175qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
176{
177 srb_t *sp = (srb_t *)ptr;
178 struct srb_iocb *lio = &sp->u.iocb_cmd;
179 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
180
181 if (!test_bit(UNLOADING, &vha->dpc_flags))
182 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
183 lio->u.logio.data);
184 sp->free(sp->fcport->vha, sp);
185}
186
187int
188qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
189{
190 srb_t *sp;
191 struct srb_iocb *lio;
192 int rval;
193
194 rval = QLA_FUNCTION_FAILED;
195 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
196 if (!sp)
197 goto done;
198
199 sp->type = SRB_LOGOUT_CMD;
200 sp->name = "logout";
201 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
202
203 lio = &sp->u.iocb_cmd;
204 lio->timeout = qla2x00_async_iocb_timeout;
205 sp->done = qla2x00_async_logout_sp_done;
206 rval = qla2x00_start_sp(sp);
207 if (rval != QLA_SUCCESS)
208 goto done_free_sp;
209
210 ql_dbg(ql_dbg_disc, vha, 0x2070,
211 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
212 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
213 fcport->d_id.b.area, fcport->d_id.b.al_pa);
214 return rval;
215
216done_free_sp:
217 sp->free(fcport->vha, sp);
218done:
219 return rval;
220}
221
222static void
223qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
224{
225 srb_t *sp = (srb_t *)ptr;
226 struct srb_iocb *lio = &sp->u.iocb_cmd;
227 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
228
229 if (!test_bit(UNLOADING, &vha->dpc_flags))
230 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
231 lio->u.logio.data);
232 sp->free(sp->fcport->vha, sp);
233}
234
235int
236qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
237 uint16_t *data)
238{
239 srb_t *sp;
240 struct srb_iocb *lio;
241 int rval;
242
243 rval = QLA_FUNCTION_FAILED;
244 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
245 if (!sp)
246 goto done;
247
248 sp->type = SRB_ADISC_CMD;
249 sp->name = "adisc";
250 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
251
252 lio = &sp->u.iocb_cmd;
253 lio->timeout = qla2x00_async_iocb_timeout;
254 sp->done = qla2x00_async_adisc_sp_done;
255 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
256 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
257 rval = qla2x00_start_sp(sp);
258 if (rval != QLA_SUCCESS)
259 goto done_free_sp;
260
261 ql_dbg(ql_dbg_disc, vha, 0x206f,
262 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
263 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
264 fcport->d_id.b.area, fcport->d_id.b.al_pa);
265 return rval;
266
267done_free_sp:
268 sp->free(fcport->vha, sp);
269done:
270 return rval;
271}
272
273static void
274qla2x00_async_tm_cmd_done(void *data, void *ptr, int res)
275{
276 srb_t *sp = (srb_t *)ptr;
277 struct srb_iocb *iocb = &sp->u.iocb_cmd;
278 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
279 uint32_t flags;
280 uint16_t lun;
281 int rval;
282
283 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
284 flags = iocb->u.tmf.flags;
285 lun = (uint16_t)iocb->u.tmf.lun;
286
287
288 rval = qla2x00_marker(vha, vha->hw->req_q_map[0],
289 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
290 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
291
292 if ((rval != QLA_SUCCESS) || iocb->u.tmf.data) {
293 ql_dbg(ql_dbg_taskm, vha, 0x8030,
294 "TM IOCB failed (%x).\n", rval);
295 }
296 }
297 sp->free(sp->fcport->vha, sp);
298}
299
300int
301qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t tm_flags, uint32_t lun,
302 uint32_t tag)
303{
304 struct scsi_qla_host *vha = fcport->vha;
305 srb_t *sp;
306 struct srb_iocb *tcf;
307 int rval;
308
309 rval = QLA_FUNCTION_FAILED;
310 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
311 if (!sp)
312 goto done;
313
314 sp->type = SRB_TM_CMD;
315 sp->name = "tmf";
316 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
317
318 tcf = &sp->u.iocb_cmd;
319 tcf->u.tmf.flags = tm_flags;
320 tcf->u.tmf.lun = lun;
321 tcf->u.tmf.data = tag;
322 tcf->timeout = qla2x00_async_iocb_timeout;
323 sp->done = qla2x00_async_tm_cmd_done;
324
325 rval = qla2x00_start_sp(sp);
326 if (rval != QLA_SUCCESS)
327 goto done_free_sp;
328
329 ql_dbg(ql_dbg_taskm, vha, 0x802f,
330 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
331 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
332 fcport->d_id.b.area, fcport->d_id.b.al_pa);
333 return rval;
334
335done_free_sp:
336 sp->free(fcport->vha, sp);
337done:
338 return rval;
339}
340
341void
342qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
343 uint16_t *data)
344{
345 int rval;
346
347 switch (data[0]) {
348 case MBS_COMMAND_COMPLETE:
349
350
351
352
353
354 rval = qla2x00_get_port_database(vha, fcport, 0);
355 if (rval == QLA_NOT_LOGGED_IN) {
356 fcport->flags &= ~FCF_ASYNC_SENT;
357 fcport->flags |= FCF_LOGIN_NEEDED;
358 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
359 break;
360 }
361
362 if (rval != QLA_SUCCESS) {
363 qla2x00_post_async_logout_work(vha, fcport, NULL);
364 qla2x00_post_async_login_work(vha, fcport, NULL);
365 break;
366 }
367 if (fcport->flags & FCF_FCP2_DEVICE) {
368 qla2x00_post_async_adisc_work(vha, fcport, data);
369 break;
370 }
371 qla2x00_update_fcport(vha, fcport);
372 break;
373 case MBS_COMMAND_ERROR:
374 fcport->flags &= ~FCF_ASYNC_SENT;
375 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
376 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
377 else
378 qla2x00_mark_device_lost(vha, fcport, 1, 0);
379 break;
380 case MBS_PORT_ID_USED:
381 fcport->loop_id = data[1];
382 qla2x00_post_async_logout_work(vha, fcport, NULL);
383 qla2x00_post_async_login_work(vha, fcport, NULL);
384 break;
385 case MBS_LOOP_ID_USED:
386 fcport->loop_id++;
387 rval = qla2x00_find_new_loop_id(vha, fcport);
388 if (rval != QLA_SUCCESS) {
389 fcport->flags &= ~FCF_ASYNC_SENT;
390 qla2x00_mark_device_lost(vha, fcport, 1, 0);
391 break;
392 }
393 qla2x00_post_async_login_work(vha, fcport, NULL);
394 break;
395 }
396 return;
397}
398
399void
400qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
401 uint16_t *data)
402{
403 qla2x00_mark_device_lost(vha, fcport, 1, 0);
404 return;
405}
406
407void
408qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
409 uint16_t *data)
410{
411 if (data[0] == MBS_COMMAND_COMPLETE) {
412 qla2x00_update_fcport(vha, fcport);
413
414 return;
415 }
416
417
418 fcport->flags &= ~FCF_ASYNC_SENT;
419 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
420 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
421 else
422 qla2x00_mark_device_lost(vha, fcport, 1, 0);
423
424 return;
425}
426
427
428
429
430
431static int
432qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
433{
434 int rval = QLA_SUCCESS;
435 struct qla_hw_data *ha = vha->hw;
436 uint32_t idc_major_ver, idc_minor_ver;
437 uint16_t config[4];
438
439 qla83xx_idc_lock(vha, 0);
440
441
442
443
444 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
445 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
446
447
448 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
449 ql_dbg(ql_dbg_p3p, vha, 0xb077,
450 "Error while setting DRV-Presence.\n");
451 rval = QLA_FUNCTION_FAILED;
452 goto exit;
453 }
454
455
456 qla83xx_reset_ownership(vha);
457
458
459
460
461
462
463
464 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
465 if (ha->flags.nic_core_reset_owner) {
466
467 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
468 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
469
470
471 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
472 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
473
474
475
476
477 ql_log(ql_log_warn, vha, 0xb07d,
478 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
479 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
480 __qla83xx_clear_drv_presence(vha);
481 rval = QLA_FUNCTION_FAILED;
482 goto exit;
483 }
484
485 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
486 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
487 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
488
489 if (ha->flags.nic_core_reset_owner) {
490 memset(config, 0, sizeof(config));
491 if (!qla81xx_get_port_config(vha, config))
492 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
493 QLA8XXX_DEV_READY);
494 }
495
496 rval = qla83xx_idc_state_handler(vha);
497
498exit:
499 qla83xx_idc_unlock(vha, 0);
500
501 return rval;
502}
503
504
505
506
507
508
509
510
511
512
513
514int
515qla2x00_initialize_adapter(scsi_qla_host_t *vha)
516{
517 int rval;
518 struct qla_hw_data *ha = vha->hw;
519 struct req_que *req = ha->req_q_map[0];
520
521
522 vha->flags.online = 0;
523 ha->flags.chip_reset_done = 0;
524 vha->flags.reset_active = 0;
525 ha->flags.pci_channel_io_perm_failure = 0;
526 ha->flags.eeh_busy = 0;
527 ha->thermal_support = THERMAL_SUPPORT_I2C|THERMAL_SUPPORT_ISP;
528 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
529 atomic_set(&vha->loop_state, LOOP_DOWN);
530 vha->device_flags = DFLG_NO_CABLE;
531 vha->dpc_flags = 0;
532 vha->flags.management_server_logged_in = 0;
533 vha->marker_needed = 0;
534 ha->isp_abort_cnt = 0;
535 ha->beacon_blink_led = 0;
536
537 set_bit(0, ha->req_qid_map);
538 set_bit(0, ha->rsp_qid_map);
539
540 ql_dbg(ql_dbg_init, vha, 0x0040,
541 "Configuring PCI space...\n");
542 rval = ha->isp_ops->pci_config(vha);
543 if (rval) {
544 ql_log(ql_log_warn, vha, 0x0044,
545 "Unable to configure PCI space.\n");
546 return (rval);
547 }
548
549 ha->isp_ops->reset_chip(vha);
550
551 rval = qla2xxx_get_flash_info(vha);
552 if (rval) {
553 ql_log(ql_log_fatal, vha, 0x004f,
554 "Unable to validate FLASH data.\n");
555 return (rval);
556 }
557
558 ha->isp_ops->get_flash_version(vha, req->ring);
559 ql_dbg(ql_dbg_init, vha, 0x0061,
560 "Configure NVRAM parameters...\n");
561
562 ha->isp_ops->nvram_config(vha);
563
564 if (ha->flags.disable_serdes) {
565
566 ql_log(ql_log_info, vha, 0x0077,
567 "Masking HBA WWPN "
568 "%02x%02x%02x%02x%02x%02x%02x%02x (via NVRAM).\n",
569 vha->port_name[0], vha->port_name[1],
570 vha->port_name[2], vha->port_name[3],
571 vha->port_name[4], vha->port_name[5],
572 vha->port_name[6], vha->port_name[7]);
573 return QLA_FUNCTION_FAILED;
574 }
575
576 ql_dbg(ql_dbg_init, vha, 0x0078,
577 "Verifying loaded RISC code...\n");
578
579 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
580 rval = ha->isp_ops->chip_diag(vha);
581 if (rval)
582 return (rval);
583 rval = qla2x00_setup_chip(vha);
584 if (rval)
585 return (rval);
586 }
587
588 if (IS_QLA84XX(ha)) {
589 ha->cs84xx = qla84xx_get_chip(vha);
590 if (!ha->cs84xx) {
591 ql_log(ql_log_warn, vha, 0x00d0,
592 "Unable to configure ISP84XX.\n");
593 return QLA_FUNCTION_FAILED;
594 }
595 }
596
597 if (qla_ini_mode_enabled(vha))
598 rval = qla2x00_init_rings(vha);
599
600 ha->flags.chip_reset_done = 1;
601
602 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
603
604 rval = qla84xx_init_chip(vha);
605 if (rval != QLA_SUCCESS) {
606 ql_log(ql_log_warn, vha, 0x00d4,
607 "Unable to initialize ISP84XX.\n");
608 qla84xx_put_chip(vha);
609 }
610 }
611
612
613 if (IS_QLA8031(ha)) {
614 rval = qla83xx_nic_core_fw_load(vha);
615 if (rval)
616 ql_log(ql_log_warn, vha, 0x0124,
617 "Error in initializing NIC Core f/w.\n");
618 }
619
620 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
621 qla24xx_read_fcp_prio_cfg(vha);
622
623 return (rval);
624}
625
626
627
628
629
630
631
632int
633qla2100_pci_config(scsi_qla_host_t *vha)
634{
635 uint16_t w;
636 unsigned long flags;
637 struct qla_hw_data *ha = vha->hw;
638 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
639
640 pci_set_master(ha->pdev);
641 pci_try_set_mwi(ha->pdev);
642
643 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
644 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
645 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
646
647 pci_disable_rom(ha->pdev);
648
649
650 spin_lock_irqsave(&ha->hardware_lock, flags);
651 ha->pci_attr = RD_REG_WORD(®->ctrl_status);
652 spin_unlock_irqrestore(&ha->hardware_lock, flags);
653
654 return QLA_SUCCESS;
655}
656
657
658
659
660
661
662
663int
664qla2300_pci_config(scsi_qla_host_t *vha)
665{
666 uint16_t w;
667 unsigned long flags = 0;
668 uint32_t cnt;
669 struct qla_hw_data *ha = vha->hw;
670 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
671
672 pci_set_master(ha->pdev);
673 pci_try_set_mwi(ha->pdev);
674
675 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
676 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
677
678 if (IS_QLA2322(ha) || IS_QLA6322(ha))
679 w &= ~PCI_COMMAND_INTX_DISABLE;
680 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
681
682
683
684
685
686
687
688
689 if (IS_QLA2300(ha)) {
690 spin_lock_irqsave(&ha->hardware_lock, flags);
691
692
693 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
694 for (cnt = 0; cnt < 30000; cnt++) {
695 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0)
696 break;
697
698 udelay(10);
699 }
700
701
702 WRT_REG_WORD(®->ctrl_status, 0x20);
703 RD_REG_WORD(®->ctrl_status);
704
705
706 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
707
708 if (ha->fb_rev == FPM_2300)
709 pci_clear_mwi(ha->pdev);
710
711
712 WRT_REG_WORD(®->ctrl_status, 0x0);
713 RD_REG_WORD(®->ctrl_status);
714
715
716 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC);
717 for (cnt = 0; cnt < 30000; cnt++) {
718 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0)
719 break;
720
721 udelay(10);
722 }
723
724 spin_unlock_irqrestore(&ha->hardware_lock, flags);
725 }
726
727 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
728
729 pci_disable_rom(ha->pdev);
730
731
732 spin_lock_irqsave(&ha->hardware_lock, flags);
733 ha->pci_attr = RD_REG_WORD(®->ctrl_status);
734 spin_unlock_irqrestore(&ha->hardware_lock, flags);
735
736 return QLA_SUCCESS;
737}
738
739
740
741
742
743
744
745int
746qla24xx_pci_config(scsi_qla_host_t *vha)
747{
748 uint16_t w;
749 unsigned long flags = 0;
750 struct qla_hw_data *ha = vha->hw;
751 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
752
753 pci_set_master(ha->pdev);
754 pci_try_set_mwi(ha->pdev);
755
756 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
757 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
758 w &= ~PCI_COMMAND_INTX_DISABLE;
759 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
760
761 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
762
763
764 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
765 pcix_set_mmrbc(ha->pdev, 2048);
766
767
768 if (pci_is_pcie(ha->pdev))
769 pcie_set_readrq(ha->pdev, 4096);
770
771 pci_disable_rom(ha->pdev);
772
773 ha->chip_revision = ha->pdev->revision;
774
775
776 spin_lock_irqsave(&ha->hardware_lock, flags);
777 ha->pci_attr = RD_REG_DWORD(®->ctrl_status);
778 spin_unlock_irqrestore(&ha->hardware_lock, flags);
779
780 return QLA_SUCCESS;
781}
782
783
784
785
786
787
788
789int
790qla25xx_pci_config(scsi_qla_host_t *vha)
791{
792 uint16_t w;
793 struct qla_hw_data *ha = vha->hw;
794
795 pci_set_master(ha->pdev);
796 pci_try_set_mwi(ha->pdev);
797
798 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
799 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
800 w &= ~PCI_COMMAND_INTX_DISABLE;
801 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
802
803
804 if (pci_is_pcie(ha->pdev))
805 pcie_set_readrq(ha->pdev, 4096);
806
807 pci_disable_rom(ha->pdev);
808
809 ha->chip_revision = ha->pdev->revision;
810
811 return QLA_SUCCESS;
812}
813
814
815
816
817
818
819
820static int
821qla2x00_isp_firmware(scsi_qla_host_t *vha)
822{
823 int rval;
824 uint16_t loop_id, topo, sw_cap;
825 uint8_t domain, area, al_pa;
826 struct qla_hw_data *ha = vha->hw;
827
828
829 rval = QLA_FUNCTION_FAILED;
830
831 if (ha->flags.disable_risc_code_load) {
832 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
833
834
835 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
836 if (rval == QLA_SUCCESS) {
837
838 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
839 &area, &domain, &topo, &sw_cap);
840 }
841 }
842
843 if (rval)
844 ql_dbg(ql_dbg_init, vha, 0x007a,
845 "**** Load RISC code ****.\n");
846
847 return (rval);
848}
849
850
851
852
853
854
855
856void
857qla2x00_reset_chip(scsi_qla_host_t *vha)
858{
859 unsigned long flags = 0;
860 struct qla_hw_data *ha = vha->hw;
861 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
862 uint32_t cnt;
863 uint16_t cmd;
864
865 if (unlikely(pci_channel_offline(ha->pdev)))
866 return;
867
868 ha->isp_ops->disable_intrs(ha);
869
870 spin_lock_irqsave(&ha->hardware_lock, flags);
871
872
873 cmd = 0;
874 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
875 cmd &= ~PCI_COMMAND_MASTER;
876 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
877
878 if (!IS_QLA2100(ha)) {
879
880 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
881 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
882 for (cnt = 0; cnt < 30000; cnt++) {
883 if ((RD_REG_WORD(®->hccr) &
884 HCCR_RISC_PAUSE) != 0)
885 break;
886 udelay(100);
887 }
888 } else {
889 RD_REG_WORD(®->hccr);
890 udelay(10);
891 }
892
893
894 WRT_REG_WORD(®->ctrl_status, 0x20);
895 RD_REG_WORD(®->ctrl_status);
896
897
898 WRT_REG_WORD(®->fpm_diag_config, 0x100);
899 RD_REG_WORD(®->fpm_diag_config);
900
901
902 if (!IS_QLA2200(ha)) {
903 WRT_REG_WORD(®->fpm_diag_config, 0x0);
904 RD_REG_WORD(®->fpm_diag_config);
905 }
906
907
908 WRT_REG_WORD(®->ctrl_status, 0x10);
909 RD_REG_WORD(®->ctrl_status);
910
911
912 if (IS_QLA2200(ha)) {
913 WRT_FB_CMD_REG(ha, reg, 0xa000);
914 RD_FB_CMD_REG(ha, reg);
915 } else {
916 WRT_FB_CMD_REG(ha, reg, 0x00fc);
917
918
919 for (cnt = 0; cnt < 3000; cnt++) {
920 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
921 break;
922 udelay(100);
923 }
924 }
925
926
927 WRT_REG_WORD(®->ctrl_status, 0);
928 RD_REG_WORD(®->ctrl_status);
929
930
931 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC);
932 RD_REG_WORD(®->hccr);
933
934
935 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC);
936 RD_REG_WORD(®->hccr);
937 }
938
939 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
940 WRT_REG_WORD(®->hccr, HCCR_CLR_HOST_INT);
941
942
943 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET);
944
945
946 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
947
948
949
950
951
952 udelay(20);
953 for (cnt = 30000; cnt; cnt--) {
954 if ((RD_REG_WORD(®->ctrl_status) &
955 CSR_ISP_SOFT_RESET) == 0)
956 break;
957 udelay(100);
958 }
959 } else
960 udelay(10);
961
962
963 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC);
964
965 WRT_REG_WORD(®->semaphore, 0);
966
967
968 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC);
969 RD_REG_WORD(®->hccr);
970
971 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
972 for (cnt = 0; cnt < 30000; cnt++) {
973 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
974 break;
975
976 udelay(100);
977 }
978 } else
979 udelay(100);
980
981
982 cmd |= PCI_COMMAND_MASTER;
983 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
984
985
986 if (!IS_QLA2100(ha)) {
987 WRT_REG_WORD(®->hccr, HCCR_DISABLE_PARITY_PAUSE);
988 RD_REG_WORD(®->hccr);
989 }
990
991 spin_unlock_irqrestore(&ha->hardware_lock, flags);
992}
993
994
995
996
997
998
999static int
1000qla81xx_reset_mpi(scsi_qla_host_t *vha)
1001{
1002 uint16_t mb[4] = {0x1010, 0, 1, 0};
1003
1004 if (!IS_QLA81XX(vha->hw))
1005 return QLA_SUCCESS;
1006
1007 return qla81xx_write_mpi_register(vha, mb);
1008}
1009
1010
1011
1012
1013
1014
1015
1016static inline void
1017qla24xx_reset_risc(scsi_qla_host_t *vha)
1018{
1019 unsigned long flags = 0;
1020 struct qla_hw_data *ha = vha->hw;
1021 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1022 uint32_t cnt, d2;
1023 uint16_t wd;
1024 static int abts_cnt;
1025
1026 spin_lock_irqsave(&ha->hardware_lock, flags);
1027
1028
1029 WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1030 for (cnt = 0; cnt < 30000; cnt++) {
1031 if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
1032 break;
1033
1034 udelay(10);
1035 }
1036
1037 WRT_REG_DWORD(®->ctrl_status,
1038 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1039 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1040
1041 udelay(100);
1042
1043 d2 = (uint32_t) RD_REG_WORD(®->mailbox0);
1044 for (cnt = 10000 ; cnt && d2; cnt--) {
1045 udelay(5);
1046 d2 = (uint32_t) RD_REG_WORD(®->mailbox0);
1047 barrier();
1048 }
1049
1050
1051 d2 = RD_REG_DWORD(®->ctrl_status);
1052 for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
1053 udelay(5);
1054 d2 = RD_REG_DWORD(®->ctrl_status);
1055 barrier();
1056 }
1057
1058
1059 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
1060 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
1061 if (++abts_cnt < 5) {
1062 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1063 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
1064 } else {
1065
1066
1067
1068
1069 abts_cnt = 0;
1070 vha->flags.online = 0;
1071 }
1072 }
1073 }
1074
1075 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET);
1076 RD_REG_DWORD(®->hccr);
1077
1078 WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE);
1079 RD_REG_DWORD(®->hccr);
1080
1081 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET);
1082 RD_REG_DWORD(®->hccr);
1083
1084 d2 = (uint32_t) RD_REG_WORD(®->mailbox0);
1085 for (cnt = 6000000 ; cnt && d2; cnt--) {
1086 udelay(5);
1087 d2 = (uint32_t) RD_REG_WORD(®->mailbox0);
1088 barrier();
1089 }
1090
1091 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1092
1093 if (IS_NOPOLLING_TYPE(ha))
1094 ha->isp_ops->enable_intrs(ha);
1095}
1096
1097static void
1098qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
1099{
1100 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1101
1102 WRT_REG_DWORD(®->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1103 *data = RD_REG_DWORD(®->iobase_window + RISC_REGISTER_WINDOW_OFFET);
1104
1105}
1106
1107static void
1108qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
1109{
1110 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
1111
1112 WRT_REG_DWORD(®->iobase_addr, RISC_REGISTER_BASE_OFFSET);
1113 WRT_REG_DWORD(®->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
1114}
1115
1116static void
1117qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
1118{
1119 struct qla_hw_data *ha = vha->hw;
1120 uint32_t wd32 = 0;
1121 uint delta_msec = 100;
1122 uint elapsed_msec = 0;
1123 uint timeout_msec;
1124 ulong n;
1125
1126 if (!IS_QLA25XX(ha) && !IS_QLA2031(ha))
1127 return;
1128
1129attempt:
1130 timeout_msec = TIMEOUT_SEMAPHORE;
1131 n = timeout_msec / delta_msec;
1132 while (n--) {
1133 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
1134 qla25xx_read_risc_sema_reg(vha, &wd32);
1135 if (wd32 & RISC_SEMAPHORE)
1136 break;
1137 msleep(delta_msec);
1138 elapsed_msec += delta_msec;
1139 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1140 goto force;
1141 }
1142
1143 if (!(wd32 & RISC_SEMAPHORE))
1144 goto force;
1145
1146 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1147 goto acquired;
1148
1149 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
1150 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
1151 n = timeout_msec / delta_msec;
1152 while (n--) {
1153 qla25xx_read_risc_sema_reg(vha, &wd32);
1154 if (!(wd32 & RISC_SEMAPHORE_FORCE))
1155 break;
1156 msleep(delta_msec);
1157 elapsed_msec += delta_msec;
1158 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
1159 goto force;
1160 }
1161
1162 if (wd32 & RISC_SEMAPHORE_FORCE)
1163 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
1164
1165 goto attempt;
1166
1167force:
1168 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
1169
1170acquired:
1171 return;
1172}
1173
1174
1175
1176
1177
1178
1179
1180void
1181qla24xx_reset_chip(scsi_qla_host_t *vha)
1182{
1183 struct qla_hw_data *ha = vha->hw;
1184
1185 if (pci_channel_offline(ha->pdev) &&
1186 ha->flags.pci_channel_io_perm_failure) {
1187 return;
1188 }
1189
1190 ha->isp_ops->disable_intrs(ha);
1191
1192 qla25xx_manipulate_risc_semaphore(vha);
1193
1194
1195 qla24xx_reset_risc(vha);
1196}
1197
1198
1199
1200
1201
1202
1203
1204int
1205qla2x00_chip_diag(scsi_qla_host_t *vha)
1206{
1207 int rval;
1208 struct qla_hw_data *ha = vha->hw;
1209 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1210 unsigned long flags = 0;
1211 uint16_t data;
1212 uint32_t cnt;
1213 uint16_t mb[5];
1214 struct req_que *req = ha->req_q_map[0];
1215
1216
1217 rval = QLA_FUNCTION_FAILED;
1218
1219 ql_dbg(ql_dbg_init, vha, 0x007b,
1220 "Testing device at %lx.\n", (u_long)®->flash_address);
1221
1222 spin_lock_irqsave(&ha->hardware_lock, flags);
1223
1224
1225 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET);
1226
1227
1228
1229
1230
1231 udelay(20);
1232 data = qla2x00_debounce_register(®->ctrl_status);
1233 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
1234 udelay(5);
1235 data = RD_REG_WORD(®->ctrl_status);
1236 barrier();
1237 }
1238
1239 if (!cnt)
1240 goto chip_diag_failed;
1241
1242 ql_dbg(ql_dbg_init, vha, 0x007c,
1243 "Reset register cleared by chip reset.\n");
1244
1245
1246 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC);
1247 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC);
1248
1249
1250 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1251 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
1252 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
1253 udelay(5);
1254 data = RD_MAILBOX_REG(ha, reg, 0);
1255 barrier();
1256 }
1257 } else
1258 udelay(10);
1259
1260 if (!cnt)
1261 goto chip_diag_failed;
1262
1263
1264 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1265
1266 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
1267 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
1268 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
1269 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
1270 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
1271 mb[3] != PROD_ID_3) {
1272 ql_log(ql_log_warn, vha, 0x0062,
1273 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
1274 mb[1], mb[2], mb[3]);
1275
1276 goto chip_diag_failed;
1277 }
1278 ha->product_id[0] = mb[1];
1279 ha->product_id[1] = mb[2];
1280 ha->product_id[2] = mb[3];
1281 ha->product_id[3] = mb[4];
1282
1283
1284 if (req->length > 1024)
1285 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
1286 else
1287 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
1288 req->length;
1289
1290 if (IS_QLA2200(ha) &&
1291 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
1292
1293 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1294
1295 ha->device_type |= DT_ISP2200A;
1296 ha->fw_transfer_size = 128;
1297 }
1298
1299
1300 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1301
1302 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
1303 rval = qla2x00_mbx_reg_test(vha);
1304 if (rval)
1305 ql_log(ql_log_warn, vha, 0x0080,
1306 "Failed mailbox send register test.\n");
1307 else
1308
1309 rval = QLA_SUCCESS;
1310 spin_lock_irqsave(&ha->hardware_lock, flags);
1311
1312chip_diag_failed:
1313 if (rval)
1314 ql_log(ql_log_info, vha, 0x0081,
1315 "Chip diagnostics **** FAILED ****.\n");
1316
1317 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1318
1319 return (rval);
1320}
1321
1322
1323
1324
1325
1326
1327
1328int
1329qla24xx_chip_diag(scsi_qla_host_t *vha)
1330{
1331 int rval;
1332 struct qla_hw_data *ha = vha->hw;
1333 struct req_que *req = ha->req_q_map[0];
1334
1335 if (IS_QLA82XX(ha))
1336 return QLA_SUCCESS;
1337
1338 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
1339
1340 rval = qla2x00_mbx_reg_test(vha);
1341 if (rval) {
1342 ql_log(ql_log_warn, vha, 0x0082,
1343 "Failed mailbox send register test.\n");
1344 } else {
1345
1346 rval = QLA_SUCCESS;
1347 }
1348
1349 return rval;
1350}
1351
1352void
1353qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
1354{
1355 int rval;
1356 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
1357 eft_size, fce_size, mq_size;
1358 dma_addr_t tc_dma;
1359 void *tc;
1360 struct qla_hw_data *ha = vha->hw;
1361 struct req_que *req = ha->req_q_map[0];
1362 struct rsp_que *rsp = ha->rsp_q_map[0];
1363
1364 if (ha->fw_dump) {
1365 ql_dbg(ql_dbg_init, vha, 0x00bd,
1366 "Firmware dump already allocated.\n");
1367 return;
1368 }
1369
1370 ha->fw_dumped = 0;
1371 fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
1372 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
1373 fixed_size = sizeof(struct qla2100_fw_dump);
1374 } else if (IS_QLA23XX(ha)) {
1375 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
1376 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
1377 sizeof(uint16_t);
1378 } else if (IS_FWI2_CAPABLE(ha)) {
1379 if (IS_QLA83XX(ha))
1380 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
1381 else if (IS_QLA81XX(ha))
1382 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
1383 else if (IS_QLA25XX(ha))
1384 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
1385 else
1386 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
1387 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
1388 sizeof(uint32_t);
1389 if (ha->mqenable) {
1390 if (!IS_QLA83XX(ha))
1391 mq_size = sizeof(struct qla2xxx_mq_chain);
1392
1393
1394
1395
1396 mq_size += ha->max_req_queues *
1397 (req->length * sizeof(request_t));
1398 mq_size += ha->max_rsp_queues *
1399 (rsp->length * sizeof(response_t));
1400 }
1401 if (ha->tgt.atio_ring)
1402 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
1403
1404 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
1405 goto try_eft;
1406
1407 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
1408 GFP_KERNEL);
1409 if (!tc) {
1410 ql_log(ql_log_warn, vha, 0x00be,
1411 "Unable to allocate (%d KB) for FCE.\n",
1412 FCE_SIZE / 1024);
1413 goto try_eft;
1414 }
1415
1416 memset(tc, 0, FCE_SIZE);
1417 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
1418 ha->fce_mb, &ha->fce_bufs);
1419 if (rval) {
1420 ql_log(ql_log_warn, vha, 0x00bf,
1421 "Unable to initialize FCE (%d).\n", rval);
1422 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
1423 tc_dma);
1424 ha->flags.fce_enabled = 0;
1425 goto try_eft;
1426 }
1427 ql_dbg(ql_dbg_init, vha, 0x00c0,
1428 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
1429
1430 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
1431 ha->flags.fce_enabled = 1;
1432 ha->fce_dma = tc_dma;
1433 ha->fce = tc;
1434try_eft:
1435
1436 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
1437 GFP_KERNEL);
1438 if (!tc) {
1439 ql_log(ql_log_warn, vha, 0x00c1,
1440 "Unable to allocate (%d KB) for EFT.\n",
1441 EFT_SIZE / 1024);
1442 goto cont_alloc;
1443 }
1444
1445 memset(tc, 0, EFT_SIZE);
1446 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
1447 if (rval) {
1448 ql_log(ql_log_warn, vha, 0x00c2,
1449 "Unable to initialize EFT (%d).\n", rval);
1450 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
1451 tc_dma);
1452 goto cont_alloc;
1453 }
1454 ql_dbg(ql_dbg_init, vha, 0x00c3,
1455 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
1456
1457 eft_size = EFT_SIZE;
1458 ha->eft_dma = tc_dma;
1459 ha->eft = tc;
1460 }
1461cont_alloc:
1462 req_q_size = req->length * sizeof(request_t);
1463 rsp_q_size = rsp->length * sizeof(response_t);
1464
1465 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
1466 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
1467 ha->chain_offset = dump_size;
1468 dump_size += mq_size + fce_size;
1469
1470 ha->fw_dump = vmalloc(dump_size);
1471 if (!ha->fw_dump) {
1472 ql_log(ql_log_warn, vha, 0x00c4,
1473 "Unable to allocate (%d KB) for firmware dump.\n",
1474 dump_size / 1024);
1475
1476 if (ha->fce) {
1477 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
1478 ha->fce_dma);
1479 ha->fce = NULL;
1480 ha->fce_dma = 0;
1481 }
1482
1483 if (ha->eft) {
1484 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
1485 ha->eft_dma);
1486 ha->eft = NULL;
1487 ha->eft_dma = 0;
1488 }
1489 return;
1490 }
1491 ql_dbg(ql_dbg_init, vha, 0x00c5,
1492 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
1493
1494 ha->fw_dump_len = dump_size;
1495 ha->fw_dump->signature[0] = 'Q';
1496 ha->fw_dump->signature[1] = 'L';
1497 ha->fw_dump->signature[2] = 'G';
1498 ha->fw_dump->signature[3] = 'C';
1499 ha->fw_dump->version = __constant_htonl(1);
1500
1501 ha->fw_dump->fixed_size = htonl(fixed_size);
1502 ha->fw_dump->mem_size = htonl(mem_size);
1503 ha->fw_dump->req_q_size = htonl(req_q_size);
1504 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
1505
1506 ha->fw_dump->eft_size = htonl(eft_size);
1507 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
1508 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
1509
1510 ha->fw_dump->header_size =
1511 htonl(offsetof(struct qla2xxx_fw_dump, isp));
1512}
1513
1514static int
1515qla81xx_mpi_sync(scsi_qla_host_t *vha)
1516{
1517#define MPS_MASK 0xe0
1518 int rval;
1519 uint16_t dc;
1520 uint32_t dw;
1521
1522 if (!IS_QLA81XX(vha->hw))
1523 return QLA_SUCCESS;
1524
1525 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
1526 if (rval != QLA_SUCCESS) {
1527 ql_log(ql_log_warn, vha, 0x0105,
1528 "Unable to acquire semaphore.\n");
1529 goto done;
1530 }
1531
1532 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
1533 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
1534 if (rval != QLA_SUCCESS) {
1535 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
1536 goto done_release;
1537 }
1538
1539 dc &= MPS_MASK;
1540 if (dc == (dw & MPS_MASK))
1541 goto done_release;
1542
1543 dw &= ~MPS_MASK;
1544 dw |= dc;
1545 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
1546 if (rval != QLA_SUCCESS) {
1547 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
1548 }
1549
1550done_release:
1551 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
1552 if (rval != QLA_SUCCESS) {
1553 ql_log(ql_log_warn, vha, 0x006d,
1554 "Unable to release semaphore.\n");
1555 }
1556
1557done:
1558 return rval;
1559}
1560
1561int
1562qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
1563{
1564
1565 if (req->outstanding_cmds)
1566 return QLA_SUCCESS;
1567
1568 if (!IS_FWI2_CAPABLE(ha) || (ha->mqiobase &&
1569 (ql2xmultique_tag || ql2xmaxqueues > 1)))
1570 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
1571 else {
1572 if (ha->fw_xcb_count <= ha->fw_iocb_count)
1573 req->num_outstanding_cmds = ha->fw_xcb_count;
1574 else
1575 req->num_outstanding_cmds = ha->fw_iocb_count;
1576 }
1577
1578 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1579 req->num_outstanding_cmds, GFP_KERNEL);
1580
1581 if (!req->outstanding_cmds) {
1582
1583
1584
1585
1586 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
1587 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
1588 req->num_outstanding_cmds, GFP_KERNEL);
1589
1590 if (!req->outstanding_cmds) {
1591 ql_log(ql_log_fatal, NULL, 0x0126,
1592 "Failed to allocate memory for "
1593 "outstanding_cmds for req_que %p.\n", req);
1594 req->num_outstanding_cmds = 0;
1595 return QLA_FUNCTION_FAILED;
1596 }
1597 }
1598
1599 return QLA_SUCCESS;
1600}
1601
1602
1603
1604
1605
1606
1607
1608static int
1609qla2x00_setup_chip(scsi_qla_host_t *vha)
1610{
1611 int rval;
1612 uint32_t srisc_address = 0;
1613 struct qla_hw_data *ha = vha->hw;
1614 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1615 unsigned long flags;
1616 uint16_t fw_major_version;
1617
1618 if (IS_QLA82XX(ha)) {
1619 rval = ha->isp_ops->load_risc(vha, &srisc_address);
1620 if (rval == QLA_SUCCESS) {
1621 qla2x00_stop_firmware(vha);
1622 goto enable_82xx_npiv;
1623 } else
1624 goto failed;
1625 }
1626
1627 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1628
1629 spin_lock_irqsave(&ha->hardware_lock, flags);
1630 WRT_REG_WORD(®->hccr, (HCCR_ENABLE_PARITY + 0x0));
1631 RD_REG_WORD(®->hccr);
1632 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1633 }
1634
1635 qla81xx_mpi_sync(vha);
1636
1637
1638 rval = ha->isp_ops->load_risc(vha, &srisc_address);
1639 if (rval == QLA_SUCCESS) {
1640 ql_dbg(ql_dbg_init, vha, 0x00c9,
1641 "Verifying Checksum of loaded RISC code.\n");
1642
1643 rval = qla2x00_verify_checksum(vha, srisc_address);
1644 if (rval == QLA_SUCCESS) {
1645
1646 ql_dbg(ql_dbg_init, vha, 0x00ca,
1647 "Starting firmware.\n");
1648
1649 rval = qla2x00_execute_fw(vha, srisc_address);
1650
1651 if (rval == QLA_SUCCESS) {
1652enable_82xx_npiv:
1653 fw_major_version = ha->fw_major_version;
1654 if (IS_QLA82XX(ha))
1655 qla82xx_check_md_needed(vha);
1656 else
1657 rval = qla2x00_get_fw_version(vha);
1658 if (rval != QLA_SUCCESS)
1659 goto failed;
1660 ha->flags.npiv_supported = 0;
1661 if (IS_QLA2XXX_MIDTYPE(ha) &&
1662 (ha->fw_attributes & BIT_2)) {
1663 ha->flags.npiv_supported = 1;
1664 if ((!ha->max_npiv_vports) ||
1665 ((ha->max_npiv_vports + 1) %
1666 MIN_MULTI_ID_FABRIC))
1667 ha->max_npiv_vports =
1668 MIN_MULTI_ID_FABRIC - 1;
1669 }
1670 qla2x00_get_resource_cnts(vha, NULL,
1671 &ha->fw_xcb_count, NULL, &ha->fw_iocb_count,
1672 &ha->max_npiv_vports, NULL);
1673
1674
1675
1676
1677
1678 rval = qla2x00_alloc_outstanding_cmds(ha,
1679 vha->req);
1680 if (rval != QLA_SUCCESS)
1681 goto failed;
1682
1683 if (!fw_major_version && ql2xallocfwdump
1684 && !IS_QLA82XX(ha))
1685 qla2x00_alloc_fw_dump(vha);
1686 }
1687 } else {
1688 ql_log(ql_log_fatal, vha, 0x00cd,
1689 "ISP Firmware failed checksum.\n");
1690 goto failed;
1691 }
1692 } else
1693 goto failed;
1694
1695 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1696
1697 spin_lock_irqsave(&ha->hardware_lock, flags);
1698 if (IS_QLA2300(ha))
1699
1700 WRT_REG_WORD(®->hccr, HCCR_ENABLE_PARITY + 0x1);
1701 else
1702
1703 WRT_REG_WORD(®->hccr, HCCR_ENABLE_PARITY + 0x7);
1704 RD_REG_WORD(®->hccr);
1705 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1706 }
1707
1708 if (IS_QLA83XX(ha))
1709 goto skip_fac_check;
1710
1711 if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1712 uint32_t size;
1713
1714 rval = qla81xx_fac_get_sector_size(vha, &size);
1715 if (rval == QLA_SUCCESS) {
1716 ha->flags.fac_supported = 1;
1717 ha->fdt_block_size = size << 2;
1718 } else {
1719 ql_log(ql_log_warn, vha, 0x00ce,
1720 "Unsupported FAC firmware (%d.%02d.%02d).\n",
1721 ha->fw_major_version, ha->fw_minor_version,
1722 ha->fw_subminor_version);
1723skip_fac_check:
1724 if (IS_QLA83XX(ha)) {
1725 ha->flags.fac_supported = 0;
1726 rval = QLA_SUCCESS;
1727 }
1728 }
1729 }
1730failed:
1731 if (rval) {
1732 ql_log(ql_log_fatal, vha, 0x00cf,
1733 "Setup chip ****FAILED****.\n");
1734 }
1735
1736 return (rval);
1737}
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748void
1749qla2x00_init_response_q_entries(struct rsp_que *rsp)
1750{
1751 uint16_t cnt;
1752 response_t *pkt;
1753
1754 rsp->ring_ptr = rsp->ring;
1755 rsp->ring_index = 0;
1756 rsp->status_srb = NULL;
1757 pkt = rsp->ring_ptr;
1758 for (cnt = 0; cnt < rsp->length; cnt++) {
1759 pkt->signature = RESPONSE_PROCESSED;
1760 pkt++;
1761 }
1762}
1763
1764
1765
1766
1767
1768
1769
1770void
1771qla2x00_update_fw_options(scsi_qla_host_t *vha)
1772{
1773 uint16_t swing, emphasis, tx_sens, rx_sens;
1774 struct qla_hw_data *ha = vha->hw;
1775
1776 memset(ha->fw_options, 0, sizeof(ha->fw_options));
1777 qla2x00_get_fw_options(vha, ha->fw_options);
1778
1779 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1780 return;
1781
1782
1783 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
1784 "Serial link options.\n");
1785 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
1786 (uint8_t *)&ha->fw_seriallink_options,
1787 sizeof(ha->fw_seriallink_options));
1788
1789 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1790 if (ha->fw_seriallink_options[3] & BIT_2) {
1791 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
1792
1793
1794 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
1795 emphasis = (ha->fw_seriallink_options[2] &
1796 (BIT_4 | BIT_3)) >> 3;
1797 tx_sens = ha->fw_seriallink_options[0] &
1798 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1799 rx_sens = (ha->fw_seriallink_options[0] &
1800 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1801 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
1802 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1803 if (rx_sens == 0x0)
1804 rx_sens = 0x3;
1805 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
1806 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1807 ha->fw_options[10] |= BIT_5 |
1808 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1809 (tx_sens & (BIT_1 | BIT_0));
1810
1811
1812 swing = (ha->fw_seriallink_options[2] &
1813 (BIT_7 | BIT_6 | BIT_5)) >> 5;
1814 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
1815 tx_sens = ha->fw_seriallink_options[1] &
1816 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1817 rx_sens = (ha->fw_seriallink_options[1] &
1818 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1819 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
1820 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1821 if (rx_sens == 0x0)
1822 rx_sens = 0x3;
1823 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
1824 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1825 ha->fw_options[11] |= BIT_5 |
1826 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1827 (tx_sens & (BIT_1 | BIT_0));
1828 }
1829
1830
1831
1832 ha->fw_options[3] |= BIT_13;
1833
1834
1835 if (ha->flags.enable_led_scheme)
1836 ha->fw_options[2] |= BIT_12;
1837
1838
1839 if (IS_QLA6312(ha))
1840 ha->fw_options[2] |= BIT_13;
1841
1842
1843 qla2x00_set_fw_options(vha, ha->fw_options);
1844}
1845
1846void
1847qla24xx_update_fw_options(scsi_qla_host_t *vha)
1848{
1849 int rval;
1850 struct qla_hw_data *ha = vha->hw;
1851
1852 if (IS_QLA82XX(ha))
1853 return;
1854
1855
1856 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
1857 return;
1858
1859 rval = qla2x00_set_serdes_params(vha,
1860 le16_to_cpu(ha->fw_seriallink_options24[1]),
1861 le16_to_cpu(ha->fw_seriallink_options24[2]),
1862 le16_to_cpu(ha->fw_seriallink_options24[3]));
1863 if (rval != QLA_SUCCESS) {
1864 ql_log(ql_log_warn, vha, 0x0104,
1865 "Unable to update Serial Link options (%x).\n", rval);
1866 }
1867}
1868
1869void
1870qla2x00_config_rings(struct scsi_qla_host *vha)
1871{
1872 struct qla_hw_data *ha = vha->hw;
1873 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1874 struct req_que *req = ha->req_q_map[0];
1875 struct rsp_que *rsp = ha->rsp_q_map[0];
1876
1877
1878 ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
1879 ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
1880 ha->init_cb->request_q_length = cpu_to_le16(req->length);
1881 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
1882 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1883 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1884 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1885 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
1886
1887 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
1888 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
1889 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
1890 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
1891 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg));
1892}
1893
1894void
1895qla24xx_config_rings(struct scsi_qla_host *vha)
1896{
1897 struct qla_hw_data *ha = vha->hw;
1898 device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
1899 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
1900 struct qla_msix_entry *msix;
1901 struct init_cb_24xx *icb;
1902 uint16_t rid = 0;
1903 struct req_que *req = ha->req_q_map[0];
1904 struct rsp_que *rsp = ha->rsp_q_map[0];
1905
1906
1907 icb = (struct init_cb_24xx *)ha->init_cb;
1908 icb->request_q_outpointer = __constant_cpu_to_le16(0);
1909 icb->response_q_inpointer = __constant_cpu_to_le16(0);
1910 icb->request_q_length = cpu_to_le16(req->length);
1911 icb->response_q_length = cpu_to_le16(rsp->length);
1912 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1913 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1914 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1915 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
1916
1917
1918 icb->atio_q_inpointer = __constant_cpu_to_le16(0);
1919 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
1920 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
1921 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
1922
1923 if (ha->mqenable || IS_QLA83XX(ha)) {
1924 icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
1925 icb->rid = __constant_cpu_to_le16(rid);
1926 if (ha->flags.msix_enabled) {
1927 msix = &ha->msix_entries[1];
1928 ql_dbg(ql_dbg_init, vha, 0x00fd,
1929 "Registering vector 0x%x for base que.\n",
1930 msix->entry);
1931 icb->msix = cpu_to_le16(msix->entry);
1932 }
1933
1934 if (MSB(rid))
1935 icb->firmware_options_2 |=
1936 __constant_cpu_to_le32(BIT_19);
1937
1938 if (LSB(rid))
1939 icb->firmware_options_2 |=
1940 __constant_cpu_to_le32(BIT_18);
1941
1942
1943 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
1944 (ha->flags.msix_enabled)) {
1945 icb->firmware_options_2 &=
1946 __constant_cpu_to_le32(~BIT_22);
1947 ha->flags.disable_msix_handshake = 1;
1948 ql_dbg(ql_dbg_init, vha, 0x00fe,
1949 "MSIX Handshake Disable Mode turned on.\n");
1950 } else {
1951 icb->firmware_options_2 |=
1952 __constant_cpu_to_le32(BIT_22);
1953 }
1954 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
1955
1956 WRT_REG_DWORD(®->isp25mq.req_q_in, 0);
1957 WRT_REG_DWORD(®->isp25mq.req_q_out, 0);
1958 WRT_REG_DWORD(®->isp25mq.rsp_q_in, 0);
1959 WRT_REG_DWORD(®->isp25mq.rsp_q_out, 0);
1960 } else {
1961 WRT_REG_DWORD(®->isp24.req_q_in, 0);
1962 WRT_REG_DWORD(®->isp24.req_q_out, 0);
1963 WRT_REG_DWORD(®->isp24.rsp_q_in, 0);
1964 WRT_REG_DWORD(®->isp24.rsp_q_out, 0);
1965 }
1966 qlt_24xx_config_rings(vha);
1967
1968
1969 RD_REG_DWORD(&ioreg->hccr);
1970}
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981int
1982qla2x00_init_rings(scsi_qla_host_t *vha)
1983{
1984 int rval;
1985 unsigned long flags = 0;
1986 int cnt, que;
1987 struct qla_hw_data *ha = vha->hw;
1988 struct req_que *req;
1989 struct rsp_que *rsp;
1990 struct mid_init_cb_24xx *mid_init_cb =
1991 (struct mid_init_cb_24xx *) ha->init_cb;
1992
1993 spin_lock_irqsave(&ha->hardware_lock, flags);
1994
1995
1996 for (que = 0; que < ha->max_req_queues; que++) {
1997 req = ha->req_q_map[que];
1998 if (!req)
1999 continue;
2000 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
2001 req->outstanding_cmds[cnt] = NULL;
2002
2003 req->current_outstanding_cmd = 1;
2004
2005
2006 req->ring_ptr = req->ring;
2007 req->ring_index = 0;
2008 req->cnt = req->length;
2009 }
2010
2011 for (que = 0; que < ha->max_rsp_queues; que++) {
2012 rsp = ha->rsp_q_map[que];
2013 if (!rsp)
2014 continue;
2015
2016 if (IS_QLAFX00(ha))
2017 qlafx00_init_response_q_entries(rsp);
2018 else
2019 qla2x00_init_response_q_entries(rsp);
2020 }
2021
2022 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
2023 ha->tgt.atio_ring_index = 0;
2024
2025 qlt_init_atio_q_entries(vha);
2026
2027 ha->isp_ops->config_rings(vha);
2028
2029 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2030
2031 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
2032
2033 if (IS_QLAFX00(ha)) {
2034 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
2035 goto next_check;
2036 }
2037
2038
2039 ha->isp_ops->update_fw_options(vha);
2040
2041 if (ha->flags.npiv_supported) {
2042 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
2043 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
2044 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
2045 }
2046
2047 if (IS_FWI2_CAPABLE(ha)) {
2048 mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
2049 mid_init_cb->init_cb.execution_throttle =
2050 cpu_to_le16(ha->fw_xcb_count);
2051 }
2052
2053 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
2054next_check:
2055 if (rval) {
2056 ql_log(ql_log_fatal, vha, 0x00d2,
2057 "Init Firmware **** FAILED ****.\n");
2058 } else {
2059 ql_dbg(ql_dbg_init, vha, 0x00d3,
2060 "Init Firmware -- success.\n");
2061 }
2062
2063 return (rval);
2064}
2065
2066
2067
2068
2069
2070
2071
2072static int
2073qla2x00_fw_ready(scsi_qla_host_t *vha)
2074{
2075 int rval;
2076 unsigned long wtime, mtime, cs84xx_time;
2077 uint16_t min_wait;
2078 uint16_t wait_time;
2079 uint16_t state[5];
2080 struct qla_hw_data *ha = vha->hw;
2081
2082 if (IS_QLAFX00(vha->hw))
2083 return qlafx00_fw_ready(vha);
2084
2085 rval = QLA_SUCCESS;
2086
2087
2088 min_wait = 20;
2089
2090
2091
2092
2093
2094 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
2095 wait_time = min_wait;
2096 }
2097
2098
2099 mtime = jiffies + (min_wait * HZ);
2100
2101
2102 wtime = jiffies + (wait_time * HZ);
2103
2104
2105 if (!vha->flags.init_done)
2106 ql_log(ql_log_info, vha, 0x801e,
2107 "Waiting for LIP to complete.\n");
2108
2109 do {
2110 memset(state, -1, sizeof(state));
2111 rval = qla2x00_get_firmware_state(vha, state);
2112 if (rval == QLA_SUCCESS) {
2113 if (state[0] < FSTATE_LOSS_OF_SYNC) {
2114 vha->device_flags &= ~DFLG_NO_CABLE;
2115 }
2116 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
2117 ql_dbg(ql_dbg_taskm, vha, 0x801f,
2118 "fw_state=%x 84xx=%x.\n", state[0],
2119 state[2]);
2120 if ((state[2] & FSTATE_LOGGED_IN) &&
2121 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
2122 ql_dbg(ql_dbg_taskm, vha, 0x8028,
2123 "Sending verify iocb.\n");
2124
2125 cs84xx_time = jiffies;
2126 rval = qla84xx_init_chip(vha);
2127 if (rval != QLA_SUCCESS) {
2128 ql_log(ql_log_warn,
2129 vha, 0x8007,
2130 "Init chip failed.\n");
2131 break;
2132 }
2133
2134
2135 cs84xx_time = jiffies - cs84xx_time;
2136 wtime += cs84xx_time;
2137 mtime += cs84xx_time;
2138 ql_dbg(ql_dbg_taskm, vha, 0x8008,
2139 "Increasing wait time by %ld. "
2140 "New time %ld.\n", cs84xx_time,
2141 wtime);
2142 }
2143 } else if (state[0] == FSTATE_READY) {
2144 ql_dbg(ql_dbg_taskm, vha, 0x8037,
2145 "F/W Ready - OK.\n");
2146
2147 qla2x00_get_retry_cnt(vha, &ha->retry_count,
2148 &ha->login_timeout, &ha->r_a_tov);
2149
2150 rval = QLA_SUCCESS;
2151 break;
2152 }
2153
2154 rval = QLA_FUNCTION_FAILED;
2155
2156 if (atomic_read(&vha->loop_down_timer) &&
2157 state[0] != FSTATE_READY) {
2158
2159
2160
2161 if (time_after_eq(jiffies, mtime)) {
2162 ql_log(ql_log_info, vha, 0x8038,
2163 "Cable is unplugged...\n");
2164
2165 vha->device_flags |= DFLG_NO_CABLE;
2166 break;
2167 }
2168 }
2169 } else {
2170
2171 if (time_after_eq(jiffies, mtime) ||
2172 ha->flags.isp82xx_fw_hung)
2173 break;
2174 }
2175
2176 if (time_after_eq(jiffies, wtime))
2177 break;
2178
2179
2180 msleep(500);
2181 } while (1);
2182
2183 ql_dbg(ql_dbg_taskm, vha, 0x803a,
2184 "fw_state=%x (%x, %x, %x, %x) " "curr time=%lx.\n", state[0],
2185 state[1], state[2], state[3], state[4], jiffies);
2186
2187 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
2188 ql_log(ql_log_warn, vha, 0x803b,
2189 "Firmware ready **** FAILED ****.\n");
2190 }
2191
2192 return (rval);
2193}
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208static int
2209qla2x00_configure_hba(scsi_qla_host_t *vha)
2210{
2211 int rval;
2212 uint16_t loop_id;
2213 uint16_t topo;
2214 uint16_t sw_cap;
2215 uint8_t al_pa;
2216 uint8_t area;
2217 uint8_t domain;
2218 char connect_type[22];
2219 struct qla_hw_data *ha = vha->hw;
2220 unsigned long flags;
2221 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
2222
2223
2224 rval = qla2x00_get_adapter_id(vha,
2225 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
2226 if (rval != QLA_SUCCESS) {
2227 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
2228 IS_CNA_CAPABLE(ha) ||
2229 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
2230 ql_dbg(ql_dbg_disc, vha, 0x2008,
2231 "Loop is in a transition state.\n");
2232 } else {
2233 ql_log(ql_log_warn, vha, 0x2009,
2234 "Unable to get host loop ID.\n");
2235 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
2236 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
2237 ql_log(ql_log_warn, vha, 0x1151,
2238 "Doing link init.\n");
2239 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
2240 return rval;
2241 }
2242 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2243 }
2244 return (rval);
2245 }
2246
2247 if (topo == 4) {
2248 ql_log(ql_log_info, vha, 0x200a,
2249 "Cannot get topology - retrying.\n");
2250 return (QLA_FUNCTION_FAILED);
2251 }
2252
2253 vha->loop_id = loop_id;
2254
2255
2256 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
2257 ha->operating_mode = LOOP;
2258 ha->switch_cap = 0;
2259
2260 switch (topo) {
2261 case 0:
2262 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
2263 ha->current_topology = ISP_CFG_NL;
2264 strcpy(connect_type, "(Loop)");
2265 break;
2266
2267 case 1:
2268 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2269 ha->switch_cap = sw_cap;
2270 ha->current_topology = ISP_CFG_FL;
2271 strcpy(connect_type, "(FL_Port)");
2272 break;
2273
2274 case 2:
2275 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
2276 ha->operating_mode = P2P;
2277 ha->current_topology = ISP_CFG_N;
2278 strcpy(connect_type, "(N_Port-to-N_Port)");
2279 break;
2280
2281 case 3:
2282 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2283 ha->switch_cap = sw_cap;
2284 ha->operating_mode = P2P;
2285 ha->current_topology = ISP_CFG_F;
2286 strcpy(connect_type, "(F_Port)");
2287 break;
2288
2289 default:
2290 ql_dbg(ql_dbg_disc, vha, 0x200f,
2291 "HBA in unknown topology %x, using NL.\n", topo);
2292 ha->current_topology = ISP_CFG_NL;
2293 strcpy(connect_type, "(Loop)");
2294 break;
2295 }
2296
2297
2298
2299 vha->d_id.b.domain = domain;
2300 vha->d_id.b.area = area;
2301 vha->d_id.b.al_pa = al_pa;
2302
2303 spin_lock_irqsave(&ha->vport_slock, flags);
2304 qlt_update_vp_map(vha, SET_AL_PA);
2305 spin_unlock_irqrestore(&ha->vport_slock, flags);
2306
2307 if (!vha->flags.init_done)
2308 ql_log(ql_log_info, vha, 0x2010,
2309 "Topology - %s, Host Loop address 0x%x.\n",
2310 connect_type, vha->loop_id);
2311
2312 if (rval) {
2313 ql_log(ql_log_warn, vha, 0x2011,
2314 "%s FAILED\n", __func__);
2315 } else {
2316 ql_dbg(ql_dbg_disc, vha, 0x2012,
2317 "%s success\n", __func__);
2318 }
2319
2320 return(rval);
2321}
2322
2323inline void
2324qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
2325 char *def)
2326{
2327 char *st, *en;
2328 uint16_t index;
2329 struct qla_hw_data *ha = vha->hw;
2330 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
2331 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
2332
2333 if (memcmp(model, BINZERO, len) != 0) {
2334 strncpy(ha->model_number, model, len);
2335 st = en = ha->model_number;
2336 en += len - 1;
2337 while (en > st) {
2338 if (*en != 0x20 && *en != 0x00)
2339 break;
2340 *en-- = '\0';
2341 }
2342
2343 index = (ha->pdev->subsystem_device & 0xff);
2344 if (use_tbl &&
2345 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
2346 index < QLA_MODEL_NAMES)
2347 strncpy(ha->model_desc,
2348 qla2x00_model_name[index * 2 + 1],
2349 sizeof(ha->model_desc) - 1);
2350 } else {
2351 index = (ha->pdev->subsystem_device & 0xff);
2352 if (use_tbl &&
2353 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
2354 index < QLA_MODEL_NAMES) {
2355 strcpy(ha->model_number,
2356 qla2x00_model_name[index * 2]);
2357 strncpy(ha->model_desc,
2358 qla2x00_model_name[index * 2 + 1],
2359 sizeof(ha->model_desc) - 1);
2360 } else {
2361 strcpy(ha->model_number, def);
2362 }
2363 }
2364 if (IS_FWI2_CAPABLE(ha))
2365 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
2366 sizeof(ha->model_desc));
2367}
2368
2369
2370
2371
2372static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
2373{
2374#ifdef CONFIG_SPARC
2375 struct qla_hw_data *ha = vha->hw;
2376 struct pci_dev *pdev = ha->pdev;
2377 struct device_node *dp = pci_device_to_OF_node(pdev);
2378 const u8 *val;
2379 int len;
2380
2381 val = of_get_property(dp, "port-wwn", &len);
2382 if (val && len >= WWN_SIZE)
2383 memcpy(nv->port_name, val, WWN_SIZE);
2384
2385 val = of_get_property(dp, "node-wwn", &len);
2386 if (val && len >= WWN_SIZE)
2387 memcpy(nv->node_name, val, WWN_SIZE);
2388#endif
2389}
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404int
2405qla2x00_nvram_config(scsi_qla_host_t *vha)
2406{
2407 int rval;
2408 uint8_t chksum = 0;
2409 uint16_t cnt;
2410 uint8_t *dptr1, *dptr2;
2411 struct qla_hw_data *ha = vha->hw;
2412 init_cb_t *icb = ha->init_cb;
2413 nvram_t *nv = ha->nvram;
2414 uint8_t *ptr = ha->nvram;
2415 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2416
2417 rval = QLA_SUCCESS;
2418
2419
2420 ha->nvram_size = sizeof(nvram_t);
2421 ha->nvram_base = 0;
2422 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
2423 if ((RD_REG_WORD(®->ctrl_status) >> 14) == 1)
2424 ha->nvram_base = 0x80;
2425
2426
2427 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
2428 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
2429 chksum += *ptr++;
2430
2431 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
2432 "Contents of NVRAM.\n");
2433 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
2434 (uint8_t *)nv, ha->nvram_size);
2435
2436
2437 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
2438 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
2439
2440 ql_log(ql_log_warn, vha, 0x0064,
2441 "Inconsistent NVRAM "
2442 "detected: checksum=0x%x id=%c version=0x%x.\n",
2443 chksum, nv->id[0], nv->nvram_version);
2444 ql_log(ql_log_warn, vha, 0x0065,
2445 "Falling back to "
2446 "functioning (yet invalid -- WWPN) defaults.\n");
2447
2448
2449
2450
2451 memset(nv, 0, ha->nvram_size);
2452 nv->parameter_block_version = ICB_VERSION;
2453
2454 if (IS_QLA23XX(ha)) {
2455 nv->firmware_options[0] = BIT_2 | BIT_1;
2456 nv->firmware_options[1] = BIT_7 | BIT_5;
2457 nv->add_firmware_options[0] = BIT_5;
2458 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2459 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2460 nv->special_options[1] = BIT_7;
2461 } else if (IS_QLA2200(ha)) {
2462 nv->firmware_options[0] = BIT_2 | BIT_1;
2463 nv->firmware_options[1] = BIT_7 | BIT_5;
2464 nv->add_firmware_options[0] = BIT_5;
2465 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2466 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2467 } else if (IS_QLA2100(ha)) {
2468 nv->firmware_options[0] = BIT_3 | BIT_1;
2469 nv->firmware_options[1] = BIT_5;
2470 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2471 }
2472
2473 nv->max_iocb_allocation = __constant_cpu_to_le16(256);
2474 nv->execution_throttle = __constant_cpu_to_le16(16);
2475 nv->retry_count = 8;
2476 nv->retry_delay = 1;
2477
2478 nv->port_name[0] = 33;
2479 nv->port_name[3] = 224;
2480 nv->port_name[4] = 139;
2481
2482 qla2xxx_nvram_wwn_from_ofw(vha, nv);
2483
2484 nv->login_timeout = 4;
2485
2486
2487
2488
2489 nv->host_p[1] = BIT_2;
2490 nv->reset_delay = 5;
2491 nv->port_down_retry_count = 8;
2492 nv->max_luns_per_target = __constant_cpu_to_le16(8);
2493 nv->link_down_timeout = 60;
2494
2495 rval = 1;
2496 }
2497
2498#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2499
2500
2501
2502
2503
2504
2505 if (ia64_platform_is("sn2")) {
2506 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2507 if (IS_QLA23XX(ha))
2508 nv->special_options[1] = BIT_7;
2509 }
2510#endif
2511
2512
2513 memset(icb, 0, ha->init_cb_size);
2514
2515
2516
2517
2518 nv->firmware_options[0] |= (BIT_6 | BIT_1);
2519 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
2520 nv->firmware_options[1] |= (BIT_5 | BIT_0);
2521 nv->firmware_options[1] &= ~BIT_4;
2522
2523 if (IS_QLA23XX(ha)) {
2524 nv->firmware_options[0] |= BIT_2;
2525 nv->firmware_options[0] &= ~BIT_3;
2526 nv->special_options[0] &= ~BIT_6;
2527 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
2528
2529 if (IS_QLA2300(ha)) {
2530 if (ha->fb_rev == FPM_2310) {
2531 strcpy(ha->model_number, "QLA2310");
2532 } else {
2533 strcpy(ha->model_number, "QLA2300");
2534 }
2535 } else {
2536 qla2x00_set_model_info(vha, nv->model_number,
2537 sizeof(nv->model_number), "QLA23xx");
2538 }
2539 } else if (IS_QLA2200(ha)) {
2540 nv->firmware_options[0] |= BIT_2;
2541
2542
2543
2544
2545 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
2546 (BIT_5 | BIT_4)) {
2547
2548 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
2549 nv->add_firmware_options[0] |= BIT_5;
2550 }
2551 strcpy(ha->model_number, "QLA22xx");
2552 } else {
2553 strcpy(ha->model_number, "QLA2100");
2554 }
2555
2556
2557
2558
2559 dptr1 = (uint8_t *)icb;
2560 dptr2 = (uint8_t *)&nv->parameter_block_version;
2561 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
2562 while (cnt--)
2563 *dptr1++ = *dptr2++;
2564
2565
2566 dptr1 = (uint8_t *)icb->add_firmware_options;
2567 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
2568 while (cnt--)
2569 *dptr1++ = *dptr2++;
2570
2571
2572 if (nv->host_p[1] & BIT_7) {
2573 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
2574 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
2575 }
2576
2577
2578 if ((icb->firmware_options[1] & BIT_6) == 0) {
2579
2580
2581
2582
2583 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
2584 icb->node_name[0] &= 0xF0;
2585 }
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595 if (nv->host_p[0] & BIT_7)
2596 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
2597 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
2598
2599 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
2600 ha->flags.disable_risc_code_load = 0;
2601 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
2602 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
2603 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
2604 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
2605 ha->flags.disable_serdes = 0;
2606
2607 ha->operating_mode =
2608 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
2609
2610 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
2611 sizeof(ha->fw_seriallink_options));
2612
2613
2614 ha->serial0 = icb->port_name[5];
2615 ha->serial1 = icb->port_name[6];
2616 ha->serial2 = icb->port_name[7];
2617 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
2618 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
2619
2620 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
2621
2622 ha->retry_count = nv->retry_count;
2623
2624
2625 if (nv->login_timeout != ql2xlogintimeout)
2626 nv->login_timeout = ql2xlogintimeout;
2627 if (nv->login_timeout < 4)
2628 nv->login_timeout = 4;
2629 ha->login_timeout = nv->login_timeout;
2630 icb->login_timeout = nv->login_timeout;
2631
2632
2633 ha->r_a_tov = 100;
2634
2635 ha->loop_reset_delay = nv->reset_delay;
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647 if (nv->link_down_timeout == 0) {
2648 ha->loop_down_abort_time =
2649 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
2650 } else {
2651 ha->link_down_timeout = nv->link_down_timeout;
2652 ha->loop_down_abort_time =
2653 (LOOP_DOWN_TIME - ha->link_down_timeout);
2654 }
2655
2656
2657
2658
2659 ha->port_down_retry_count = nv->port_down_retry_count;
2660 if (qlport_down_retry)
2661 ha->port_down_retry_count = qlport_down_retry;
2662
2663 ha->login_retry_count = nv->retry_count;
2664 if (ha->port_down_retry_count == nv->port_down_retry_count &&
2665 ha->port_down_retry_count > 3)
2666 ha->login_retry_count = ha->port_down_retry_count;
2667 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
2668 ha->login_retry_count = ha->port_down_retry_count;
2669 if (ql2xloginretrycount)
2670 ha->login_retry_count = ql2xloginretrycount;
2671
2672 icb->lun_enables = __constant_cpu_to_le16(0);
2673 icb->command_resource_count = 0;
2674 icb->immediate_notify_resource_count = 0;
2675 icb->timeout = __constant_cpu_to_le16(0);
2676
2677 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2678
2679 icb->firmware_options[0] &= ~BIT_3;
2680 icb->add_firmware_options[0] &=
2681 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2682 icb->add_firmware_options[0] |= BIT_2;
2683 icb->response_accumulation_timer = 3;
2684 icb->interrupt_delay_timer = 5;
2685
2686 vha->flags.process_response_queue = 1;
2687 } else {
2688
2689 if (!vha->flags.init_done) {
2690 ha->zio_mode = icb->add_firmware_options[0] &
2691 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2692 ha->zio_timer = icb->interrupt_delay_timer ?
2693 icb->interrupt_delay_timer: 2;
2694 }
2695 icb->add_firmware_options[0] &=
2696 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2697 vha->flags.process_response_queue = 0;
2698 if (ha->zio_mode != QLA_ZIO_DISABLED) {
2699 ha->zio_mode = QLA_ZIO_MODE_6;
2700
2701 ql_log(ql_log_info, vha, 0x0068,
2702 "ZIO mode %d enabled; timer delay (%d us).\n",
2703 ha->zio_mode, ha->zio_timer * 100);
2704
2705 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
2706 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
2707 vha->flags.process_response_queue = 1;
2708 }
2709 }
2710
2711 if (rval) {
2712 ql_log(ql_log_warn, vha, 0x0069,
2713 "NVRAM configuration failed.\n");
2714 }
2715 return (rval);
2716}
2717
2718static void
2719qla2x00_rport_del(void *data)
2720{
2721 fc_port_t *fcport = data;
2722 struct fc_rport *rport;
2723 scsi_qla_host_t *vha = fcport->vha;
2724 unsigned long flags;
2725
2726 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
2727 rport = fcport->drport ? fcport->drport: fcport->rport;
2728 fcport->drport = NULL;
2729 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
2730 if (rport) {
2731 fc_remote_port_delete(rport);
2732
2733
2734
2735
2736 qlt_fc_port_deleted(vha, fcport);
2737 }
2738}
2739
2740
2741
2742
2743
2744
2745
2746
2747fc_port_t *
2748qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
2749{
2750 fc_port_t *fcport;
2751
2752 fcport = kzalloc(sizeof(fc_port_t), flags);
2753 if (!fcport)
2754 return NULL;
2755
2756
2757 fcport->vha = vha;
2758 fcport->port_type = FCT_UNKNOWN;
2759 fcport->loop_id = FC_NO_LOOP_ID;
2760 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
2761 fcport->supported_classes = FC_COS_UNSPECIFIED;
2762
2763 return fcport;
2764}
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778static int
2779qla2x00_configure_loop(scsi_qla_host_t *vha)
2780{
2781 int rval;
2782 unsigned long flags, save_flags;
2783 struct qla_hw_data *ha = vha->hw;
2784 rval = QLA_SUCCESS;
2785
2786
2787 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
2788 rval = qla2x00_configure_hba(vha);
2789 if (rval != QLA_SUCCESS) {
2790 ql_dbg(ql_dbg_disc, vha, 0x2013,
2791 "Unable to configure HBA.\n");
2792 return (rval);
2793 }
2794 }
2795
2796 save_flags = flags = vha->dpc_flags;
2797 ql_dbg(ql_dbg_disc, vha, 0x2014,
2798 "Configure loop -- dpc flags = 0x%lx.\n", flags);
2799
2800
2801
2802
2803
2804 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2805 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
2806
2807 qla2x00_get_data_rate(vha);
2808
2809
2810 if (ha->current_topology == ISP_CFG_FL &&
2811 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2812
2813 set_bit(RSCN_UPDATE, &flags);
2814
2815 } else if (ha->current_topology == ISP_CFG_F &&
2816 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2817
2818 set_bit(RSCN_UPDATE, &flags);
2819 clear_bit(LOCAL_LOOP_UPDATE, &flags);
2820
2821 } else if (ha->current_topology == ISP_CFG_N) {
2822 clear_bit(RSCN_UPDATE, &flags);
2823
2824 } else if (!vha->flags.online ||
2825 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
2826
2827 set_bit(RSCN_UPDATE, &flags);
2828 set_bit(LOCAL_LOOP_UPDATE, &flags);
2829 }
2830
2831 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
2832 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2833 ql_dbg(ql_dbg_disc, vha, 0x2015,
2834 "Loop resync needed, failing.\n");
2835 rval = QLA_FUNCTION_FAILED;
2836 } else
2837 rval = qla2x00_configure_local_loop(vha);
2838 }
2839
2840 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
2841 if (LOOP_TRANSITION(vha)) {
2842 ql_dbg(ql_dbg_disc, vha, 0x201e,
2843 "Needs RSCN update and loop transition.\n");
2844 rval = QLA_FUNCTION_FAILED;
2845 }
2846 else
2847 rval = qla2x00_configure_fabric(vha);
2848 }
2849
2850 if (rval == QLA_SUCCESS) {
2851 if (atomic_read(&vha->loop_down_timer) ||
2852 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2853 rval = QLA_FUNCTION_FAILED;
2854 } else {
2855 atomic_set(&vha->loop_state, LOOP_READY);
2856 ql_dbg(ql_dbg_disc, vha, 0x2069,
2857 "LOOP READY.\n");
2858 }
2859 }
2860
2861 if (rval) {
2862 ql_dbg(ql_dbg_disc, vha, 0x206a,
2863 "%s *** FAILED ***.\n", __func__);
2864 } else {
2865 ql_dbg(ql_dbg_disc, vha, 0x206b,
2866 "%s: exiting normally.\n", __func__);
2867 }
2868
2869
2870 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2871 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
2872 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2873 if (test_bit(RSCN_UPDATE, &save_flags)) {
2874 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2875 }
2876 }
2877
2878 return (rval);
2879}
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893static int
2894qla2x00_configure_local_loop(scsi_qla_host_t *vha)
2895{
2896 int rval, rval2;
2897 int found_devs;
2898 int found;
2899 fc_port_t *fcport, *new_fcport;
2900
2901 uint16_t index;
2902 uint16_t entries;
2903 char *id_iter;
2904 uint16_t loop_id;
2905 uint8_t domain, area, al_pa;
2906 struct qla_hw_data *ha = vha->hw;
2907
2908 found_devs = 0;
2909 new_fcport = NULL;
2910 entries = MAX_FIBRE_DEVICES_LOOP;
2911
2912
2913 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
2914 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
2915 &entries);
2916 if (rval != QLA_SUCCESS)
2917 goto cleanup_allocation;
2918
2919 ql_dbg(ql_dbg_disc, vha, 0x2017,
2920 "Entries in ID list (%d).\n", entries);
2921 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
2922 (uint8_t *)ha->gid_list,
2923 entries * sizeof(struct gid_list_info));
2924
2925
2926 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
2927 if (new_fcport == NULL) {
2928 ql_log(ql_log_warn, vha, 0x2018,
2929 "Memory allocation failed for fcport.\n");
2930 rval = QLA_MEMORY_ALLOC_FAILED;
2931 goto cleanup_allocation;
2932 }
2933 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
2934
2935
2936
2937
2938 list_for_each_entry(fcport, &vha->vp_fcports, list) {
2939 if (atomic_read(&fcport->state) == FCS_ONLINE &&
2940 fcport->port_type != FCT_BROADCAST &&
2941 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
2942
2943 ql_dbg(ql_dbg_disc, vha, 0x2019,
2944 "Marking port lost loop_id=0x%04x.\n",
2945 fcport->loop_id);
2946
2947 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
2948 }
2949 }
2950
2951
2952 id_iter = (char *)ha->gid_list;
2953 for (index = 0; index < entries; index++) {
2954 domain = ((struct gid_list_info *)id_iter)->domain;
2955 area = ((struct gid_list_info *)id_iter)->area;
2956 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
2957 if (IS_QLA2100(ha) || IS_QLA2200(ha))
2958 loop_id = (uint16_t)
2959 ((struct gid_list_info *)id_iter)->loop_id_2100;
2960 else
2961 loop_id = le16_to_cpu(
2962 ((struct gid_list_info *)id_iter)->loop_id);
2963 id_iter += ha->gid_list_info_size;
2964
2965
2966 if ((domain & 0xf0) == 0xf0)
2967 continue;
2968
2969
2970 if (area && domain &&
2971 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
2972 continue;
2973
2974
2975 if (loop_id > LAST_LOCAL_LOOP_ID)
2976 continue;
2977
2978 memset(new_fcport, 0, sizeof(fc_port_t));
2979
2980
2981 new_fcport->d_id.b.domain = domain;
2982 new_fcport->d_id.b.area = area;
2983 new_fcport->d_id.b.al_pa = al_pa;
2984 new_fcport->loop_id = loop_id;
2985 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
2986 if (rval2 != QLA_SUCCESS) {
2987 ql_dbg(ql_dbg_disc, vha, 0x201a,
2988 "Failed to retrieve fcport information "
2989 "-- get_port_database=%x, loop_id=0x%04x.\n",
2990 rval2, new_fcport->loop_id);
2991 ql_dbg(ql_dbg_disc, vha, 0x201b,
2992 "Scheduling resync.\n");
2993 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2994 continue;
2995 }
2996
2997
2998 found = 0;
2999 fcport = NULL;
3000 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3001 if (memcmp(new_fcport->port_name, fcport->port_name,
3002 WWN_SIZE))
3003 continue;
3004
3005 fcport->flags &= ~FCF_FABRIC_DEVICE;
3006 fcport->loop_id = new_fcport->loop_id;
3007 fcport->port_type = new_fcport->port_type;
3008 fcport->d_id.b24 = new_fcport->d_id.b24;
3009 memcpy(fcport->node_name, new_fcport->node_name,
3010 WWN_SIZE);
3011
3012 found++;
3013 break;
3014 }
3015
3016 if (!found) {
3017
3018 list_add_tail(&new_fcport->list, &vha->vp_fcports);
3019
3020
3021 fcport = new_fcport;
3022 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
3023 if (new_fcport == NULL) {
3024 ql_log(ql_log_warn, vha, 0x201c,
3025 "Failed to allocate memory for fcport.\n");
3026 rval = QLA_MEMORY_ALLOC_FAILED;
3027 goto cleanup_allocation;
3028 }
3029 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
3030 }
3031
3032
3033 fcport->fp_speed = ha->link_data_rate;
3034
3035 qla2x00_update_fcport(vha, fcport);
3036
3037 found_devs++;
3038 }
3039
3040cleanup_allocation:
3041 kfree(new_fcport);
3042
3043 if (rval != QLA_SUCCESS) {
3044 ql_dbg(ql_dbg_disc, vha, 0x201d,
3045 "Configure local loop error exit: rval=%x.\n", rval);
3046 }
3047
3048 return (rval);
3049}
3050
3051static void
3052qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
3053{
3054 int rval;
3055 uint16_t mb[4];
3056 struct qla_hw_data *ha = vha->hw;
3057
3058 if (!IS_IIDMA_CAPABLE(ha))
3059 return;
3060
3061 if (atomic_read(&fcport->state) != FCS_ONLINE)
3062 return;
3063
3064 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
3065 fcport->fp_speed > ha->link_data_rate)
3066 return;
3067
3068 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
3069 mb);
3070 if (rval != QLA_SUCCESS) {
3071 ql_dbg(ql_dbg_disc, vha, 0x2004,
3072 "Unable to adjust iIDMA "
3073 "%02x%02x%02x%02x%02x%02x%02x%02x -- %04x %x %04x "
3074 "%04x.\n", fcport->port_name[0], fcport->port_name[1],
3075 fcport->port_name[2], fcport->port_name[3],
3076 fcport->port_name[4], fcport->port_name[5],
3077 fcport->port_name[6], fcport->port_name[7], rval,
3078 fcport->fp_speed, mb[0], mb[1]);
3079 } else {
3080 ql_dbg(ql_dbg_disc, vha, 0x2005,
3081 "iIDMA adjusted to %s GB/s "
3082 "on %02x%02x%02x%02x%02x%02x%02x%02x.\n",
3083 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
3084 fcport->port_name[0], fcport->port_name[1],
3085 fcport->port_name[2], fcport->port_name[3],
3086 fcport->port_name[4], fcport->port_name[5],
3087 fcport->port_name[6], fcport->port_name[7]);
3088 }
3089}
3090
3091static void
3092qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
3093{
3094 struct fc_rport_identifiers rport_ids;
3095 struct fc_rport *rport;
3096 unsigned long flags;
3097
3098 qla2x00_rport_del(fcport);
3099
3100 rport_ids.node_name = wwn_to_u64(fcport->node_name);
3101 rport_ids.port_name = wwn_to_u64(fcport->port_name);
3102 rport_ids.port_id = fcport->d_id.b.domain << 16 |
3103 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
3104 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
3105 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
3106 if (!rport) {
3107 ql_log(ql_log_warn, vha, 0x2006,
3108 "Unable to allocate fc remote port.\n");
3109 return;
3110 }
3111
3112
3113
3114
3115 qlt_fc_port_added(vha, fcport);
3116
3117 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
3118 *((fc_port_t **)rport->dd_data) = fcport;
3119 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
3120
3121 rport->supported_classes = fcport->supported_classes;
3122
3123 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
3124 if (fcport->port_type == FCT_INITIATOR)
3125 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
3126 if (fcport->port_type == FCT_TARGET)
3127 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
3128 fc_remote_port_rolechg(rport, rport_ids.roles);
3129}
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146void
3147qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
3148{
3149 fcport->vha = vha;
3150
3151 if (IS_QLAFX00(vha->hw)) {
3152 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
3153 qla2x00_reg_remote_port(vha, fcport);
3154 return;
3155 }
3156 fcport->login_retry = 0;
3157 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
3158
3159 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
3160 qla2x00_iidma_fcport(vha, fcport);
3161 qla24xx_update_fcport_fcp_prio(vha, fcport);
3162 qla2x00_reg_remote_port(vha, fcport);
3163}
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176static int
3177qla2x00_configure_fabric(scsi_qla_host_t *vha)
3178{
3179 int rval;
3180 fc_port_t *fcport, *fcptemp;
3181 uint16_t next_loopid;
3182 uint16_t mb[MAILBOX_REGISTER_COUNT];
3183 uint16_t loop_id;
3184 LIST_HEAD(new_fcports);
3185 struct qla_hw_data *ha = vha->hw;
3186 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
3187
3188
3189 if (IS_FWI2_CAPABLE(ha))
3190 loop_id = NPH_F_PORT;
3191 else
3192 loop_id = SNS_FL_PORT;
3193 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
3194 if (rval != QLA_SUCCESS) {
3195 ql_dbg(ql_dbg_disc, vha, 0x201f,
3196 "MBX_GET_PORT_NAME failed, No FL Port.\n");
3197
3198 vha->device_flags &= ~SWITCH_FOUND;
3199 return (QLA_SUCCESS);
3200 }
3201 vha->device_flags |= SWITCH_FOUND;
3202
3203 do {
3204
3205 if (ql2xfdmienable &&
3206 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
3207 qla2x00_fdmi_register(vha);
3208
3209
3210 if (IS_FWI2_CAPABLE(ha))
3211 loop_id = NPH_SNS;
3212 else
3213 loop_id = SIMPLE_NAME_SERVER;
3214 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
3215 0xfc, mb, BIT_1|BIT_0);
3216 if (rval != QLA_SUCCESS) {
3217 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3218 return rval;
3219 }
3220 if (mb[0] != MBS_COMMAND_COMPLETE) {
3221 ql_dbg(ql_dbg_disc, vha, 0x2042,
3222 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
3223 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
3224 mb[2], mb[6], mb[7]);
3225 return (QLA_SUCCESS);
3226 }
3227
3228 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
3229 if (qla2x00_rft_id(vha)) {
3230
3231 ql_dbg(ql_dbg_disc, vha, 0x2045,
3232 "Register FC-4 TYPE failed.\n");
3233 }
3234 if (qla2x00_rff_id(vha)) {
3235
3236 ql_dbg(ql_dbg_disc, vha, 0x2049,
3237 "Register FC-4 Features failed.\n");
3238 }
3239 if (qla2x00_rnn_id(vha)) {
3240
3241 ql_dbg(ql_dbg_disc, vha, 0x204f,
3242 "Register Node Name failed.\n");
3243 } else if (qla2x00_rsnn_nn(vha)) {
3244
3245 ql_dbg(ql_dbg_disc, vha, 0x2053,
3246 "Register Symobilic Node Name failed.\n");
3247 }
3248 }
3249
3250#define QLA_FCPORT_SCAN 1
3251#define QLA_FCPORT_FOUND 2
3252
3253 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3254 fcport->scan_state = QLA_FCPORT_SCAN;
3255 }
3256
3257 rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
3258 if (rval != QLA_SUCCESS)
3259 break;
3260
3261
3262
3263
3264
3265 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3266 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3267 break;
3268
3269 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
3270 continue;
3271
3272 if (fcport->scan_state == QLA_FCPORT_SCAN &&
3273 atomic_read(&fcport->state) == FCS_ONLINE) {
3274 qla2x00_mark_device_lost(vha, fcport,
3275 ql2xplogiabsentdevice, 0);
3276 if (fcport->loop_id != FC_NO_LOOP_ID &&
3277 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
3278 fcport->port_type != FCT_INITIATOR &&
3279 fcport->port_type != FCT_BROADCAST) {
3280 ha->isp_ops->fabric_logout(vha,
3281 fcport->loop_id,
3282 fcport->d_id.b.domain,
3283 fcport->d_id.b.area,
3284 fcport->d_id.b.al_pa);
3285 fcport->loop_id = FC_NO_LOOP_ID;
3286 }
3287 }
3288 }
3289
3290
3291 next_loopid = ha->min_external_loopid;
3292
3293
3294
3295
3296
3297 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3298 if (atomic_read(&vha->loop_down_timer) ||
3299 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3300 break;
3301
3302 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
3303 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
3304 continue;
3305
3306 if (fcport->loop_id == FC_NO_LOOP_ID) {
3307 fcport->loop_id = next_loopid;
3308 rval = qla2x00_find_new_loop_id(
3309 base_vha, fcport);
3310 if (rval != QLA_SUCCESS) {
3311
3312 break;
3313 }
3314 }
3315
3316 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
3317 }
3318
3319
3320 if (rval != QLA_SUCCESS) {
3321 break;
3322 }
3323
3324
3325
3326
3327 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3328 if (atomic_read(&vha->loop_down_timer) ||
3329 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3330 break;
3331
3332
3333 fcport->loop_id = next_loopid;
3334 rval = qla2x00_find_new_loop_id(base_vha, fcport);
3335 if (rval != QLA_SUCCESS) {
3336
3337 break;
3338 }
3339
3340
3341 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
3342
3343 list_move_tail(&fcport->list, &vha->vp_fcports);
3344 }
3345 } while (0);
3346
3347
3348 list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
3349 list_del(&fcport->list);
3350 kfree(fcport);
3351 }
3352
3353 if (rval) {
3354 ql_dbg(ql_dbg_disc, vha, 0x2068,
3355 "Configure fabric error exit rval=%d.\n", rval);
3356 }
3357
3358 return (rval);
3359}
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374static int
3375qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
3376 struct list_head *new_fcports)
3377{
3378 int rval;
3379 uint16_t loop_id;
3380 fc_port_t *fcport, *new_fcport, *fcptemp;
3381 int found;
3382
3383 sw_info_t *swl;
3384 int swl_idx;
3385 int first_dev, last_dev;
3386 port_id_t wrap = {}, nxt_d_id;
3387 struct qla_hw_data *ha = vha->hw;
3388 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
3389
3390 rval = QLA_SUCCESS;
3391
3392
3393 if (!ha->swl)
3394 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
3395 GFP_KERNEL);
3396 swl = ha->swl;
3397 if (!swl) {
3398
3399 ql_dbg(ql_dbg_disc, vha, 0x2054,
3400 "GID_PT allocations failed, fallback on GA_NXT.\n");
3401 } else {
3402 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
3403 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
3404 swl = NULL;
3405 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
3406 swl = NULL;
3407 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
3408 swl = NULL;
3409 } else if (ql2xiidmaenable &&
3410 qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
3411 qla2x00_gpsc(vha, swl);
3412 }
3413
3414
3415 if (swl)
3416 qla2x00_gff_id(vha, swl);
3417 }
3418 swl_idx = 0;
3419
3420
3421 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
3422 if (new_fcport == NULL) {
3423 ql_log(ql_log_warn, vha, 0x205e,
3424 "Failed to allocate memory for fcport.\n");
3425 return (QLA_MEMORY_ALLOC_FAILED);
3426 }
3427 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3428
3429 first_dev = 1;
3430 last_dev = 0;
3431
3432
3433 loop_id = ha->min_external_loopid;
3434 for (; loop_id <= ha->max_loop_id; loop_id++) {
3435 if (qla2x00_is_reserved_id(vha, loop_id))
3436 continue;
3437
3438 if (ha->current_topology == ISP_CFG_FL &&
3439 (atomic_read(&vha->loop_down_timer) ||
3440 LOOP_TRANSITION(vha))) {
3441 atomic_set(&vha->loop_down_timer, 0);
3442 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3443 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
3444 break;
3445 }
3446
3447 if (swl != NULL) {
3448 if (last_dev) {
3449 wrap.b24 = new_fcport->d_id.b24;
3450 } else {
3451 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
3452 memcpy(new_fcport->node_name,
3453 swl[swl_idx].node_name, WWN_SIZE);
3454 memcpy(new_fcport->port_name,
3455 swl[swl_idx].port_name, WWN_SIZE);
3456 memcpy(new_fcport->fabric_port_name,
3457 swl[swl_idx].fabric_port_name, WWN_SIZE);
3458 new_fcport->fp_speed = swl[swl_idx].fp_speed;
3459 new_fcport->fc4_type = swl[swl_idx].fc4_type;
3460
3461 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
3462 last_dev = 1;
3463 }
3464 swl_idx++;
3465 }
3466 } else {
3467
3468 rval = qla2x00_ga_nxt(vha, new_fcport);
3469 if (rval != QLA_SUCCESS) {
3470 ql_log(ql_log_warn, vha, 0x2064,
3471 "SNS scan failed -- assuming "
3472 "zero-entry result.\n");
3473 list_for_each_entry_safe(fcport, fcptemp,
3474 new_fcports, list) {
3475 list_del(&fcport->list);
3476 kfree(fcport);
3477 }
3478 rval = QLA_SUCCESS;
3479 break;
3480 }
3481 }
3482
3483
3484 if (first_dev) {
3485 wrap.b24 = new_fcport->d_id.b24;
3486 first_dev = 0;
3487 } else if (new_fcport->d_id.b24 == wrap.b24) {
3488 ql_dbg(ql_dbg_disc, vha, 0x2065,
3489 "Device wrap (%02x%02x%02x).\n",
3490 new_fcport->d_id.b.domain,
3491 new_fcport->d_id.b.area,
3492 new_fcport->d_id.b.al_pa);
3493 break;
3494 }
3495
3496
3497 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
3498 continue;
3499
3500
3501 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
3502 continue;
3503
3504
3505 if (((new_fcport->d_id.b24 & 0xffff00) ==
3506 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
3507 ISP_CFG_FL)
3508 continue;
3509
3510
3511 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
3512 continue;
3513
3514
3515 if (ql2xgffidenable &&
3516 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
3517 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
3518 continue;
3519
3520
3521 found = 0;
3522 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3523 if (memcmp(new_fcport->port_name, fcport->port_name,
3524 WWN_SIZE))
3525 continue;
3526
3527 fcport->scan_state = QLA_FCPORT_FOUND;
3528
3529 found++;
3530
3531
3532 memcpy(fcport->fabric_port_name,
3533 new_fcport->fabric_port_name, WWN_SIZE);
3534 fcport->fp_speed = new_fcport->fp_speed;
3535
3536
3537
3538
3539
3540 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
3541 atomic_read(&fcport->state) == FCS_ONLINE) {
3542 break;
3543 }
3544
3545
3546
3547
3548 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3549 fcport->d_id.b24 = new_fcport->d_id.b24;
3550 qla2x00_clear_loop_id(fcport);
3551 fcport->flags |= (FCF_FABRIC_DEVICE |
3552 FCF_LOGIN_NEEDED);
3553 break;
3554 }
3555
3556
3557
3558
3559
3560
3561 fcport->d_id.b24 = new_fcport->d_id.b24;
3562 fcport->flags |= FCF_LOGIN_NEEDED;
3563 if (fcport->loop_id != FC_NO_LOOP_ID &&
3564 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
3565 (fcport->flags & FCF_ASYNC_SENT) == 0 &&
3566 fcport->port_type != FCT_INITIATOR &&
3567 fcport->port_type != FCT_BROADCAST) {
3568 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
3569 fcport->d_id.b.domain, fcport->d_id.b.area,
3570 fcport->d_id.b.al_pa);
3571 qla2x00_clear_loop_id(fcport);
3572 }
3573
3574 break;
3575 }
3576
3577 if (found)
3578 continue;
3579
3580 list_add_tail(&new_fcport->list, new_fcports);
3581
3582
3583 nxt_d_id.b24 = new_fcport->d_id.b24;
3584 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
3585 if (new_fcport == NULL) {
3586 ql_log(ql_log_warn, vha, 0x2066,
3587 "Memory allocation failed for fcport.\n");
3588 return (QLA_MEMORY_ALLOC_FAILED);
3589 }
3590 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3591 new_fcport->d_id.b24 = nxt_d_id.b24;
3592 }
3593
3594 kfree(new_fcport);
3595
3596 return (rval);
3597}
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613int
3614qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
3615{
3616 int rval;
3617 struct qla_hw_data *ha = vha->hw;
3618 unsigned long flags = 0;
3619
3620 rval = QLA_SUCCESS;
3621
3622 spin_lock_irqsave(&ha->vport_slock, flags);
3623
3624 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
3625 LOOPID_MAP_SIZE);
3626 if (dev->loop_id >= LOOPID_MAP_SIZE ||
3627 qla2x00_is_reserved_id(vha, dev->loop_id)) {
3628 dev->loop_id = FC_NO_LOOP_ID;
3629 rval = QLA_FUNCTION_FAILED;
3630 } else
3631 set_bit(dev->loop_id, ha->loop_id_map);
3632
3633 spin_unlock_irqrestore(&ha->vport_slock, flags);
3634
3635 if (rval == QLA_SUCCESS)
3636 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
3637 "Assigning new loopid=%x, portid=%x.\n",
3638 dev->loop_id, dev->d_id.b24);
3639 else
3640 ql_log(ql_log_warn, dev->vha, 0x2087,
3641 "No loop_id's available, portid=%x.\n",
3642 dev->d_id.b24);
3643
3644 return (rval);
3645}
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663static int
3664qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
3665 uint16_t *next_loopid)
3666{
3667 int rval;
3668 int retry;
3669 uint8_t opts;
3670 struct qla_hw_data *ha = vha->hw;
3671
3672 rval = QLA_SUCCESS;
3673 retry = 0;
3674
3675 if (IS_ALOGIO_CAPABLE(ha)) {
3676 if (fcport->flags & FCF_ASYNC_SENT)
3677 return rval;
3678 fcport->flags |= FCF_ASYNC_SENT;
3679 rval = qla2x00_post_async_login_work(vha, fcport, NULL);
3680 if (!rval)
3681 return rval;
3682 }
3683
3684 fcport->flags &= ~FCF_ASYNC_SENT;
3685 rval = qla2x00_fabric_login(vha, fcport, next_loopid);
3686 if (rval == QLA_SUCCESS) {
3687
3688 opts = 0;
3689 if (fcport->flags & FCF_FCP2_DEVICE)
3690 opts |= BIT_1;
3691 rval = qla2x00_get_port_database(vha, fcport, opts);
3692 if (rval != QLA_SUCCESS) {
3693 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
3694 fcport->d_id.b.domain, fcport->d_id.b.area,
3695 fcport->d_id.b.al_pa);
3696 qla2x00_mark_device_lost(vha, fcport, 1, 0);
3697 } else {
3698 qla2x00_update_fcport(vha, fcport);
3699 }
3700 } else {
3701
3702 qla2x00_mark_device_lost(vha, fcport, 1, 0);
3703 }
3704
3705 return (rval);
3706}
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722int
3723qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
3724 uint16_t *next_loopid)
3725{
3726 int rval;
3727 int retry;
3728 uint16_t tmp_loopid;
3729 uint16_t mb[MAILBOX_REGISTER_COUNT];
3730 struct qla_hw_data *ha = vha->hw;
3731
3732 retry = 0;
3733 tmp_loopid = 0;
3734
3735 for (;;) {
3736 ql_dbg(ql_dbg_disc, vha, 0x2000,
3737 "Trying Fabric Login w/loop id 0x%04x for port "
3738 "%02x%02x%02x.\n",
3739 fcport->loop_id, fcport->d_id.b.domain,
3740 fcport->d_id.b.area, fcport->d_id.b.al_pa);
3741
3742
3743 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
3744 fcport->d_id.b.domain, fcport->d_id.b.area,
3745 fcport->d_id.b.al_pa, mb, BIT_0);
3746 if (rval != QLA_SUCCESS) {
3747 return rval;
3748 }
3749 if (mb[0] == MBS_PORT_ID_USED) {
3750
3751
3752
3753
3754
3755
3756
3757 retry++;
3758 tmp_loopid = fcport->loop_id;
3759 fcport->loop_id = mb[1];
3760
3761 ql_dbg(ql_dbg_disc, vha, 0x2001,
3762 "Fabric Login: port in use - next loop "
3763 "id=0x%04x, port id= %02x%02x%02x.\n",
3764 fcport->loop_id, fcport->d_id.b.domain,
3765 fcport->d_id.b.area, fcport->d_id.b.al_pa);
3766
3767 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
3768
3769
3770
3771 if (retry) {
3772
3773 *next_loopid = tmp_loopid;
3774 } else {
3775
3776
3777
3778
3779 *next_loopid = (fcport->loop_id + 1);
3780 }
3781
3782 if (mb[1] & BIT_0) {
3783 fcport->port_type = FCT_INITIATOR;
3784 } else {
3785 fcport->port_type = FCT_TARGET;
3786 if (mb[1] & BIT_1) {
3787 fcport->flags |= FCF_FCP2_DEVICE;
3788 }
3789 }
3790
3791 if (mb[10] & BIT_0)
3792 fcport->supported_classes |= FC_COS_CLASS2;
3793 if (mb[10] & BIT_1)
3794 fcport->supported_classes |= FC_COS_CLASS3;
3795
3796 if (IS_FWI2_CAPABLE(ha)) {
3797 if (mb[10] & BIT_7)
3798 fcport->flags |=
3799 FCF_CONF_COMP_SUPPORTED;
3800 }
3801
3802 rval = QLA_SUCCESS;
3803 break;
3804 } else if (mb[0] == MBS_LOOP_ID_USED) {
3805
3806
3807
3808 fcport->loop_id++;
3809 rval = qla2x00_find_new_loop_id(vha, fcport);
3810 if (rval != QLA_SUCCESS) {
3811
3812 break;
3813 }
3814 } else if (mb[0] == MBS_COMMAND_ERROR) {
3815
3816
3817
3818
3819
3820 *next_loopid = fcport->loop_id;
3821 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
3822 fcport->d_id.b.domain, fcport->d_id.b.area,
3823 fcport->d_id.b.al_pa);
3824 qla2x00_mark_device_lost(vha, fcport, 1, 0);
3825
3826 rval = 1;
3827 break;
3828 } else {
3829
3830
3831
3832 ql_dbg(ql_dbg_disc, vha, 0x2002,
3833 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
3834 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
3835 fcport->d_id.b.area, fcport->d_id.b.al_pa,
3836 fcport->loop_id, jiffies);
3837
3838 *next_loopid = fcport->loop_id;
3839 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
3840 fcport->d_id.b.domain, fcport->d_id.b.area,
3841 fcport->d_id.b.al_pa);
3842 qla2x00_clear_loop_id(fcport);
3843 fcport->login_retry = 0;
3844
3845 rval = 3;
3846 break;
3847 }
3848 }
3849
3850 return (rval);
3851}
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866int
3867qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
3868{
3869 int rval;
3870 uint16_t mb[MAILBOX_REGISTER_COUNT];
3871
3872 memset(mb, 0, sizeof(mb));
3873 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
3874 if (rval == QLA_SUCCESS) {
3875
3876 if (mb[0] == MBS_COMMAND_ERROR)
3877 rval = 1;
3878 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
3879
3880 rval = 3;
3881 }
3882
3883 return (rval);
3884}
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896int
3897qla2x00_loop_resync(scsi_qla_host_t *vha)
3898{
3899 int rval = QLA_SUCCESS;
3900 uint32_t wait_time;
3901 struct req_que *req;
3902 struct rsp_que *rsp;
3903
3904 if (vha->hw->flags.cpu_affinity_enabled)
3905 req = vha->hw->req_q_map[0];
3906 else
3907 req = vha->req;
3908 rsp = req->rsp;
3909
3910 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3911 if (vha->flags.online) {
3912 if (!(rval = qla2x00_fw_ready(vha))) {
3913
3914 wait_time = 256;
3915 do {
3916 if (!IS_QLAFX00(vha->hw)) {
3917
3918
3919
3920
3921 qla2x00_marker(vha, req, rsp, 0, 0,
3922 MK_SYNC_ALL);
3923 vha->marker_needed = 0;
3924 }
3925
3926
3927 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3928
3929 if (IS_QLAFX00(vha->hw))
3930 qlafx00_configure_devices(vha);
3931 else
3932 qla2x00_configure_loop(vha);
3933
3934 wait_time--;
3935 } while (!atomic_read(&vha->loop_down_timer) &&
3936 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
3937 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
3938 &vha->dpc_flags)));
3939 }
3940 }
3941
3942 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
3943 return (QLA_FUNCTION_FAILED);
3944
3945 if (rval)
3946 ql_dbg(ql_dbg_disc, vha, 0x206c,
3947 "%s *** FAILED ***.\n", __func__);
3948
3949 return (rval);
3950}
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
3961{
3962 int32_t rval = 0;
3963
3964 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
3965
3966 atomic_set(&ha->loop_down_timer, 0);
3967 if (!(ha->device_flags & DFLG_NO_CABLE)) {
3968 atomic_set(&ha->loop_state, LOOP_UP);
3969 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
3970 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
3971 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
3972
3973 rval = qla2x00_loop_resync(ha);
3974 } else
3975 atomic_set(&ha->loop_state, LOOP_DEAD);
3976
3977 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
3978 }
3979
3980 return rval;
3981}
3982
3983void
3984qla2x00_update_fcports(scsi_qla_host_t *base_vha)
3985{
3986 fc_port_t *fcport;
3987 struct scsi_qla_host *vha;
3988 struct qla_hw_data *ha = base_vha->hw;
3989 unsigned long flags;
3990
3991 spin_lock_irqsave(&ha->vport_slock, flags);
3992
3993 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
3994 atomic_inc(&vha->vref_count);
3995 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3996 if (fcport->drport &&
3997 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
3998 spin_unlock_irqrestore(&ha->vport_slock, flags);
3999 qla2x00_rport_del(fcport);
4000 spin_lock_irqsave(&ha->vport_slock, flags);
4001 }
4002 }
4003 atomic_dec(&vha->vref_count);
4004 }
4005 spin_unlock_irqrestore(&ha->vport_slock, flags);
4006}
4007
4008
4009void
4010qla83xx_reset_ownership(scsi_qla_host_t *vha)
4011{
4012 struct qla_hw_data *ha = vha->hw;
4013 uint32_t drv_presence, drv_presence_mask;
4014 uint32_t dev_part_info1, dev_part_info2, class_type;
4015 uint32_t class_type_mask = 0x3;
4016 uint16_t fcoe_other_function = 0xffff, i;
4017
4018 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4019
4020 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
4021 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
4022 for (i = 0; i < 8; i++) {
4023 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
4024 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4025 (i != ha->portnum)) {
4026 fcoe_other_function = i;
4027 break;
4028 }
4029 }
4030 if (fcoe_other_function == 0xffff) {
4031 for (i = 0; i < 8; i++) {
4032 class_type = ((dev_part_info2 >> (i * 4)) &
4033 class_type_mask);
4034 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
4035 ((i + 8) != ha->portnum)) {
4036 fcoe_other_function = i + 8;
4037 break;
4038 }
4039 }
4040 }
4041
4042
4043
4044
4045 drv_presence_mask = ~((1 << (ha->portnum)) |
4046 ((fcoe_other_function == 0xffff) ?
4047 0 : (1 << (fcoe_other_function))));
4048
4049
4050
4051
4052 if (!(drv_presence & drv_presence_mask) &&
4053 (ha->portnum < fcoe_other_function)) {
4054 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
4055 "This host is Reset owner.\n");
4056 ha->flags.nic_core_reset_owner = 1;
4057 }
4058}
4059
4060static int
4061__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
4062{
4063 int rval = QLA_SUCCESS;
4064 struct qla_hw_data *ha = vha->hw;
4065 uint32_t drv_ack;
4066
4067 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4068 if (rval == QLA_SUCCESS) {
4069 drv_ack |= (1 << ha->portnum);
4070 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4071 }
4072
4073 return rval;
4074}
4075
4076static int
4077__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
4078{
4079 int rval = QLA_SUCCESS;
4080 struct qla_hw_data *ha = vha->hw;
4081 uint32_t drv_ack;
4082
4083 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4084 if (rval == QLA_SUCCESS) {
4085 drv_ack &= ~(1 << ha->portnum);
4086 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
4087 }
4088
4089 return rval;
4090}
4091
4092static const char *
4093qla83xx_dev_state_to_string(uint32_t dev_state)
4094{
4095 switch (dev_state) {
4096 case QLA8XXX_DEV_COLD:
4097 return "COLD/RE-INIT";
4098 case QLA8XXX_DEV_INITIALIZING:
4099 return "INITIALIZING";
4100 case QLA8XXX_DEV_READY:
4101 return "READY";
4102 case QLA8XXX_DEV_NEED_RESET:
4103 return "NEED RESET";
4104 case QLA8XXX_DEV_NEED_QUIESCENT:
4105 return "NEED QUIESCENT";
4106 case QLA8XXX_DEV_FAILED:
4107 return "FAILED";
4108 case QLA8XXX_DEV_QUIESCENT:
4109 return "QUIESCENT";
4110 default:
4111 return "Unknown";
4112 }
4113}
4114
4115
4116void
4117qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
4118{
4119 struct qla_hw_data *ha = vha->hw;
4120 uint32_t idc_audit_reg = 0, duration_secs = 0;
4121
4122 switch (audit_type) {
4123 case IDC_AUDIT_TIMESTAMP:
4124 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
4125 idc_audit_reg = (ha->portnum) |
4126 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
4127 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4128 break;
4129
4130 case IDC_AUDIT_COMPLETION:
4131 duration_secs = ((jiffies_to_msecs(jiffies) -
4132 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
4133 idc_audit_reg = (ha->portnum) |
4134 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
4135 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
4136 break;
4137
4138 default:
4139 ql_log(ql_log_warn, vha, 0xb078,
4140 "Invalid audit type specified.\n");
4141 break;
4142 }
4143}
4144
4145
4146static int
4147qla83xx_initiating_reset(scsi_qla_host_t *vha)
4148{
4149 struct qla_hw_data *ha = vha->hw;
4150 uint32_t idc_control, dev_state;
4151
4152 __qla83xx_get_idc_control(vha, &idc_control);
4153 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
4154 ql_log(ql_log_info, vha, 0xb080,
4155 "NIC Core reset has been disabled. idc-control=0x%x\n",
4156 idc_control);
4157 return QLA_FUNCTION_FAILED;
4158 }
4159
4160
4161 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4162 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
4163 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
4164 QLA8XXX_DEV_NEED_RESET);
4165 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
4166 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
4167 } else {
4168 const char *state = qla83xx_dev_state_to_string(dev_state);
4169 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
4170
4171
4172
4173 while (dev_state == QLA8XXX_DEV_READY) {
4174 qla83xx_idc_unlock(vha, 0);
4175 msleep(200);
4176 qla83xx_idc_lock(vha, 0);
4177 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4178 }
4179 }
4180
4181
4182 __qla83xx_set_drv_ack(vha);
4183
4184 return QLA_SUCCESS;
4185}
4186
4187int
4188__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
4189{
4190 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4191}
4192
4193int
4194__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
4195{
4196 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4197}
4198
4199static int
4200qla83xx_check_driver_presence(scsi_qla_host_t *vha)
4201{
4202 uint32_t drv_presence = 0;
4203 struct qla_hw_data *ha = vha->hw;
4204
4205 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4206 if (drv_presence & (1 << ha->portnum))
4207 return QLA_SUCCESS;
4208 else
4209 return QLA_TEST_FAILED;
4210}
4211
4212int
4213qla83xx_nic_core_reset(scsi_qla_host_t *vha)
4214{
4215 int rval = QLA_SUCCESS;
4216 struct qla_hw_data *ha = vha->hw;
4217
4218 ql_dbg(ql_dbg_p3p, vha, 0xb058,
4219 "Entered %s().\n", __func__);
4220
4221 if (vha->device_flags & DFLG_DEV_FAILED) {
4222 ql_log(ql_log_warn, vha, 0xb059,
4223 "Device in unrecoverable FAILED state.\n");
4224 return QLA_FUNCTION_FAILED;
4225 }
4226
4227 qla83xx_idc_lock(vha, 0);
4228
4229 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
4230 ql_log(ql_log_warn, vha, 0xb05a,
4231 "Function=0x%x has been removed from IDC participation.\n",
4232 ha->portnum);
4233 rval = QLA_FUNCTION_FAILED;
4234 goto exit;
4235 }
4236
4237 qla83xx_reset_ownership(vha);
4238
4239 rval = qla83xx_initiating_reset(vha);
4240
4241
4242
4243
4244
4245 if (rval == QLA_SUCCESS) {
4246 rval = qla83xx_idc_state_handler(vha);
4247
4248 if (rval == QLA_SUCCESS)
4249 ha->flags.nic_core_hung = 0;
4250 __qla83xx_clear_drv_ack(vha);
4251 }
4252
4253exit:
4254 qla83xx_idc_unlock(vha, 0);
4255
4256 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
4257
4258 return rval;
4259}
4260
4261int
4262qla2xxx_mctp_dump(scsi_qla_host_t *vha)
4263{
4264 struct qla_hw_data *ha = vha->hw;
4265 int rval = QLA_FUNCTION_FAILED;
4266
4267 if (!IS_MCTP_CAPABLE(ha)) {
4268
4269 ql_log(ql_log_info, vha, 0x506d,
4270 "This board is not MCTP capable\n");
4271 return rval;
4272 }
4273
4274 if (!ha->mctp_dump) {
4275 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
4276 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
4277
4278 if (!ha->mctp_dump) {
4279 ql_log(ql_log_warn, vha, 0x506e,
4280 "Failed to allocate memory for mctp dump\n");
4281 return rval;
4282 }
4283 }
4284
4285#define MCTP_DUMP_STR_ADDR 0x00000000
4286 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
4287 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
4288 if (rval != QLA_SUCCESS) {
4289 ql_log(ql_log_warn, vha, 0x506f,
4290 "Failed to capture mctp dump\n");
4291 } else {
4292 ql_log(ql_log_info, vha, 0x5070,
4293 "Mctp dump capture for host (%ld/%p).\n",
4294 vha->host_no, ha->mctp_dump);
4295 ha->mctp_dumped = 1;
4296 }
4297
4298 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
4299 ha->flags.nic_core_reset_hdlr_active = 1;
4300 rval = qla83xx_restart_nic_firmware(vha);
4301 if (rval)
4302
4303 ql_log(ql_log_warn, vha, 0x5071,
4304 "Failed to restart nic firmware\n");
4305 else
4306 ql_dbg(ql_dbg_p3p, vha, 0xb084,
4307 "Restarted NIC firmware successfully.\n");
4308 ha->flags.nic_core_reset_hdlr_active = 0;
4309 }
4310
4311 return rval;
4312
4313}
4314
4315
4316
4317
4318
4319
4320
4321
4322
4323void
4324qla2x00_quiesce_io(scsi_qla_host_t *vha)
4325{
4326 struct qla_hw_data *ha = vha->hw;
4327 struct scsi_qla_host *vp;
4328
4329 ql_dbg(ql_dbg_dpc, vha, 0x401d,
4330 "Quiescing I/O - ha=%p.\n", ha);
4331
4332 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
4333 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4334 atomic_set(&vha->loop_state, LOOP_DOWN);
4335 qla2x00_mark_all_devices_lost(vha, 0);
4336 list_for_each_entry(vp, &ha->vp_list, list)
4337 qla2x00_mark_all_devices_lost(vp, 0);
4338 } else {
4339 if (!atomic_read(&vha->loop_down_timer))
4340 atomic_set(&vha->loop_down_timer,
4341 LOOP_DOWN_TIME);
4342 }
4343
4344 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
4345}
4346
4347void
4348qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
4349{
4350 struct qla_hw_data *ha = vha->hw;
4351 struct scsi_qla_host *vp;
4352 unsigned long flags;
4353 fc_port_t *fcport;
4354
4355
4356
4357
4358 if (!IS_QLA82XX(ha))
4359 vha->flags.online = 0;
4360 ha->flags.chip_reset_done = 0;
4361 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
4362 vha->qla_stats.total_isp_aborts++;
4363
4364 ql_log(ql_log_info, vha, 0x00af,
4365 "Performing ISP error recovery - ha=%p.\n", ha);
4366
4367
4368
4369
4370
4371 if (!IS_QLA82XX(ha))
4372 ha->isp_ops->reset_chip(vha);
4373
4374 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
4375 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4376 atomic_set(&vha->loop_state, LOOP_DOWN);
4377 qla2x00_mark_all_devices_lost(vha, 0);
4378
4379 spin_lock_irqsave(&ha->vport_slock, flags);
4380 list_for_each_entry(vp, &ha->vp_list, list) {
4381 atomic_inc(&vp->vref_count);
4382 spin_unlock_irqrestore(&ha->vport_slock, flags);
4383
4384 qla2x00_mark_all_devices_lost(vp, 0);
4385
4386 spin_lock_irqsave(&ha->vport_slock, flags);
4387 atomic_dec(&vp->vref_count);
4388 }
4389 spin_unlock_irqrestore(&ha->vport_slock, flags);
4390 } else {
4391 if (!atomic_read(&vha->loop_down_timer))
4392 atomic_set(&vha->loop_down_timer,
4393 LOOP_DOWN_TIME);
4394 }
4395
4396
4397 list_for_each_entry(fcport, &vha->vp_fcports, list)
4398 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4399 spin_lock_irqsave(&ha->vport_slock, flags);
4400 list_for_each_entry(vp, &ha->vp_list, list) {
4401 atomic_inc(&vp->vref_count);
4402 spin_unlock_irqrestore(&ha->vport_slock, flags);
4403
4404 list_for_each_entry(fcport, &vp->vp_fcports, list)
4405 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4406
4407 spin_lock_irqsave(&ha->vport_slock, flags);
4408 atomic_dec(&vp->vref_count);
4409 }
4410 spin_unlock_irqrestore(&ha->vport_slock, flags);
4411
4412 if (!ha->flags.eeh_busy) {
4413
4414 if (IS_QLA82XX(ha)) {
4415 qla82xx_chip_reset_cleanup(vha);
4416 ql_log(ql_log_info, vha, 0x00b4,
4417 "Done chip reset cleanup.\n");
4418
4419
4420
4421
4422 vha->flags.online = 0;
4423 }
4424
4425
4426 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
4427 }
4428}
4429
4430
4431
4432
4433
4434
4435
4436
4437
4438
4439
4440int
4441qla2x00_abort_isp(scsi_qla_host_t *vha)
4442{
4443 int rval;
4444 uint8_t status = 0;
4445 struct qla_hw_data *ha = vha->hw;
4446 struct scsi_qla_host *vp;
4447 struct req_que *req = ha->req_q_map[0];
4448 unsigned long flags;
4449
4450 if (vha->flags.online) {
4451 qla2x00_abort_isp_cleanup(vha);
4452
4453 if (IS_QLA8031(ha)) {
4454 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
4455 "Clearing fcoe driver presence.\n");
4456 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
4457 ql_dbg(ql_dbg_p3p, vha, 0xb073,
4458 "Error while clearing DRV-Presence.\n");
4459 }
4460
4461 if (unlikely(pci_channel_offline(ha->pdev) &&
4462 ha->flags.pci_channel_io_perm_failure)) {
4463 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4464 status = 0;
4465 return status;
4466 }
4467
4468 ha->isp_ops->get_flash_version(vha, req->ring);
4469
4470 ha->isp_ops->nvram_config(vha);
4471
4472 if (!qla2x00_restart_isp(vha)) {
4473 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
4474
4475 if (!atomic_read(&vha->loop_down_timer)) {
4476
4477
4478
4479
4480 vha->marker_needed = 1;
4481 }
4482
4483 vha->flags.online = 1;
4484
4485 ha->isp_ops->enable_intrs(ha);
4486
4487 ha->isp_abort_cnt = 0;
4488 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4489
4490 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
4491 qla2x00_get_fw_version(vha);
4492 if (ha->fce) {
4493 ha->flags.fce_enabled = 1;
4494 memset(ha->fce, 0,
4495 fce_calc_size(ha->fce_bufs));
4496 rval = qla2x00_enable_fce_trace(vha,
4497 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
4498 &ha->fce_bufs);
4499 if (rval) {
4500 ql_log(ql_log_warn, vha, 0x8033,
4501 "Unable to reinitialize FCE "
4502 "(%d).\n", rval);
4503 ha->flags.fce_enabled = 0;
4504 }
4505 }
4506
4507 if (ha->eft) {
4508 memset(ha->eft, 0, EFT_SIZE);
4509 rval = qla2x00_enable_eft_trace(vha,
4510 ha->eft_dma, EFT_NUM_BUFFERS);
4511 if (rval) {
4512 ql_log(ql_log_warn, vha, 0x8034,
4513 "Unable to reinitialize EFT "
4514 "(%d).\n", rval);
4515 }
4516 }
4517 } else {
4518 vha->flags.online = 1;
4519 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
4520 if (ha->isp_abort_cnt == 0) {
4521 ql_log(ql_log_fatal, vha, 0x8035,
4522 "ISP error recover failed - "
4523 "board disabled.\n");
4524
4525
4526
4527
4528 ha->isp_ops->reset_adapter(vha);
4529 vha->flags.online = 0;
4530 clear_bit(ISP_ABORT_RETRY,
4531 &vha->dpc_flags);
4532 status = 0;
4533 } else {
4534 ha->isp_abort_cnt--;
4535 ql_dbg(ql_dbg_taskm, vha, 0x8020,
4536 "ISP abort - retry remaining %d.\n",
4537 ha->isp_abort_cnt);
4538 status = 1;
4539 }
4540 } else {
4541 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
4542 ql_dbg(ql_dbg_taskm, vha, 0x8021,
4543 "ISP error recovery - retrying (%d) "
4544 "more times.\n", ha->isp_abort_cnt);
4545 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4546 status = 1;
4547 }
4548 }
4549
4550 }
4551
4552 if (!status) {
4553 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
4554
4555 spin_lock_irqsave(&ha->vport_slock, flags);
4556 list_for_each_entry(vp, &ha->vp_list, list) {
4557 if (vp->vp_idx) {
4558 atomic_inc(&vp->vref_count);
4559 spin_unlock_irqrestore(&ha->vport_slock, flags);
4560
4561 qla2x00_vp_abort_isp(vp);
4562
4563 spin_lock_irqsave(&ha->vport_slock, flags);
4564 atomic_dec(&vp->vref_count);
4565 }
4566 }
4567 spin_unlock_irqrestore(&ha->vport_slock, flags);
4568
4569 if (IS_QLA8031(ha)) {
4570 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
4571 "Setting back fcoe driver presence.\n");
4572 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
4573 ql_dbg(ql_dbg_p3p, vha, 0xb074,
4574 "Error while setting DRV-Presence.\n");
4575 }
4576 } else {
4577 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
4578 __func__);
4579 }
4580
4581 return(status);
4582}
4583
4584
4585
4586
4587
4588
4589
4590
4591
4592
4593
4594static int
4595qla2x00_restart_isp(scsi_qla_host_t *vha)
4596{
4597 int status = 0;
4598 uint32_t wait_time;
4599 struct qla_hw_data *ha = vha->hw;
4600 struct req_que *req = ha->req_q_map[0];
4601 struct rsp_que *rsp = ha->rsp_q_map[0];
4602 unsigned long flags;
4603
4604
4605 if (qla2x00_isp_firmware(vha)) {
4606 vha->flags.online = 0;
4607 status = ha->isp_ops->chip_diag(vha);
4608 if (!status)
4609 status = qla2x00_setup_chip(vha);
4610 }
4611
4612 if (!status && !(status = qla2x00_init_rings(vha))) {
4613 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
4614 ha->flags.chip_reset_done = 1;
4615
4616 qla25xx_init_queues(ha);
4617
4618 status = qla2x00_fw_ready(vha);
4619 if (!status) {
4620 ql_dbg(ql_dbg_taskm, vha, 0x8031,
4621 "Start configure loop status = %d.\n", status);
4622
4623
4624 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
4625
4626 vha->flags.online = 1;
4627
4628
4629
4630
4631
4632 spin_lock_irqsave(&ha->hardware_lock, flags);
4633 if (qla_tgt_mode_enabled(vha))
4634 qlt_24xx_process_atio_queue(vha);
4635 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4636
4637
4638 wait_time = 256;
4639 do {
4640 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4641 qla2x00_configure_loop(vha);
4642 wait_time--;
4643 } while (!atomic_read(&vha->loop_down_timer) &&
4644 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
4645 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
4646 &vha->dpc_flags)));
4647 }
4648
4649
4650 if ((vha->device_flags & DFLG_NO_CABLE))
4651 status = 0;
4652
4653 ql_dbg(ql_dbg_taskm, vha, 0x8032,
4654 "Configure loop done, status = 0x%x.\n", status);
4655 }
4656 return (status);
4657}
4658
4659static int
4660qla25xx_init_queues(struct qla_hw_data *ha)
4661{
4662 struct rsp_que *rsp = NULL;
4663 struct req_que *req = NULL;
4664 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
4665 int ret = -1;
4666 int i;
4667
4668 for (i = 1; i < ha->max_rsp_queues; i++) {
4669 rsp = ha->rsp_q_map[i];
4670 if (rsp) {
4671 rsp->options &= ~BIT_0;
4672 ret = qla25xx_init_rsp_que(base_vha, rsp);
4673 if (ret != QLA_SUCCESS)
4674 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
4675 "%s Rsp que: %d init failed.\n",
4676 __func__, rsp->id);
4677 else
4678 ql_dbg(ql_dbg_init, base_vha, 0x0100,
4679 "%s Rsp que: %d inited.\n",
4680 __func__, rsp->id);
4681 }
4682 }
4683 for (i = 1; i < ha->max_req_queues; i++) {
4684 req = ha->req_q_map[i];
4685 if (req) {
4686
4687 req->options &= ~BIT_0;
4688 ret = qla25xx_init_req_que(base_vha, req);
4689 if (ret != QLA_SUCCESS)
4690 ql_dbg(ql_dbg_init, base_vha, 0x0101,
4691 "%s Req que: %d init failed.\n",
4692 __func__, req->id);
4693 else
4694 ql_dbg(ql_dbg_init, base_vha, 0x0102,
4695 "%s Req que: %d inited.\n",
4696 __func__, req->id);
4697 }
4698 }
4699 return ret;
4700}
4701
4702
4703
4704
4705
4706
4707
4708
4709void
4710qla2x00_reset_adapter(scsi_qla_host_t *vha)
4711{
4712 unsigned long flags = 0;
4713 struct qla_hw_data *ha = vha->hw;
4714 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
4715
4716 vha->flags.online = 0;
4717 ha->isp_ops->disable_intrs(ha);
4718
4719 spin_lock_irqsave(&ha->hardware_lock, flags);
4720 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC);
4721 RD_REG_WORD(®->hccr);
4722 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC);
4723 RD_REG_WORD(®->hccr);
4724 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4725}
4726
4727void
4728qla24xx_reset_adapter(scsi_qla_host_t *vha)
4729{
4730 unsigned long flags = 0;
4731 struct qla_hw_data *ha = vha->hw;
4732 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4733
4734 if (IS_QLA82XX(ha))
4735 return;
4736
4737 vha->flags.online = 0;
4738 ha->isp_ops->disable_intrs(ha);
4739
4740 spin_lock_irqsave(&ha->hardware_lock, flags);
4741 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET);
4742 RD_REG_DWORD(®->hccr);
4743 WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE);
4744 RD_REG_DWORD(®->hccr);
4745 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4746
4747 if (IS_NOPOLLING_TYPE(ha))
4748 ha->isp_ops->enable_intrs(ha);
4749}
4750
4751
4752
4753
4754static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
4755 struct nvram_24xx *nv)
4756{
4757#ifdef CONFIG_SPARC
4758 struct qla_hw_data *ha = vha->hw;
4759 struct pci_dev *pdev = ha->pdev;
4760 struct device_node *dp = pci_device_to_OF_node(pdev);
4761 const u8 *val;
4762 int len;
4763
4764 val = of_get_property(dp, "port-wwn", &len);
4765 if (val && len >= WWN_SIZE)
4766 memcpy(nv->port_name, val, WWN_SIZE);
4767
4768 val = of_get_property(dp, "node-wwn", &len);
4769 if (val && len >= WWN_SIZE)
4770 memcpy(nv->node_name, val, WWN_SIZE);
4771#endif
4772}
4773
4774int
4775qla24xx_nvram_config(scsi_qla_host_t *vha)
4776{
4777 int rval;
4778 struct init_cb_24xx *icb;
4779 struct nvram_24xx *nv;
4780 uint32_t *dptr;
4781 uint8_t *dptr1, *dptr2;
4782 uint32_t chksum;
4783 uint16_t cnt;
4784 struct qla_hw_data *ha = vha->hw;
4785
4786 rval = QLA_SUCCESS;
4787 icb = (struct init_cb_24xx *)ha->init_cb;
4788 nv = ha->nvram;
4789
4790
4791 if (ha->flags.port0) {
4792 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
4793 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
4794 } else {
4795 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
4796 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
4797 }
4798 ha->nvram_size = sizeof(struct nvram_24xx);
4799 ha->vpd_size = FA_NVRAM_VPD_SIZE;
4800 if (IS_QLA82XX(ha))
4801 ha->vpd_size = FA_VPD_SIZE_82XX;
4802
4803
4804 ha->vpd = ha->nvram + VPD_OFFSET;
4805 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
4806 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
4807
4808
4809 dptr = (uint32_t *)nv;
4810 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
4811 ha->nvram_size);
4812 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
4813 chksum += le32_to_cpu(*dptr++);
4814
4815 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
4816 "Contents of NVRAM\n");
4817 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
4818 (uint8_t *)nv, ha->nvram_size);
4819
4820
4821 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
4822 || nv->id[3] != ' ' ||
4823 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
4824
4825 ql_log(ql_log_warn, vha, 0x006b,
4826 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
4827 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
4828 ql_log(ql_log_warn, vha, 0x006c,
4829 "Falling back to functioning (yet invalid -- WWPN) "
4830 "defaults.\n");
4831
4832
4833
4834
4835 memset(nv, 0, ha->nvram_size);
4836 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
4837 nv->version = __constant_cpu_to_le16(ICB_VERSION);
4838 nv->frame_payload_size = __constant_cpu_to_le16(2048);
4839 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4840 nv->exchange_count = __constant_cpu_to_le16(0);
4841 nv->hard_address = __constant_cpu_to_le16(124);
4842 nv->port_name[0] = 0x21;
4843 nv->port_name[1] = 0x00 + ha->port_no;
4844 nv->port_name[2] = 0x00;
4845 nv->port_name[3] = 0xe0;
4846 nv->port_name[4] = 0x8b;
4847 nv->port_name[5] = 0x1c;
4848 nv->port_name[6] = 0x55;
4849 nv->port_name[7] = 0x86;
4850 nv->node_name[0] = 0x20;
4851 nv->node_name[1] = 0x00;
4852 nv->node_name[2] = 0x00;
4853 nv->node_name[3] = 0xe0;
4854 nv->node_name[4] = 0x8b;
4855 nv->node_name[5] = 0x1c;
4856 nv->node_name[6] = 0x55;
4857 nv->node_name[7] = 0x86;
4858 qla24xx_nvram_wwn_from_ofw(vha, nv);
4859 nv->login_retry_count = __constant_cpu_to_le16(8);
4860 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
4861 nv->login_timeout = __constant_cpu_to_le16(0);
4862 nv->firmware_options_1 =
4863 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
4864 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
4865 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
4866 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
4867 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
4868 nv->efi_parameters = __constant_cpu_to_le32(0);
4869 nv->reset_delay = 5;
4870 nv->max_luns_per_target = __constant_cpu_to_le16(128);
4871 nv->port_down_retry_count = __constant_cpu_to_le16(30);
4872 nv->link_down_timeout = __constant_cpu_to_le16(30);
4873
4874 rval = 1;
4875 }
4876
4877 if (!qla_ini_mode_enabled(vha)) {
4878
4879 nv->firmware_options_1 &= __constant_cpu_to_le32(~BIT_13);
4880
4881 nv->host_p &= __constant_cpu_to_le32(~BIT_10);
4882 }
4883
4884 qlt_24xx_config_nvram_stage1(vha, nv);
4885
4886
4887 memset(icb, 0, ha->init_cb_size);
4888
4889
4890 dptr1 = (uint8_t *)icb;
4891 dptr2 = (uint8_t *)&nv->version;
4892 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
4893 while (cnt--)
4894 *dptr1++ = *dptr2++;
4895
4896 icb->login_retry_count = nv->login_retry_count;
4897 icb->link_down_on_nos = nv->link_down_on_nos;
4898
4899
4900 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
4901 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
4902 cnt = (uint8_t *)&icb->reserved_3 -
4903 (uint8_t *)&icb->interrupt_delay_timer;
4904 while (cnt--)
4905 *dptr1++ = *dptr2++;
4906
4907
4908
4909
4910 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
4911 "QLA2462");
4912
4913 qlt_24xx_config_nvram_stage2(vha, icb);
4914
4915 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
4916
4917 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4918 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4919 }
4920
4921
4922 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
4923
4924
4925
4926
4927 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4928 icb->node_name[0] &= 0xF0;
4929 }
4930
4931
4932 ha->flags.disable_risc_code_load = 0;
4933 ha->flags.enable_lip_reset = 0;
4934 ha->flags.enable_lip_full_login =
4935 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
4936 ha->flags.enable_target_reset =
4937 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
4938 ha->flags.enable_led_scheme = 0;
4939 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
4940
4941 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
4942 (BIT_6 | BIT_5 | BIT_4)) >> 4;
4943
4944 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
4945 sizeof(ha->fw_seriallink_options24));
4946
4947
4948 ha->serial0 = icb->port_name[5];
4949 ha->serial1 = icb->port_name[6];
4950 ha->serial2 = icb->port_name[7];
4951 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4952 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
4953
4954 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4955
4956 ha->retry_count = le16_to_cpu(nv->login_retry_count);
4957
4958
4959 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
4960 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
4961 if (le16_to_cpu(nv->login_timeout) < 4)
4962 nv->login_timeout = __constant_cpu_to_le16(4);
4963 ha->login_timeout = le16_to_cpu(nv->login_timeout);
4964 icb->login_timeout = nv->login_timeout;
4965
4966
4967 ha->r_a_tov = 100;
4968
4969 ha->loop_reset_delay = nv->reset_delay;
4970
4971
4972
4973
4974
4975
4976
4977
4978
4979
4980
4981 if (le16_to_cpu(nv->link_down_timeout) == 0) {
4982 ha->loop_down_abort_time =
4983 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
4984 } else {
4985 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
4986 ha->loop_down_abort_time =
4987 (LOOP_DOWN_TIME - ha->link_down_timeout);
4988 }
4989
4990
4991 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
4992 if (qlport_down_retry)
4993 ha->port_down_retry_count = qlport_down_retry;
4994
4995
4996 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
4997 if (ha->port_down_retry_count ==
4998 le16_to_cpu(nv->port_down_retry_count) &&
4999 ha->port_down_retry_count > 3)
5000 ha->login_retry_count = ha->port_down_retry_count;
5001 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5002 ha->login_retry_count = ha->port_down_retry_count;
5003 if (ql2xloginretrycount)
5004 ha->login_retry_count = ql2xloginretrycount;
5005
5006
5007 if (!vha->flags.init_done) {
5008 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5009 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5010 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5011 le16_to_cpu(icb->interrupt_delay_timer): 2;
5012 }
5013 icb->firmware_options_2 &= __constant_cpu_to_le32(
5014 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
5015 vha->flags.process_response_queue = 0;
5016 if (ha->zio_mode != QLA_ZIO_DISABLED) {
5017 ha->zio_mode = QLA_ZIO_MODE_6;
5018
5019 ql_log(ql_log_info, vha, 0x006f,
5020 "ZIO mode %d enabled; timer delay (%d us).\n",
5021 ha->zio_mode, ha->zio_timer * 100);
5022
5023 icb->firmware_options_2 |= cpu_to_le32(
5024 (uint32_t)ha->zio_mode);
5025 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
5026 vha->flags.process_response_queue = 1;
5027 }
5028
5029 if (rval) {
5030 ql_log(ql_log_warn, vha, 0x0070,
5031 "NVRAM configuration failed.\n");
5032 }
5033 return (rval);
5034}
5035
5036static int
5037qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
5038 uint32_t faddr)
5039{
5040 int rval = QLA_SUCCESS;
5041 int segments, fragment;
5042 uint32_t *dcode, dlen;
5043 uint32_t risc_addr;
5044 uint32_t risc_size;
5045 uint32_t i;
5046 struct qla_hw_data *ha = vha->hw;
5047 struct req_que *req = ha->req_q_map[0];
5048
5049 ql_dbg(ql_dbg_init, vha, 0x008b,
5050 "FW: Loading firmware from flash (%x).\n", faddr);
5051
5052 rval = QLA_SUCCESS;
5053
5054 segments = FA_RISC_CODE_SEGMENTS;
5055 dcode = (uint32_t *)req->ring;
5056 *srisc_addr = 0;
5057
5058
5059 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
5060 for (i = 0; i < 4; i++)
5061 dcode[i] = be32_to_cpu(dcode[i]);
5062 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5063 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5064 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5065 dcode[3] == 0)) {
5066 ql_log(ql_log_fatal, vha, 0x008c,
5067 "Unable to verify the integrity of flash firmware "
5068 "image.\n");
5069 ql_log(ql_log_fatal, vha, 0x008d,
5070 "Firmware data: %08x %08x %08x %08x.\n",
5071 dcode[0], dcode[1], dcode[2], dcode[3]);
5072
5073 return QLA_FUNCTION_FAILED;
5074 }
5075
5076 while (segments && rval == QLA_SUCCESS) {
5077
5078 qla24xx_read_flash_data(vha, dcode, faddr, 4);
5079
5080 risc_addr = be32_to_cpu(dcode[2]);
5081 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5082 risc_size = be32_to_cpu(dcode[3]);
5083
5084 fragment = 0;
5085 while (risc_size > 0 && rval == QLA_SUCCESS) {
5086 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5087 if (dlen > risc_size)
5088 dlen = risc_size;
5089
5090 ql_dbg(ql_dbg_init, vha, 0x008e,
5091 "Loading risc segment@ risc addr %x "
5092 "number of dwords 0x%x offset 0x%x.\n",
5093 risc_addr, dlen, faddr);
5094
5095 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
5096 for (i = 0; i < dlen; i++)
5097 dcode[i] = swab32(dcode[i]);
5098
5099 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5100 dlen);
5101 if (rval) {
5102 ql_log(ql_log_fatal, vha, 0x008f,
5103 "Failed to load segment %d of firmware.\n",
5104 fragment);
5105 break;
5106 }
5107
5108 faddr += dlen;
5109 risc_addr += dlen;
5110 risc_size -= dlen;
5111 fragment++;
5112 }
5113
5114
5115 segments--;
5116 }
5117
5118 return rval;
5119}
5120
5121#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
5122
5123int
5124qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5125{
5126 int rval;
5127 int i, fragment;
5128 uint16_t *wcode, *fwcode;
5129 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
5130 struct fw_blob *blob;
5131 struct qla_hw_data *ha = vha->hw;
5132 struct req_que *req = ha->req_q_map[0];
5133
5134
5135 blob = qla2x00_request_firmware(vha);
5136 if (!blob) {
5137 ql_log(ql_log_info, vha, 0x0083,
5138 "Fimware image unavailable.\n");
5139 ql_log(ql_log_info, vha, 0x0084,
5140 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5141 return QLA_FUNCTION_FAILED;
5142 }
5143
5144 rval = QLA_SUCCESS;
5145
5146 wcode = (uint16_t *)req->ring;
5147 *srisc_addr = 0;
5148 fwcode = (uint16_t *)blob->fw->data;
5149 fwclen = 0;
5150
5151
5152 if (blob->fw->size < 8 * sizeof(uint16_t)) {
5153 ql_log(ql_log_fatal, vha, 0x0085,
5154 "Unable to verify integrity of firmware image (%Zd).\n",
5155 blob->fw->size);
5156 goto fail_fw_integrity;
5157 }
5158 for (i = 0; i < 4; i++)
5159 wcode[i] = be16_to_cpu(fwcode[i + 4]);
5160 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
5161 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
5162 wcode[2] == 0 && wcode[3] == 0)) {
5163 ql_log(ql_log_fatal, vha, 0x0086,
5164 "Unable to verify integrity of firmware image.\n");
5165 ql_log(ql_log_fatal, vha, 0x0087,
5166 "Firmware data: %04x %04x %04x %04x.\n",
5167 wcode[0], wcode[1], wcode[2], wcode[3]);
5168 goto fail_fw_integrity;
5169 }
5170
5171 seg = blob->segs;
5172 while (*seg && rval == QLA_SUCCESS) {
5173 risc_addr = *seg;
5174 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
5175 risc_size = be16_to_cpu(fwcode[3]);
5176
5177
5178 fwclen += risc_size * sizeof(uint16_t);
5179 if (blob->fw->size < fwclen) {
5180 ql_log(ql_log_fatal, vha, 0x0088,
5181 "Unable to verify integrity of firmware image "
5182 "(%Zd).\n", blob->fw->size);
5183 goto fail_fw_integrity;
5184 }
5185
5186 fragment = 0;
5187 while (risc_size > 0 && rval == QLA_SUCCESS) {
5188 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
5189 if (wlen > risc_size)
5190 wlen = risc_size;
5191 ql_dbg(ql_dbg_init, vha, 0x0089,
5192 "Loading risc segment@ risc addr %x number of "
5193 "words 0x%x.\n", risc_addr, wlen);
5194
5195 for (i = 0; i < wlen; i++)
5196 wcode[i] = swab16(fwcode[i]);
5197
5198 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5199 wlen);
5200 if (rval) {
5201 ql_log(ql_log_fatal, vha, 0x008a,
5202 "Failed to load segment %d of firmware.\n",
5203 fragment);
5204 break;
5205 }
5206
5207 fwcode += wlen;
5208 risc_addr += wlen;
5209 risc_size -= wlen;
5210 fragment++;
5211 }
5212
5213
5214 seg++;
5215 }
5216 return rval;
5217
5218fail_fw_integrity:
5219 return QLA_FUNCTION_FAILED;
5220}
5221
5222static int
5223qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5224{
5225 int rval;
5226 int segments, fragment;
5227 uint32_t *dcode, dlen;
5228 uint32_t risc_addr;
5229 uint32_t risc_size;
5230 uint32_t i;
5231 struct fw_blob *blob;
5232 uint32_t *fwcode, fwclen;
5233 struct qla_hw_data *ha = vha->hw;
5234 struct req_que *req = ha->req_q_map[0];
5235
5236
5237 blob = qla2x00_request_firmware(vha);
5238 if (!blob) {
5239 ql_log(ql_log_warn, vha, 0x0090,
5240 "Fimware image unavailable.\n");
5241 ql_log(ql_log_warn, vha, 0x0091,
5242 "Firmware images can be retrieved from: "
5243 QLA_FW_URL ".\n");
5244
5245 return QLA_FUNCTION_FAILED;
5246 }
5247
5248 ql_dbg(ql_dbg_init, vha, 0x0092,
5249 "FW: Loading via request-firmware.\n");
5250
5251 rval = QLA_SUCCESS;
5252
5253 segments = FA_RISC_CODE_SEGMENTS;
5254 dcode = (uint32_t *)req->ring;
5255 *srisc_addr = 0;
5256 fwcode = (uint32_t *)blob->fw->data;
5257 fwclen = 0;
5258
5259
5260 if (blob->fw->size < 8 * sizeof(uint32_t)) {
5261 ql_log(ql_log_fatal, vha, 0x0093,
5262 "Unable to verify integrity of firmware image (%Zd).\n",
5263 blob->fw->size);
5264 goto fail_fw_integrity;
5265 }
5266 for (i = 0; i < 4; i++)
5267 dcode[i] = be32_to_cpu(fwcode[i + 4]);
5268 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5269 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5270 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5271 dcode[3] == 0)) {
5272 ql_log(ql_log_fatal, vha, 0x0094,
5273 "Unable to verify integrity of firmware image (%Zd).\n",
5274 blob->fw->size);
5275 ql_log(ql_log_fatal, vha, 0x0095,
5276 "Firmware data: %08x %08x %08x %08x.\n",
5277 dcode[0], dcode[1], dcode[2], dcode[3]);
5278 goto fail_fw_integrity;
5279 }
5280
5281 while (segments && rval == QLA_SUCCESS) {
5282 risc_addr = be32_to_cpu(fwcode[2]);
5283 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5284 risc_size = be32_to_cpu(fwcode[3]);
5285
5286
5287 fwclen += risc_size * sizeof(uint32_t);
5288 if (blob->fw->size < fwclen) {
5289 ql_log(ql_log_fatal, vha, 0x0096,
5290 "Unable to verify integrity of firmware image "
5291 "(%Zd).\n", blob->fw->size);
5292
5293 goto fail_fw_integrity;
5294 }
5295
5296 fragment = 0;
5297 while (risc_size > 0 && rval == QLA_SUCCESS) {
5298 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5299 if (dlen > risc_size)
5300 dlen = risc_size;
5301
5302 ql_dbg(ql_dbg_init, vha, 0x0097,
5303 "Loading risc segment@ risc addr %x "
5304 "number of dwords 0x%x.\n", risc_addr, dlen);
5305
5306 for (i = 0; i < dlen; i++)
5307 dcode[i] = swab32(fwcode[i]);
5308
5309 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5310 dlen);
5311 if (rval) {
5312 ql_log(ql_log_fatal, vha, 0x0098,
5313 "Failed to load segment %d of firmware.\n",
5314 fragment);
5315 break;
5316 }
5317
5318 fwcode += dlen;
5319 risc_addr += dlen;
5320 risc_size -= dlen;
5321 fragment++;
5322 }
5323
5324
5325 segments--;
5326 }
5327 return rval;
5328
5329fail_fw_integrity:
5330 return QLA_FUNCTION_FAILED;
5331}
5332
5333int
5334qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5335{
5336 int rval;
5337
5338 if (ql2xfwloadbin == 1)
5339 return qla81xx_load_risc(vha, srisc_addr);
5340
5341
5342
5343
5344
5345
5346 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5347 if (rval == QLA_SUCCESS)
5348 return rval;
5349
5350 return qla24xx_load_risc_flash(vha, srisc_addr,
5351 vha->hw->flt_region_fw);
5352}
5353
5354int
5355qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5356{
5357 int rval;
5358 struct qla_hw_data *ha = vha->hw;
5359
5360 if (ql2xfwloadbin == 2)
5361 goto try_blob_fw;
5362
5363
5364
5365
5366
5367
5368
5369 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
5370 if (rval == QLA_SUCCESS)
5371 return rval;
5372
5373try_blob_fw:
5374 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5375 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
5376 return rval;
5377
5378 ql_log(ql_log_info, vha, 0x0099,
5379 "Attempting to fallback to golden firmware.\n");
5380 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
5381 if (rval != QLA_SUCCESS)
5382 return rval;
5383
5384 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
5385 ha->flags.running_gold_fw = 1;
5386 return rval;
5387}
5388
5389void
5390qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
5391{
5392 int ret, retries;
5393 struct qla_hw_data *ha = vha->hw;
5394
5395 if (ha->flags.pci_channel_io_perm_failure)
5396 return;
5397 if (!IS_FWI2_CAPABLE(ha))
5398 return;
5399 if (!ha->fw_major_version)
5400 return;
5401
5402 ret = qla2x00_stop_firmware(vha);
5403 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
5404 ret != QLA_INVALID_COMMAND && retries ; retries--) {
5405 ha->isp_ops->reset_chip(vha);
5406 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
5407 continue;
5408 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
5409 continue;
5410 ql_log(ql_log_info, vha, 0x8015,
5411 "Attempting retry of stop-firmware command.\n");
5412 ret = qla2x00_stop_firmware(vha);
5413 }
5414}
5415
5416int
5417qla24xx_configure_vhba(scsi_qla_host_t *vha)
5418{
5419 int rval = QLA_SUCCESS;
5420 int rval2;
5421 uint16_t mb[MAILBOX_REGISTER_COUNT];
5422 struct qla_hw_data *ha = vha->hw;
5423 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
5424 struct req_que *req;
5425 struct rsp_que *rsp;
5426
5427 if (!vha->vp_idx)
5428 return -EINVAL;
5429
5430 rval = qla2x00_fw_ready(base_vha);
5431 if (ha->flags.cpu_affinity_enabled)
5432 req = ha->req_q_map[0];
5433 else
5434 req = vha->req;
5435 rsp = req->rsp;
5436
5437 if (rval == QLA_SUCCESS) {
5438 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5439 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
5440 }
5441
5442 vha->flags.management_server_logged_in = 0;
5443
5444
5445 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
5446 BIT_1);
5447 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5448 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
5449 ql_dbg(ql_dbg_init, vha, 0x0120,
5450 "Failed SNS login: loop_id=%x, rval2=%d\n",
5451 NPH_SNS, rval2);
5452 else
5453 ql_dbg(ql_dbg_init, vha, 0x0103,
5454 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
5455 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
5456 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
5457 return (QLA_FUNCTION_FAILED);
5458 }
5459
5460 atomic_set(&vha->loop_down_timer, 0);
5461 atomic_set(&vha->loop_state, LOOP_UP);
5462 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5463 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5464 rval = qla2x00_loop_resync(base_vha);
5465
5466 return rval;
5467}
5468
5469
5470
5471static LIST_HEAD(qla_cs84xx_list);
5472static DEFINE_MUTEX(qla_cs84xx_mutex);
5473
5474static struct qla_chip_state_84xx *
5475qla84xx_get_chip(struct scsi_qla_host *vha)
5476{
5477 struct qla_chip_state_84xx *cs84xx;
5478 struct qla_hw_data *ha = vha->hw;
5479
5480 mutex_lock(&qla_cs84xx_mutex);
5481
5482
5483 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
5484 if (cs84xx->bus == ha->pdev->bus) {
5485 kref_get(&cs84xx->kref);
5486 goto done;
5487 }
5488 }
5489
5490 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
5491 if (!cs84xx)
5492 goto done;
5493
5494 kref_init(&cs84xx->kref);
5495 spin_lock_init(&cs84xx->access_lock);
5496 mutex_init(&cs84xx->fw_update_mutex);
5497 cs84xx->bus = ha->pdev->bus;
5498
5499 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
5500done:
5501 mutex_unlock(&qla_cs84xx_mutex);
5502 return cs84xx;
5503}
5504
5505static void
5506__qla84xx_chip_release(struct kref *kref)
5507{
5508 struct qla_chip_state_84xx *cs84xx =
5509 container_of(kref, struct qla_chip_state_84xx, kref);
5510
5511 mutex_lock(&qla_cs84xx_mutex);
5512 list_del(&cs84xx->list);
5513 mutex_unlock(&qla_cs84xx_mutex);
5514 kfree(cs84xx);
5515}
5516
5517void
5518qla84xx_put_chip(struct scsi_qla_host *vha)
5519{
5520 struct qla_hw_data *ha = vha->hw;
5521 if (ha->cs84xx)
5522 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
5523}
5524
5525static int
5526qla84xx_init_chip(scsi_qla_host_t *vha)
5527{
5528 int rval;
5529 uint16_t status[2];
5530 struct qla_hw_data *ha = vha->hw;
5531
5532 mutex_lock(&ha->cs84xx->fw_update_mutex);
5533
5534 rval = qla84xx_verify_chip(vha, status);
5535
5536 mutex_unlock(&ha->cs84xx->fw_update_mutex);
5537
5538 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
5539 QLA_SUCCESS;
5540}
5541
5542
5543
5544int
5545qla81xx_nvram_config(scsi_qla_host_t *vha)
5546{
5547 int rval;
5548 struct init_cb_81xx *icb;
5549 struct nvram_81xx *nv;
5550 uint32_t *dptr;
5551 uint8_t *dptr1, *dptr2;
5552 uint32_t chksum;
5553 uint16_t cnt;
5554 struct qla_hw_data *ha = vha->hw;
5555
5556 rval = QLA_SUCCESS;
5557 icb = (struct init_cb_81xx *)ha->init_cb;
5558 nv = ha->nvram;
5559
5560
5561 ha->nvram_size = sizeof(struct nvram_81xx);
5562 ha->vpd_size = FA_NVRAM_VPD_SIZE;
5563
5564
5565 ha->vpd = ha->nvram + VPD_OFFSET;
5566 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
5567 ha->vpd_size);
5568
5569
5570 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
5571 ha->nvram_size);
5572 dptr = (uint32_t *)nv;
5573 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
5574 chksum += le32_to_cpu(*dptr++);
5575
5576 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
5577 "Contents of NVRAM:\n");
5578 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
5579 (uint8_t *)nv, ha->nvram_size);
5580
5581
5582 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5583 || nv->id[3] != ' ' ||
5584 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
5585
5586 ql_log(ql_log_info, vha, 0x0073,
5587 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
5588 "version=0x%x.\n", chksum, nv->id[0],
5589 le16_to_cpu(nv->nvram_version));
5590 ql_log(ql_log_info, vha, 0x0074,
5591 "Falling back to functioning (yet invalid -- WWPN) "
5592 "defaults.\n");
5593
5594
5595
5596
5597 memset(nv, 0, ha->nvram_size);
5598 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
5599 nv->version = __constant_cpu_to_le16(ICB_VERSION);
5600 nv->frame_payload_size = __constant_cpu_to_le16(2048);
5601 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5602 nv->exchange_count = __constant_cpu_to_le16(0);
5603 nv->port_name[0] = 0x21;
5604 nv->port_name[1] = 0x00 + ha->port_no;
5605 nv->port_name[2] = 0x00;
5606 nv->port_name[3] = 0xe0;
5607 nv->port_name[4] = 0x8b;
5608 nv->port_name[5] = 0x1c;
5609 nv->port_name[6] = 0x55;
5610 nv->port_name[7] = 0x86;
5611 nv->node_name[0] = 0x20;
5612 nv->node_name[1] = 0x00;
5613 nv->node_name[2] = 0x00;
5614 nv->node_name[3] = 0xe0;
5615 nv->node_name[4] = 0x8b;
5616 nv->node_name[5] = 0x1c;
5617 nv->node_name[6] = 0x55;
5618 nv->node_name[7] = 0x86;
5619 nv->login_retry_count = __constant_cpu_to_le16(8);
5620 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
5621 nv->login_timeout = __constant_cpu_to_le16(0);
5622 nv->firmware_options_1 =
5623 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5624 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
5625 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
5626 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
5627 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
5628 nv->efi_parameters = __constant_cpu_to_le32(0);
5629 nv->reset_delay = 5;
5630 nv->max_luns_per_target = __constant_cpu_to_le16(128);
5631 nv->port_down_retry_count = __constant_cpu_to_le16(30);
5632 nv->link_down_timeout = __constant_cpu_to_le16(180);
5633 nv->enode_mac[0] = 0x00;
5634 nv->enode_mac[1] = 0xC0;
5635 nv->enode_mac[2] = 0xDD;
5636 nv->enode_mac[3] = 0x04;
5637 nv->enode_mac[4] = 0x05;
5638 nv->enode_mac[5] = 0x06 + ha->port_no;
5639
5640 rval = 1;
5641 }
5642
5643 if (IS_T10_PI_CAPABLE(ha))
5644 nv->frame_payload_size &= ~7;
5645
5646 qlt_81xx_config_nvram_stage1(vha, nv);
5647
5648
5649 memset(icb, 0, ha->init_cb_size);
5650
5651
5652 dptr1 = (uint8_t *)icb;
5653 dptr2 = (uint8_t *)&nv->version;
5654 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5655 while (cnt--)
5656 *dptr1++ = *dptr2++;
5657
5658 icb->login_retry_count = nv->login_retry_count;
5659
5660
5661 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5662 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5663 cnt = (uint8_t *)&icb->reserved_5 -
5664 (uint8_t *)&icb->interrupt_delay_timer;
5665 while (cnt--)
5666 *dptr1++ = *dptr2++;
5667
5668 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
5669
5670 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
5671 icb->enode_mac[0] = 0x00;
5672 icb->enode_mac[1] = 0xC0;
5673 icb->enode_mac[2] = 0xDD;
5674 icb->enode_mac[3] = 0x04;
5675 icb->enode_mac[4] = 0x05;
5676 icb->enode_mac[5] = 0x06 + ha->port_no;
5677 }
5678
5679
5680 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
5681
5682
5683
5684
5685 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
5686 "QLE8XXX");
5687
5688 qlt_81xx_config_nvram_stage2(vha, icb);
5689
5690
5691 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
5692 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
5693 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
5694 }
5695
5696
5697 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
5698
5699
5700
5701
5702 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
5703 icb->node_name[0] &= 0xF0;
5704 }
5705
5706
5707 ha->flags.disable_risc_code_load = 0;
5708 ha->flags.enable_lip_reset = 0;
5709 ha->flags.enable_lip_full_login =
5710 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
5711 ha->flags.enable_target_reset =
5712 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
5713 ha->flags.enable_led_scheme = 0;
5714 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
5715
5716 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
5717 (BIT_6 | BIT_5 | BIT_4)) >> 4;
5718
5719
5720 ha->serial0 = icb->port_name[5];
5721 ha->serial1 = icb->port_name[6];
5722 ha->serial2 = icb->port_name[7];
5723 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
5724 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
5725
5726 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5727
5728 ha->retry_count = le16_to_cpu(nv->login_retry_count);
5729
5730
5731 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
5732 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
5733 if (le16_to_cpu(nv->login_timeout) < 4)
5734 nv->login_timeout = __constant_cpu_to_le16(4);
5735 ha->login_timeout = le16_to_cpu(nv->login_timeout);
5736 icb->login_timeout = nv->login_timeout;
5737
5738
5739 ha->r_a_tov = 100;
5740
5741 ha->loop_reset_delay = nv->reset_delay;
5742
5743
5744
5745
5746
5747
5748
5749
5750
5751
5752
5753 if (le16_to_cpu(nv->link_down_timeout) == 0) {
5754 ha->loop_down_abort_time =
5755 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5756 } else {
5757 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
5758 ha->loop_down_abort_time =
5759 (LOOP_DOWN_TIME - ha->link_down_timeout);
5760 }
5761
5762
5763 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
5764 if (qlport_down_retry)
5765 ha->port_down_retry_count = qlport_down_retry;
5766
5767
5768 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
5769 if (ha->port_down_retry_count ==
5770 le16_to_cpu(nv->port_down_retry_count) &&
5771 ha->port_down_retry_count > 3)
5772 ha->login_retry_count = ha->port_down_retry_count;
5773 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5774 ha->login_retry_count = ha->port_down_retry_count;
5775 if (ql2xloginretrycount)
5776 ha->login_retry_count = ql2xloginretrycount;
5777
5778
5779 if (!vha->hw->flags.msix_enabled && IS_QLA83XX(ha))
5780 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22);
5781
5782
5783 if (!vha->flags.init_done) {
5784 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5785 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5786 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5787 le16_to_cpu(icb->interrupt_delay_timer): 2;
5788 }
5789 icb->firmware_options_2 &= __constant_cpu_to_le32(
5790 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
5791 vha->flags.process_response_queue = 0;
5792 if (ha->zio_mode != QLA_ZIO_DISABLED) {
5793 ha->zio_mode = QLA_ZIO_MODE_6;
5794
5795 ql_log(ql_log_info, vha, 0x0075,
5796 "ZIO mode %d enabled; timer delay (%d us).\n",
5797 ha->zio_mode,
5798 ha->zio_timer * 100);
5799
5800 icb->firmware_options_2 |= cpu_to_le32(
5801 (uint32_t)ha->zio_mode);
5802 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
5803 vha->flags.process_response_queue = 1;
5804 }
5805
5806 if (rval) {
5807 ql_log(ql_log_warn, vha, 0x0076,
5808 "NVRAM configuration failed.\n");
5809 }
5810 return (rval);
5811}
5812
5813int
5814qla82xx_restart_isp(scsi_qla_host_t *vha)
5815{
5816 int status, rval;
5817 uint32_t wait_time;
5818 struct qla_hw_data *ha = vha->hw;
5819 struct req_que *req = ha->req_q_map[0];
5820 struct rsp_que *rsp = ha->rsp_q_map[0];
5821 struct scsi_qla_host *vp;
5822 unsigned long flags;
5823
5824 status = qla2x00_init_rings(vha);
5825 if (!status) {
5826 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5827 ha->flags.chip_reset_done = 1;
5828
5829 status = qla2x00_fw_ready(vha);
5830 if (!status) {
5831 ql_log(ql_log_info, vha, 0x803c,
5832 "Start configure loop, status =%d.\n", status);
5833
5834
5835 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
5836
5837 vha->flags.online = 1;
5838
5839 wait_time = 256;
5840 do {
5841 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5842 qla2x00_configure_loop(vha);
5843 wait_time--;
5844 } while (!atomic_read(&vha->loop_down_timer) &&
5845 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) &&
5846 wait_time &&
5847 (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)));
5848 }
5849
5850
5851 if ((vha->device_flags & DFLG_NO_CABLE))
5852 status = 0;
5853
5854 ql_log(ql_log_info, vha, 0x8000,
5855 "Configure loop done, status = 0x%x.\n", status);
5856 }
5857
5858 if (!status) {
5859 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5860
5861 if (!atomic_read(&vha->loop_down_timer)) {
5862
5863
5864
5865
5866 vha->marker_needed = 1;
5867 }
5868
5869 vha->flags.online = 1;
5870
5871 ha->isp_ops->enable_intrs(ha);
5872
5873 ha->isp_abort_cnt = 0;
5874 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
5875
5876
5877 status = qla82xx_check_md_needed(vha);
5878
5879 if (ha->fce) {
5880 ha->flags.fce_enabled = 1;
5881 memset(ha->fce, 0,
5882 fce_calc_size(ha->fce_bufs));
5883 rval = qla2x00_enable_fce_trace(vha,
5884 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
5885 &ha->fce_bufs);
5886 if (rval) {
5887 ql_log(ql_log_warn, vha, 0x8001,
5888 "Unable to reinitialize FCE (%d).\n",
5889 rval);
5890 ha->flags.fce_enabled = 0;
5891 }
5892 }
5893
5894 if (ha->eft) {
5895 memset(ha->eft, 0, EFT_SIZE);
5896 rval = qla2x00_enable_eft_trace(vha,
5897 ha->eft_dma, EFT_NUM_BUFFERS);
5898 if (rval) {
5899 ql_log(ql_log_warn, vha, 0x8010,
5900 "Unable to reinitialize EFT (%d).\n",
5901 rval);
5902 }
5903 }
5904 }
5905
5906 if (!status) {
5907 ql_dbg(ql_dbg_taskm, vha, 0x8011,
5908 "qla82xx_restart_isp succeeded.\n");
5909
5910 spin_lock_irqsave(&ha->vport_slock, flags);
5911 list_for_each_entry(vp, &ha->vp_list, list) {
5912 if (vp->vp_idx) {
5913 atomic_inc(&vp->vref_count);
5914 spin_unlock_irqrestore(&ha->vport_slock, flags);
5915
5916 qla2x00_vp_abort_isp(vp);
5917
5918 spin_lock_irqsave(&ha->vport_slock, flags);
5919 atomic_dec(&vp->vref_count);
5920 }
5921 }
5922 spin_unlock_irqrestore(&ha->vport_slock, flags);
5923
5924 } else {
5925 ql_log(ql_log_warn, vha, 0x8016,
5926 "qla82xx_restart_isp **** FAILED ****.\n");
5927 }
5928
5929 return status;
5930}
5931
5932void
5933qla81xx_update_fw_options(scsi_qla_host_t *vha)
5934{
5935 struct qla_hw_data *ha = vha->hw;
5936
5937 if (!ql2xetsenable)
5938 return;
5939
5940
5941 memset(ha->fw_options, 0, sizeof(ha->fw_options));
5942 ha->fw_options[2] |= BIT_9;
5943 qla2x00_set_fw_options(vha, ha->fw_options);
5944}
5945
5946
5947
5948
5949
5950
5951
5952
5953
5954
5955
5956
5957
5958
5959
5960
5961
5962
5963
5964static int
5965qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
5966{
5967 int i, entries;
5968 uint8_t pid_match, wwn_match;
5969 int priority;
5970 uint32_t pid1, pid2;
5971 uint64_t wwn1, wwn2;
5972 struct qla_fcp_prio_entry *pri_entry;
5973 struct qla_hw_data *ha = vha->hw;
5974
5975 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
5976 return -1;
5977
5978 priority = -1;
5979 entries = ha->fcp_prio_cfg->num_entries;
5980 pri_entry = &ha->fcp_prio_cfg->entry[0];
5981
5982 for (i = 0; i < entries; i++) {
5983 pid_match = wwn_match = 0;
5984
5985 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
5986 pri_entry++;
5987 continue;
5988 }
5989
5990
5991 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
5992 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
5993 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
5994 if (pid1 == INVALID_PORT_ID)
5995 pid_match++;
5996 else if (pid1 == pid2)
5997 pid_match++;
5998 }
5999
6000
6001 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
6002 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
6003 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
6004 if (pid1 == INVALID_PORT_ID)
6005 pid_match++;
6006 else if (pid1 == pid2)
6007 pid_match++;
6008 }
6009
6010
6011 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
6012 wwn1 = wwn_to_u64(vha->port_name);
6013 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
6014 if (wwn2 == (uint64_t)-1)
6015 wwn_match++;
6016 else if (wwn1 == wwn2)
6017 wwn_match++;
6018 }
6019
6020
6021 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
6022 wwn1 = wwn_to_u64(fcport->port_name);
6023 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
6024 if (wwn2 == (uint64_t)-1)
6025 wwn_match++;
6026 else if (wwn1 == wwn2)
6027 wwn_match++;
6028 }
6029
6030 if (pid_match == 2 || wwn_match == 2) {
6031
6032 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
6033 priority = pri_entry->tag;
6034 break;
6035 }
6036
6037 pri_entry++;
6038 }
6039
6040 return priority;
6041}
6042
6043
6044
6045
6046
6047
6048
6049
6050
6051
6052
6053
6054
6055
6056
6057int
6058qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
6059{
6060 int ret;
6061 int priority;
6062 uint16_t mb[5];
6063
6064 if (fcport->port_type != FCT_TARGET ||
6065 fcport->loop_id == FC_NO_LOOP_ID)
6066 return QLA_FUNCTION_FAILED;
6067
6068 priority = qla24xx_get_fcp_prio(vha, fcport);
6069 if (priority < 0)
6070 return QLA_FUNCTION_FAILED;
6071
6072 if (IS_QLA82XX(vha->hw)) {
6073 fcport->fcp_prio = priority & 0xf;
6074 return QLA_SUCCESS;
6075 }
6076
6077 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
6078 if (ret == QLA_SUCCESS) {
6079 if (fcport->fcp_prio != priority)
6080 ql_dbg(ql_dbg_user, vha, 0x709e,
6081 "Updated FCP_CMND priority - value=%d loop_id=%d "
6082 "port_id=%02x%02x%02x.\n", priority,
6083 fcport->loop_id, fcport->d_id.b.domain,
6084 fcport->d_id.b.area, fcport->d_id.b.al_pa);
6085 fcport->fcp_prio = priority & 0xf;
6086 } else
6087 ql_dbg(ql_dbg_user, vha, 0x704f,
6088 "Unable to update FCP_CMND priority - ret=0x%x for "
6089 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
6090 fcport->d_id.b.domain, fcport->d_id.b.area,
6091 fcport->d_id.b.al_pa);
6092 return ret;
6093}
6094
6095
6096
6097
6098
6099
6100
6101
6102
6103
6104
6105
6106
6107
6108int
6109qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
6110{
6111 int ret;
6112 fc_port_t *fcport;
6113
6114 ret = QLA_FUNCTION_FAILED;
6115
6116 list_for_each_entry(fcport, &vha->vp_fcports, list)
6117 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
6118
6119 return ret;
6120}
6121