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35
36#include "ufshcd.h"
37
38enum {
39 UFSHCD_MAX_CHANNEL = 0,
40 UFSHCD_MAX_ID = 1,
41 UFSHCD_MAX_LUNS = 8,
42 UFSHCD_CMD_PER_LUN = 32,
43 UFSHCD_CAN_QUEUE = 32,
44};
45
46
47enum {
48 UFSHCD_STATE_OPERATIONAL,
49 UFSHCD_STATE_RESET,
50 UFSHCD_STATE_ERROR,
51};
52
53
54enum {
55 UFSHCD_INT_DISABLE,
56 UFSHCD_INT_ENABLE,
57 UFSHCD_INT_CLEAR,
58};
59
60
61enum {
62 INT_AGGR_RESET,
63 INT_AGGR_CONFIG,
64};
65
66
67
68
69
70
71
72static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
73{
74 return readl(hba->mmio_base + REG_UFS_VERSION);
75}
76
77
78
79
80
81
82
83
84static inline int ufshcd_is_device_present(u32 reg_hcs)
85{
86 return (DEVICE_PRESENT & reg_hcs) ? 1 : 0;
87}
88
89
90
91
92
93
94
95
96static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
97{
98 return lrbp->utr_descriptor_ptr->header.dword_2 & MASK_OCS;
99}
100
101
102
103
104
105
106
107
108static inline int
109ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
110{
111 return task_req_descp->header.dword_2 & MASK_OCS;
112}
113
114
115
116
117
118
119
120
121static inline int ufshcd_get_tm_free_slot(struct ufs_hba *hba)
122{
123 return find_first_zero_bit(&hba->outstanding_tasks, hba->nutmrs);
124}
125
126
127
128
129
130
131static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
132{
133 writel(~(1 << pos),
134 (hba->mmio_base + REG_UTP_TRANSFER_REQ_LIST_CLEAR));
135}
136
137
138
139
140
141
142
143static inline int ufshcd_get_lists_status(u32 reg)
144{
145
146
147
148
149
150
151
152
153
154
155
156 return (((reg) & (0xFF)) >> 1) ^ (0x07);
157}
158
159
160
161
162
163
164
165
166static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
167{
168 return readl(hba->mmio_base + REG_UIC_COMMAND_ARG_2) &
169 MASK_UIC_COMMAND_RESULT;
170}
171
172
173
174
175
176
177static inline void ufshcd_free_hba_memory(struct ufs_hba *hba)
178{
179 size_t utmrdl_size, utrdl_size, ucdl_size;
180
181 kfree(hba->lrb);
182
183 if (hba->utmrdl_base_addr) {
184 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
185 dma_free_coherent(hba->dev, utmrdl_size,
186 hba->utmrdl_base_addr, hba->utmrdl_dma_addr);
187 }
188
189 if (hba->utrdl_base_addr) {
190 utrdl_size =
191 (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
192 dma_free_coherent(hba->dev, utrdl_size,
193 hba->utrdl_base_addr, hba->utrdl_dma_addr);
194 }
195
196 if (hba->ucdl_base_addr) {
197 ucdl_size =
198 (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
199 dma_free_coherent(hba->dev, ucdl_size,
200 hba->ucdl_base_addr, hba->ucdl_dma_addr);
201 }
202}
203
204
205
206
207
208
209
210
211
212static inline int
213ufshcd_is_valid_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
214{
215 return ((be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24) ==
216 UPIU_TRANSACTION_RESPONSE) ? 0 : DID_ERROR << 16;
217}
218
219
220
221
222
223
224
225
226static inline int
227ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
228{
229 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
230}
231
232
233
234
235
236
237
238
239
240
241static inline void
242ufshcd_config_int_aggr(struct ufs_hba *hba, int option)
243{
244 switch (option) {
245 case INT_AGGR_RESET:
246 writel((INT_AGGR_ENABLE |
247 INT_AGGR_COUNTER_AND_TIMER_RESET),
248 (hba->mmio_base +
249 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL));
250 break;
251 case INT_AGGR_CONFIG:
252 writel((INT_AGGR_ENABLE |
253 INT_AGGR_PARAM_WRITE |
254 INT_AGGR_COUNTER_THRESHOLD_VALUE |
255 INT_AGGR_TIMEOUT_VALUE),
256 (hba->mmio_base +
257 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL));
258 break;
259 }
260}
261
262
263
264
265
266
267
268static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
269{
270 writel(UTP_TASK_REQ_LIST_RUN_STOP_BIT,
271 (hba->mmio_base +
272 REG_UTP_TASK_REQ_LIST_RUN_STOP));
273 writel(UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
274 (hba->mmio_base +
275 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP));
276}
277
278
279
280
281
282static inline void ufshcd_hba_start(struct ufs_hba *hba)
283{
284 writel(CONTROLLER_ENABLE , (hba->mmio_base + REG_CONTROLLER_ENABLE));
285}
286
287
288
289
290
291
292
293static inline int ufshcd_is_hba_active(struct ufs_hba *hba)
294{
295 return (readl(hba->mmio_base + REG_CONTROLLER_ENABLE) & 0x1) ? 0 : 1;
296}
297
298
299
300
301
302
303static inline
304void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
305{
306 __set_bit(task_tag, &hba->outstanding_reqs);
307 writel((1 << task_tag),
308 (hba->mmio_base + REG_UTP_TRANSFER_REQ_DOOR_BELL));
309}
310
311
312
313
314
315static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
316{
317 int len;
318 if (lrbp->sense_buffer) {
319 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sense_data_len);
320 memcpy(lrbp->sense_buffer,
321 lrbp->ucd_rsp_ptr->sense_data,
322 min_t(int, len, SCSI_SENSE_BUFFERSIZE));
323 }
324}
325
326
327
328
329
330static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
331{
332 hba->capabilities =
333 readl(hba->mmio_base + REG_CONTROLLER_CAPABILITIES);
334
335
336 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
337 hba->nutmrs =
338 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
339}
340
341
342
343
344
345
346static inline void
347ufshcd_send_uic_command(struct ufs_hba *hba, struct uic_command *uic_cmnd)
348{
349
350 writel(uic_cmnd->argument1,
351 (hba->mmio_base + REG_UIC_COMMAND_ARG_1));
352 writel(uic_cmnd->argument2,
353 (hba->mmio_base + REG_UIC_COMMAND_ARG_2));
354 writel(uic_cmnd->argument3,
355 (hba->mmio_base + REG_UIC_COMMAND_ARG_3));
356
357
358 writel((uic_cmnd->command & COMMAND_OPCODE_MASK),
359 (hba->mmio_base + REG_UIC_COMMAND));
360}
361
362
363
364
365
366
367
368static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
369{
370 struct ufshcd_sg_entry *prd_table;
371 struct scatterlist *sg;
372 struct scsi_cmnd *cmd;
373 int sg_segments;
374 int i;
375
376 cmd = lrbp->cmd;
377 sg_segments = scsi_dma_map(cmd);
378 if (sg_segments < 0)
379 return sg_segments;
380
381 if (sg_segments) {
382 lrbp->utr_descriptor_ptr->prd_table_length =
383 cpu_to_le16((u16) (sg_segments));
384
385 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
386
387 scsi_for_each_sg(cmd, sg, sg_segments, i) {
388 prd_table[i].size =
389 cpu_to_le32(((u32) sg_dma_len(sg))-1);
390 prd_table[i].base_addr =
391 cpu_to_le32(lower_32_bits(sg->dma_address));
392 prd_table[i].upper_addr =
393 cpu_to_le32(upper_32_bits(sg->dma_address));
394 }
395 } else {
396 lrbp->utr_descriptor_ptr->prd_table_length = 0;
397 }
398
399 return 0;
400}
401
402
403
404
405
406
407static void ufshcd_int_config(struct ufs_hba *hba, u32 option)
408{
409 switch (option) {
410 case UFSHCD_INT_ENABLE:
411 writel(hba->int_enable_mask,
412 (hba->mmio_base + REG_INTERRUPT_ENABLE));
413 break;
414 case UFSHCD_INT_DISABLE:
415 if (hba->ufs_version == UFSHCI_VERSION_10)
416 writel(INTERRUPT_DISABLE_MASK_10,
417 (hba->mmio_base + REG_INTERRUPT_ENABLE));
418 else
419 writel(INTERRUPT_DISABLE_MASK_11,
420 (hba->mmio_base + REG_INTERRUPT_ENABLE));
421 break;
422 }
423}
424
425
426
427
428
429static void ufshcd_compose_upiu(struct ufshcd_lrb *lrbp)
430{
431 struct utp_transfer_req_desc *req_desc;
432 struct utp_upiu_cmd *ucd_cmd_ptr;
433 u32 data_direction;
434 u32 upiu_flags;
435
436 ucd_cmd_ptr = lrbp->ucd_cmd_ptr;
437 req_desc = lrbp->utr_descriptor_ptr;
438
439 switch (lrbp->command_type) {
440 case UTP_CMD_TYPE_SCSI:
441 if (lrbp->cmd->sc_data_direction == DMA_FROM_DEVICE) {
442 data_direction = UTP_DEVICE_TO_HOST;
443 upiu_flags = UPIU_CMD_FLAGS_READ;
444 } else if (lrbp->cmd->sc_data_direction == DMA_TO_DEVICE) {
445 data_direction = UTP_HOST_TO_DEVICE;
446 upiu_flags = UPIU_CMD_FLAGS_WRITE;
447 } else {
448 data_direction = UTP_NO_DATA_TRANSFER;
449 upiu_flags = UPIU_CMD_FLAGS_NONE;
450 }
451
452
453 req_desc->header.dword_0 =
454 cpu_to_le32(data_direction | UTP_SCSI_COMMAND);
455
456
457
458
459
460
461 req_desc->header.dword_2 =
462 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
463
464
465 ucd_cmd_ptr->header.dword_0 =
466 cpu_to_be32(UPIU_HEADER_DWORD(UPIU_TRANSACTION_COMMAND,
467 upiu_flags,
468 lrbp->lun,
469 lrbp->task_tag));
470 ucd_cmd_ptr->header.dword_1 =
471 cpu_to_be32(
472 UPIU_HEADER_DWORD(UPIU_COMMAND_SET_TYPE_SCSI,
473 0,
474 0,
475 0));
476
477
478 ucd_cmd_ptr->header.dword_2 = 0;
479
480 ucd_cmd_ptr->exp_data_transfer_len =
481 cpu_to_be32(lrbp->cmd->sdb.length);
482
483 memcpy(ucd_cmd_ptr->cdb,
484 lrbp->cmd->cmnd,
485 (min_t(unsigned short,
486 lrbp->cmd->cmd_len,
487 MAX_CDB_SIZE)));
488 break;
489 case UTP_CMD_TYPE_DEV_MANAGE:
490
491 break;
492 case UTP_CMD_TYPE_UFS:
493
494 break;
495 }
496}
497
498
499
500
501
502
503
504
505static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
506{
507 struct ufshcd_lrb *lrbp;
508 struct ufs_hba *hba;
509 unsigned long flags;
510 int tag;
511 int err = 0;
512
513 hba = shost_priv(host);
514
515 tag = cmd->request->tag;
516
517 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
518 err = SCSI_MLQUEUE_HOST_BUSY;
519 goto out;
520 }
521
522 lrbp = &hba->lrb[tag];
523
524 lrbp->cmd = cmd;
525 lrbp->sense_bufflen = SCSI_SENSE_BUFFERSIZE;
526 lrbp->sense_buffer = cmd->sense_buffer;
527 lrbp->task_tag = tag;
528 lrbp->lun = cmd->device->lun;
529
530 lrbp->command_type = UTP_CMD_TYPE_SCSI;
531
532
533 ufshcd_compose_upiu(lrbp);
534 err = ufshcd_map_sg(lrbp);
535 if (err)
536 goto out;
537
538
539 spin_lock_irqsave(hba->host->host_lock, flags);
540 ufshcd_send_command(hba, tag);
541 spin_unlock_irqrestore(hba->host->host_lock, flags);
542out:
543 return err;
544}
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559static int ufshcd_memory_alloc(struct ufs_hba *hba)
560{
561 size_t utmrdl_size, utrdl_size, ucdl_size;
562
563
564 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
565 hba->ucdl_base_addr = dma_alloc_coherent(hba->dev,
566 ucdl_size,
567 &hba->ucdl_dma_addr,
568 GFP_KERNEL);
569
570
571
572
573
574
575
576 if (!hba->ucdl_base_addr ||
577 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
578 dev_err(hba->dev,
579 "Command Descriptor Memory allocation failed\n");
580 goto out;
581 }
582
583
584
585
586
587 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
588 hba->utrdl_base_addr = dma_alloc_coherent(hba->dev,
589 utrdl_size,
590 &hba->utrdl_dma_addr,
591 GFP_KERNEL);
592 if (!hba->utrdl_base_addr ||
593 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
594 dev_err(hba->dev,
595 "Transfer Descriptor Memory allocation failed\n");
596 goto out;
597 }
598
599
600
601
602
603 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
604 hba->utmrdl_base_addr = dma_alloc_coherent(hba->dev,
605 utmrdl_size,
606 &hba->utmrdl_dma_addr,
607 GFP_KERNEL);
608 if (!hba->utmrdl_base_addr ||
609 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
610 dev_err(hba->dev,
611 "Task Management Descriptor Memory allocation failed\n");
612 goto out;
613 }
614
615
616 hba->lrb = kcalloc(hba->nutrs, sizeof(struct ufshcd_lrb), GFP_KERNEL);
617 if (!hba->lrb) {
618 dev_err(hba->dev, "LRB Memory allocation failed\n");
619 goto out;
620 }
621 return 0;
622out:
623 ufshcd_free_hba_memory(hba);
624 return -ENOMEM;
625}
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640static void ufshcd_host_memory_configure(struct ufs_hba *hba)
641{
642 struct utp_transfer_cmd_desc *cmd_descp;
643 struct utp_transfer_req_desc *utrdlp;
644 dma_addr_t cmd_desc_dma_addr;
645 dma_addr_t cmd_desc_element_addr;
646 u16 response_offset;
647 u16 prdt_offset;
648 int cmd_desc_size;
649 int i;
650
651 utrdlp = hba->utrdl_base_addr;
652 cmd_descp = hba->ucdl_base_addr;
653
654 response_offset =
655 offsetof(struct utp_transfer_cmd_desc, response_upiu);
656 prdt_offset =
657 offsetof(struct utp_transfer_cmd_desc, prd_table);
658
659 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
660 cmd_desc_dma_addr = hba->ucdl_dma_addr;
661
662 for (i = 0; i < hba->nutrs; i++) {
663
664 cmd_desc_element_addr =
665 (cmd_desc_dma_addr + (cmd_desc_size * i));
666 utrdlp[i].command_desc_base_addr_lo =
667 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
668 utrdlp[i].command_desc_base_addr_hi =
669 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
670
671
672 utrdlp[i].response_upiu_offset =
673 cpu_to_le16((response_offset >> 2));
674 utrdlp[i].prd_table_offset =
675 cpu_to_le16((prdt_offset >> 2));
676 utrdlp[i].response_upiu_length =
677 cpu_to_le16(ALIGNED_UPIU_SIZE);
678
679 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
680 hba->lrb[i].ucd_cmd_ptr =
681 (struct utp_upiu_cmd *)(cmd_descp + i);
682 hba->lrb[i].ucd_rsp_ptr =
683 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
684 hba->lrb[i].ucd_prdt_ptr =
685 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
686 }
687}
688
689
690
691
692
693
694
695
696
697
698
699
700static int ufshcd_dme_link_startup(struct ufs_hba *hba)
701{
702 struct uic_command *uic_cmd;
703 unsigned long flags;
704
705
706 if (((readl(hba->mmio_base + REG_CONTROLLER_STATUS)) &
707 UIC_COMMAND_READY) == 0x0) {
708 dev_err(hba->dev,
709 "Controller not ready"
710 " to accept UIC commands\n");
711 return -EIO;
712 }
713
714 spin_lock_irqsave(hba->host->host_lock, flags);
715
716
717 uic_cmd = &hba->active_uic_cmd;
718 uic_cmd->command = UIC_CMD_DME_LINK_STARTUP;
719 uic_cmd->argument1 = 0;
720 uic_cmd->argument2 = 0;
721 uic_cmd->argument3 = 0;
722
723
724 hba->int_enable_mask |= UIC_COMMAND_COMPL;
725 ufshcd_int_config(hba, UFSHCD_INT_ENABLE);
726
727
728 ufshcd_send_uic_command(hba, uic_cmd);
729 spin_unlock_irqrestore(hba->host->host_lock, flags);
730 return 0;
731}
732
733
734
735
736
737
738
739
740
741
742
743
744
745static int ufshcd_make_hba_operational(struct ufs_hba *hba)
746{
747 int err = 0;
748 u32 reg;
749
750
751 reg = readl((hba->mmio_base + REG_CONTROLLER_STATUS));
752 if (!ufshcd_is_device_present(reg)) {
753 dev_err(hba->dev, "cc: Device not present\n");
754 err = -ENXIO;
755 goto out;
756 }
757
758
759
760
761
762 if (!(ufshcd_get_lists_status(reg))) {
763 ufshcd_enable_run_stop_reg(hba);
764 } else {
765 dev_err(hba->dev,
766 "Host controller not ready to process requests");
767 err = -EIO;
768 goto out;
769 }
770
771
772 hba->int_enable_mask |= (UTP_TRANSFER_REQ_COMPL |
773 UIC_ERROR |
774 UTP_TASK_REQ_COMPL |
775 DEVICE_FATAL_ERROR |
776 CONTROLLER_FATAL_ERROR |
777 SYSTEM_BUS_FATAL_ERROR);
778 ufshcd_int_config(hba, UFSHCD_INT_ENABLE);
779
780
781 ufshcd_config_int_aggr(hba, INT_AGGR_CONFIG);
782
783 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
784 scsi_unblock_requests(hba->host);
785
786 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
787 scsi_scan_host(hba->host);
788out:
789 return err;
790}
791
792
793
794
795
796
797
798
799
800
801
802static int ufshcd_hba_enable(struct ufs_hba *hba)
803{
804 int retry;
805
806
807
808
809
810
811
812 if (!ufshcd_is_hba_active(hba)) {
813
814
815 ufshcd_hba_stop(hba);
816
817
818
819
820
821
822 msleep(5);
823 }
824
825
826 ufshcd_hba_start(hba);
827
828
829
830
831
832
833
834
835
836
837
838 msleep(1);
839
840
841 retry = 10;
842 while (ufshcd_is_hba_active(hba)) {
843 if (retry) {
844 retry--;
845 } else {
846 dev_err(hba->dev,
847 "Controller enable failed\n");
848 return -EIO;
849 }
850 msleep(5);
851 }
852 return 0;
853}
854
855
856
857
858
859
860
861
862
863
864
865
866
867static int ufshcd_initialize_hba(struct ufs_hba *hba)
868{
869 if (ufshcd_hba_enable(hba))
870 return -EIO;
871
872
873 writel(lower_32_bits(hba->utrdl_dma_addr),
874 (hba->mmio_base + REG_UTP_TRANSFER_REQ_LIST_BASE_L));
875 writel(upper_32_bits(hba->utrdl_dma_addr),
876 (hba->mmio_base + REG_UTP_TRANSFER_REQ_LIST_BASE_H));
877 writel(lower_32_bits(hba->utmrdl_dma_addr),
878 (hba->mmio_base + REG_UTP_TASK_REQ_LIST_BASE_L));
879 writel(upper_32_bits(hba->utmrdl_dma_addr),
880 (hba->mmio_base + REG_UTP_TASK_REQ_LIST_BASE_H));
881
882
883 return ufshcd_dme_link_startup(hba);
884}
885
886
887
888
889
890
891
892static int ufshcd_do_reset(struct ufs_hba *hba)
893{
894 struct ufshcd_lrb *lrbp;
895 unsigned long flags;
896 int tag;
897
898
899 scsi_block_requests(hba->host);
900
901 spin_lock_irqsave(hba->host->host_lock, flags);
902 hba->ufshcd_state = UFSHCD_STATE_RESET;
903
904
905 ufshcd_hba_stop(hba);
906 spin_unlock_irqrestore(hba->host->host_lock, flags);
907
908
909 for (tag = 0; tag < hba->nutrs; tag++) {
910 if (test_bit(tag, &hba->outstanding_reqs)) {
911 lrbp = &hba->lrb[tag];
912 scsi_dma_unmap(lrbp->cmd);
913 lrbp->cmd->result = DID_RESET << 16;
914 lrbp->cmd->scsi_done(lrbp->cmd);
915 lrbp->cmd = NULL;
916 }
917 }
918
919
920 hba->outstanding_reqs = 0;
921 hba->outstanding_tasks = 0;
922
923
924 if (ufshcd_initialize_hba(hba)) {
925 dev_err(hba->dev,
926 "Reset: Controller initialization failed\n");
927 return FAILED;
928 }
929 return SUCCESS;
930}
931
932
933
934
935
936
937
938static int ufshcd_slave_alloc(struct scsi_device *sdev)
939{
940 struct ufs_hba *hba;
941
942 hba = shost_priv(sdev->host);
943 sdev->tagged_supported = 1;
944
945
946 sdev->use_10_for_ms = 1;
947 scsi_set_tag_type(sdev, MSG_SIMPLE_TAG);
948
949
950
951
952
953
954
955
956 scsi_activate_tcq(sdev, hba->nutrs);
957 return 0;
958}
959
960
961
962
963
964static void ufshcd_slave_destroy(struct scsi_device *sdev)
965{
966 struct ufs_hba *hba;
967
968 hba = shost_priv(sdev->host);
969 scsi_deactivate_tcq(sdev, hba->nutrs);
970}
971
972
973
974
975
976
977
978
979static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index)
980{
981 struct utp_task_req_desc *task_req_descp;
982 struct utp_upiu_task_rsp *task_rsp_upiup;
983 unsigned long flags;
984 int ocs_value;
985 int task_result;
986
987 spin_lock_irqsave(hba->host->host_lock, flags);
988
989
990 __clear_bit(index, &hba->outstanding_tasks);
991
992 task_req_descp = hba->utmrdl_base_addr;
993 ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
994
995 if (ocs_value == OCS_SUCCESS) {
996 task_rsp_upiup = (struct utp_upiu_task_rsp *)
997 task_req_descp[index].task_rsp_upiu;
998 task_result = be32_to_cpu(task_rsp_upiup->header.dword_1);
999 task_result = ((task_result & MASK_TASK_RESPONSE) >> 8);
1000
1001 if (task_result != UPIU_TASK_MANAGEMENT_FUNC_COMPL &&
1002 task_result != UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED)
1003 task_result = FAILED;
1004 else
1005 task_result = SUCCESS;
1006 } else {
1007 task_result = FAILED;
1008 dev_err(hba->dev,
1009 "trc: Invalid ocs = %x\n", ocs_value);
1010 }
1011 spin_unlock_irqrestore(hba->host->host_lock, flags);
1012 return task_result;
1013}
1014
1015
1016
1017
1018
1019
1020static void ufshcd_adjust_lun_qdepth(struct scsi_cmnd *cmd)
1021{
1022 struct ufs_hba *hba;
1023 int i;
1024 int lun_qdepth = 0;
1025
1026 hba = shost_priv(cmd->device->host);
1027
1028
1029
1030
1031
1032 for (i = 0; i < hba->nutrs; i++) {
1033 if (test_bit(i, &hba->outstanding_reqs)) {
1034
1035
1036
1037
1038
1039 if (cmd->device->lun == hba->lrb[i].lun)
1040 lun_qdepth++;
1041 }
1042 }
1043
1044
1045
1046
1047
1048 scsi_adjust_queue_depth(cmd->device, MSG_SIMPLE_TAG, lun_qdepth - 1);
1049}
1050
1051
1052
1053
1054
1055
1056
1057
1058static inline int
1059ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
1060{
1061 int result = 0;
1062
1063 switch (scsi_status) {
1064 case SAM_STAT_GOOD:
1065 result |= DID_OK << 16 |
1066 COMMAND_COMPLETE << 8 |
1067 SAM_STAT_GOOD;
1068 break;
1069 case SAM_STAT_CHECK_CONDITION:
1070 result |= DID_OK << 16 |
1071 COMMAND_COMPLETE << 8 |
1072 SAM_STAT_CHECK_CONDITION;
1073 ufshcd_copy_sense_data(lrbp);
1074 break;
1075 case SAM_STAT_BUSY:
1076 result |= SAM_STAT_BUSY;
1077 break;
1078 case SAM_STAT_TASK_SET_FULL:
1079
1080
1081
1082
1083
1084
1085 ufshcd_adjust_lun_qdepth(lrbp->cmd);
1086 result |= SAM_STAT_TASK_SET_FULL;
1087 break;
1088 case SAM_STAT_TASK_ABORTED:
1089 result |= SAM_STAT_TASK_ABORTED;
1090 break;
1091 default:
1092 result |= DID_ERROR << 16;
1093 break;
1094 }
1095
1096 return result;
1097}
1098
1099
1100
1101
1102
1103
1104
1105
1106static inline int
1107ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1108{
1109 int result = 0;
1110 int scsi_status;
1111 int ocs;
1112
1113
1114 ocs = ufshcd_get_tr_ocs(lrbp);
1115
1116 switch (ocs) {
1117 case OCS_SUCCESS:
1118
1119
1120 result = ufshcd_is_valid_req_rsp(lrbp->ucd_rsp_ptr);
1121 if (result) {
1122 dev_err(hba->dev,
1123 "Invalid response = %x\n", result);
1124 break;
1125 }
1126
1127
1128
1129
1130
1131 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
1132
1133
1134
1135
1136
1137 scsi_status = result & MASK_SCSI_STATUS;
1138 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
1139 break;
1140 case OCS_ABORTED:
1141 result |= DID_ABORT << 16;
1142 break;
1143 case OCS_INVALID_CMD_TABLE_ATTR:
1144 case OCS_INVALID_PRDT_ATTR:
1145 case OCS_MISMATCH_DATA_BUF_SIZE:
1146 case OCS_MISMATCH_RESP_UPIU_SIZE:
1147 case OCS_PEER_COMM_FAILURE:
1148 case OCS_FATAL_ERROR:
1149 default:
1150 result |= DID_ERROR << 16;
1151 dev_err(hba->dev,
1152 "OCS error from controller = %x\n", ocs);
1153 break;
1154 }
1155
1156 return result;
1157}
1158
1159
1160
1161
1162
1163static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
1164{
1165 struct ufshcd_lrb *lrb;
1166 unsigned long completed_reqs;
1167 u32 tr_doorbell;
1168 int result;
1169 int index;
1170
1171 lrb = hba->lrb;
1172 tr_doorbell =
1173 readl(hba->mmio_base + REG_UTP_TRANSFER_REQ_DOOR_BELL);
1174 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
1175
1176 for (index = 0; index < hba->nutrs; index++) {
1177 if (test_bit(index, &completed_reqs)) {
1178
1179 result = ufshcd_transfer_rsp_status(hba, &lrb[index]);
1180
1181 if (lrb[index].cmd) {
1182 scsi_dma_unmap(lrb[index].cmd);
1183 lrb[index].cmd->result = result;
1184 lrb[index].cmd->scsi_done(lrb[index].cmd);
1185
1186
1187 lrb[index].cmd = NULL;
1188 }
1189 }
1190 }
1191
1192
1193 hba->outstanding_reqs ^= completed_reqs;
1194
1195
1196 ufshcd_config_int_aggr(hba, INT_AGGR_RESET);
1197}
1198
1199
1200
1201
1202
1203
1204
1205static void ufshcd_uic_cc_handler (struct work_struct *work)
1206{
1207 struct ufs_hba *hba;
1208
1209 hba = container_of(work, struct ufs_hba, uic_workq);
1210
1211 if ((hba->active_uic_cmd.command == UIC_CMD_DME_LINK_STARTUP) &&
1212 !(ufshcd_get_uic_cmd_result(hba))) {
1213
1214 if (ufshcd_make_hba_operational(hba))
1215 dev_err(hba->dev,
1216 "cc: hba not operational state\n");
1217 return;
1218 }
1219}
1220
1221
1222
1223
1224
1225static void ufshcd_fatal_err_handler(struct work_struct *work)
1226{
1227 struct ufs_hba *hba;
1228 hba = container_of(work, struct ufs_hba, feh_workq);
1229
1230
1231 if (hba->ufshcd_state != UFSHCD_STATE_RESET)
1232 ufshcd_do_reset(hba);
1233}
1234
1235
1236
1237
1238
1239static void ufshcd_err_handler(struct ufs_hba *hba)
1240{
1241 u32 reg;
1242
1243 if (hba->errors & INT_FATAL_ERRORS)
1244 goto fatal_eh;
1245
1246 if (hba->errors & UIC_ERROR) {
1247
1248 reg = readl(hba->mmio_base +
1249 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
1250 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
1251 goto fatal_eh;
1252 }
1253 return;
1254fatal_eh:
1255 hba->ufshcd_state = UFSHCD_STATE_ERROR;
1256 schedule_work(&hba->feh_workq);
1257}
1258
1259
1260
1261
1262
1263static void ufshcd_tmc_handler(struct ufs_hba *hba)
1264{
1265 u32 tm_doorbell;
1266
1267 tm_doorbell = readl(hba->mmio_base + REG_UTP_TASK_REQ_DOOR_BELL);
1268 hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
1269 wake_up_interruptible(&hba->ufshcd_tm_wait_queue);
1270}
1271
1272
1273
1274
1275
1276
1277static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
1278{
1279 hba->errors = UFSHCD_ERROR_MASK & intr_status;
1280 if (hba->errors)
1281 ufshcd_err_handler(hba);
1282
1283 if (intr_status & UIC_COMMAND_COMPL)
1284 schedule_work(&hba->uic_workq);
1285
1286 if (intr_status & UTP_TASK_REQ_COMPL)
1287 ufshcd_tmc_handler(hba);
1288
1289 if (intr_status & UTP_TRANSFER_REQ_COMPL)
1290 ufshcd_transfer_req_compl(hba);
1291}
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301static irqreturn_t ufshcd_intr(int irq, void *__hba)
1302{
1303 u32 intr_status;
1304 irqreturn_t retval = IRQ_NONE;
1305 struct ufs_hba *hba = __hba;
1306
1307 spin_lock(hba->host->host_lock);
1308 intr_status = readl(hba->mmio_base + REG_INTERRUPT_STATUS);
1309
1310 if (intr_status) {
1311 ufshcd_sl_intr(hba, intr_status);
1312
1313
1314 if (hba->ufs_version == UFSHCI_VERSION_10)
1315 writel(intr_status,
1316 (hba->mmio_base + REG_INTERRUPT_STATUS));
1317 retval = IRQ_HANDLED;
1318 }
1319 spin_unlock(hba->host->host_lock);
1320 return retval;
1321}
1322
1323
1324
1325
1326
1327
1328
1329
1330static int
1331ufshcd_issue_tm_cmd(struct ufs_hba *hba,
1332 struct ufshcd_lrb *lrbp,
1333 u8 tm_function)
1334{
1335 struct utp_task_req_desc *task_req_descp;
1336 struct utp_upiu_task_req *task_req_upiup;
1337 struct Scsi_Host *host;
1338 unsigned long flags;
1339 int free_slot = 0;
1340 int err;
1341
1342 host = hba->host;
1343
1344 spin_lock_irqsave(host->host_lock, flags);
1345
1346
1347 free_slot = ufshcd_get_tm_free_slot(hba);
1348 if (free_slot >= hba->nutmrs) {
1349 spin_unlock_irqrestore(host->host_lock, flags);
1350 dev_err(hba->dev, "Task management queue full\n");
1351 err = FAILED;
1352 goto out;
1353 }
1354
1355 task_req_descp = hba->utmrdl_base_addr;
1356 task_req_descp += free_slot;
1357
1358
1359 task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
1360 task_req_descp->header.dword_2 =
1361 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
1362
1363
1364 task_req_upiup =
1365 (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
1366 task_req_upiup->header.dword_0 =
1367 cpu_to_be32(UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
1368 lrbp->lun, lrbp->task_tag));
1369 task_req_upiup->header.dword_1 =
1370 cpu_to_be32(UPIU_HEADER_DWORD(0, tm_function, 0, 0));
1371
1372 task_req_upiup->input_param1 = lrbp->lun;
1373 task_req_upiup->input_param1 =
1374 cpu_to_be32(task_req_upiup->input_param1);
1375 task_req_upiup->input_param2 = lrbp->task_tag;
1376 task_req_upiup->input_param2 =
1377 cpu_to_be32(task_req_upiup->input_param2);
1378
1379
1380 __set_bit(free_slot, &hba->outstanding_tasks);
1381 writel((1 << free_slot),
1382 (hba->mmio_base + REG_UTP_TASK_REQ_DOOR_BELL));
1383
1384 spin_unlock_irqrestore(host->host_lock, flags);
1385
1386
1387 err =
1388 wait_event_interruptible_timeout(hba->ufshcd_tm_wait_queue,
1389 (test_bit(free_slot,
1390 &hba->tm_condition) != 0),
1391 60 * HZ);
1392 if (!err) {
1393 dev_err(hba->dev,
1394 "Task management command timed-out\n");
1395 err = FAILED;
1396 goto out;
1397 }
1398 clear_bit(free_slot, &hba->tm_condition);
1399 err = ufshcd_task_req_compl(hba, free_slot);
1400out:
1401 return err;
1402}
1403
1404
1405
1406
1407
1408
1409
1410static int ufshcd_device_reset(struct scsi_cmnd *cmd)
1411{
1412 struct Scsi_Host *host;
1413 struct ufs_hba *hba;
1414 unsigned int tag;
1415 u32 pos;
1416 int err;
1417
1418 host = cmd->device->host;
1419 hba = shost_priv(host);
1420 tag = cmd->request->tag;
1421
1422 err = ufshcd_issue_tm_cmd(hba, &hba->lrb[tag], UFS_LOGICAL_RESET);
1423 if (err == FAILED)
1424 goto out;
1425
1426 for (pos = 0; pos < hba->nutrs; pos++) {
1427 if (test_bit(pos, &hba->outstanding_reqs) &&
1428 (hba->lrb[tag].lun == hba->lrb[pos].lun)) {
1429
1430
1431 ufshcd_utrl_clear(hba, pos);
1432
1433 clear_bit(pos, &hba->outstanding_reqs);
1434
1435 if (hba->lrb[pos].cmd) {
1436 scsi_dma_unmap(hba->lrb[pos].cmd);
1437 hba->lrb[pos].cmd->result =
1438 DID_ABORT << 16;
1439 hba->lrb[pos].cmd->scsi_done(cmd);
1440 hba->lrb[pos].cmd = NULL;
1441 }
1442 }
1443 }
1444out:
1445 return err;
1446}
1447
1448
1449
1450
1451
1452
1453
1454static int ufshcd_host_reset(struct scsi_cmnd *cmd)
1455{
1456 struct ufs_hba *hba;
1457
1458 hba = shost_priv(cmd->device->host);
1459
1460 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
1461 return SUCCESS;
1462
1463 return ufshcd_do_reset(hba);
1464}
1465
1466
1467
1468
1469
1470
1471
1472static int ufshcd_abort(struct scsi_cmnd *cmd)
1473{
1474 struct Scsi_Host *host;
1475 struct ufs_hba *hba;
1476 unsigned long flags;
1477 unsigned int tag;
1478 int err;
1479
1480 host = cmd->device->host;
1481 hba = shost_priv(host);
1482 tag = cmd->request->tag;
1483
1484 spin_lock_irqsave(host->host_lock, flags);
1485
1486
1487 if (!(test_bit(tag, &hba->outstanding_reqs))) {
1488 err = FAILED;
1489 spin_unlock_irqrestore(host->host_lock, flags);
1490 goto out;
1491 }
1492 spin_unlock_irqrestore(host->host_lock, flags);
1493
1494 err = ufshcd_issue_tm_cmd(hba, &hba->lrb[tag], UFS_ABORT_TASK);
1495 if (err == FAILED)
1496 goto out;
1497
1498 scsi_dma_unmap(cmd);
1499
1500 spin_lock_irqsave(host->host_lock, flags);
1501
1502
1503 ufshcd_utrl_clear(hba, tag);
1504
1505 __clear_bit(tag, &hba->outstanding_reqs);
1506 hba->lrb[tag].cmd = NULL;
1507 spin_unlock_irqrestore(host->host_lock, flags);
1508out:
1509 return err;
1510}
1511
1512static struct scsi_host_template ufshcd_driver_template = {
1513 .module = THIS_MODULE,
1514 .name = UFSHCD,
1515 .proc_name = UFSHCD,
1516 .queuecommand = ufshcd_queuecommand,
1517 .slave_alloc = ufshcd_slave_alloc,
1518 .slave_destroy = ufshcd_slave_destroy,
1519 .eh_abort_handler = ufshcd_abort,
1520 .eh_device_reset_handler = ufshcd_device_reset,
1521 .eh_host_reset_handler = ufshcd_host_reset,
1522 .this_id = -1,
1523 .sg_tablesize = SG_ALL,
1524 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
1525 .can_queue = UFSHCD_CAN_QUEUE,
1526};
1527
1528
1529
1530
1531
1532
1533
1534
1535int ufshcd_suspend(struct ufs_hba *hba, pm_message_t state)
1536{
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546 return -ENOSYS;
1547}
1548EXPORT_SYMBOL_GPL(ufshcd_suspend);
1549
1550
1551
1552
1553
1554
1555
1556int ufshcd_resume(struct ufs_hba *hba)
1557{
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567 return -ENOSYS;
1568}
1569EXPORT_SYMBOL_GPL(ufshcd_resume);
1570
1571
1572
1573
1574
1575
1576static void ufshcd_hba_free(struct ufs_hba *hba)
1577{
1578 iounmap(hba->mmio_base);
1579 ufshcd_free_hba_memory(hba);
1580}
1581
1582
1583
1584
1585
1586
1587void ufshcd_remove(struct ufs_hba *hba)
1588{
1589
1590 ufshcd_int_config(hba, UFSHCD_INT_DISABLE);
1591
1592 ufshcd_hba_stop(hba);
1593 ufshcd_hba_free(hba);
1594
1595 scsi_remove_host(hba->host);
1596 scsi_host_put(hba->host);
1597}
1598EXPORT_SYMBOL_GPL(ufshcd_remove);
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608int ufshcd_init(struct device *dev, struct ufs_hba **hba_handle,
1609 void __iomem *mmio_base, unsigned int irq)
1610{
1611 struct Scsi_Host *host;
1612 struct ufs_hba *hba;
1613 int err;
1614
1615 if (!dev) {
1616 dev_err(dev,
1617 "Invalid memory reference for dev is NULL\n");
1618 err = -ENODEV;
1619 goto out_error;
1620 }
1621
1622 if (!mmio_base) {
1623 dev_err(dev,
1624 "Invalid memory reference for mmio_base is NULL\n");
1625 err = -ENODEV;
1626 goto out_error;
1627 }
1628
1629 host = scsi_host_alloc(&ufshcd_driver_template,
1630 sizeof(struct ufs_hba));
1631 if (!host) {
1632 dev_err(dev, "scsi_host_alloc failed\n");
1633 err = -ENOMEM;
1634 goto out_error;
1635 }
1636 hba = shost_priv(host);
1637 hba->host = host;
1638 hba->dev = dev;
1639 hba->mmio_base = mmio_base;
1640 hba->irq = irq;
1641
1642
1643 ufshcd_hba_capabilities(hba);
1644
1645
1646 hba->ufs_version = ufshcd_get_ufs_version(hba);
1647
1648
1649 err = ufshcd_memory_alloc(hba);
1650 if (err) {
1651 dev_err(hba->dev, "Memory allocation failed\n");
1652 goto out_disable;
1653 }
1654
1655
1656 ufshcd_host_memory_configure(hba);
1657
1658 host->can_queue = hba->nutrs;
1659 host->cmd_per_lun = hba->nutrs;
1660 host->max_id = UFSHCD_MAX_ID;
1661 host->max_lun = UFSHCD_MAX_LUNS;
1662 host->max_channel = UFSHCD_MAX_CHANNEL;
1663 host->unique_id = host->host_no;
1664 host->max_cmd_len = MAX_CDB_SIZE;
1665
1666
1667 init_waitqueue_head(&hba->ufshcd_tm_wait_queue);
1668
1669
1670 INIT_WORK(&hba->uic_workq, ufshcd_uic_cc_handler);
1671 INIT_WORK(&hba->feh_workq, ufshcd_fatal_err_handler);
1672
1673
1674 err = request_irq(irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
1675 if (err) {
1676 dev_err(hba->dev, "request irq failed\n");
1677 goto out_lrb_free;
1678 }
1679
1680
1681 err = scsi_init_shared_tag_map(host, host->can_queue);
1682 if (err) {
1683 dev_err(hba->dev, "init shared queue failed\n");
1684 goto out_free_irq;
1685 }
1686
1687 err = scsi_add_host(host, hba->dev);
1688 if (err) {
1689 dev_err(hba->dev, "scsi_add_host failed\n");
1690 goto out_free_irq;
1691 }
1692
1693
1694 err = ufshcd_initialize_hba(hba);
1695 if (err) {
1696 dev_err(hba->dev, "Initialization failed\n");
1697 goto out_remove_scsi_host;
1698 }
1699 *hba_handle = hba;
1700
1701 return 0;
1702
1703out_remove_scsi_host:
1704 scsi_remove_host(hba->host);
1705out_free_irq:
1706 free_irq(irq, hba);
1707out_lrb_free:
1708 ufshcd_free_hba_memory(hba);
1709out_disable:
1710 scsi_host_put(host);
1711out_error:
1712 return err;
1713}
1714EXPORT_SYMBOL_GPL(ufshcd_init);
1715
1716MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
1717MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
1718MODULE_DESCRIPTION("Generic UFS host controller driver Core");
1719MODULE_LICENSE("GPL");
1720MODULE_VERSION(UFSHCD_DRIVER_VERSION);
1721