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25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/device.h>
28#include <linux/ioport.h>
29#include <linux/errno.h>
30#include <linux/interrupt.h>
31#include <linux/spi/spi.h>
32#include <linux/delay.h>
33#include <linux/clk.h>
34#include <linux/err.h>
35#include <linux/amba/bus.h>
36#include <linux/amba/pl022.h>
37#include <linux/io.h>
38#include <linux/slab.h>
39#include <linux/dmaengine.h>
40#include <linux/dma-mapping.h>
41#include <linux/scatterlist.h>
42#include <linux/pm_runtime.h>
43#include <linux/gpio.h>
44#include <linux/of_gpio.h>
45#include <linux/pinctrl/consumer.h>
46
47
48
49
50
51
52#define SSP_WRITE_BITS(reg, val, mask, sb) \
53 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
54
55
56
57
58
59
60#define GEN_MASK_BITS(val, mask, sb) \
61 (((val)<<(sb)) & (mask))
62
63#define DRIVE_TX 0
64#define DO_NOT_DRIVE_TX 1
65
66#define DO_NOT_QUEUE_DMA 0
67#define QUEUE_DMA 1
68
69#define RX_TRANSFER 1
70#define TX_TRANSFER 2
71
72
73
74
75#define SSP_CR0(r) (r + 0x000)
76#define SSP_CR1(r) (r + 0x004)
77#define SSP_DR(r) (r + 0x008)
78#define SSP_SR(r) (r + 0x00C)
79#define SSP_CPSR(r) (r + 0x010)
80#define SSP_IMSC(r) (r + 0x014)
81#define SSP_RIS(r) (r + 0x018)
82#define SSP_MIS(r) (r + 0x01C)
83#define SSP_ICR(r) (r + 0x020)
84#define SSP_DMACR(r) (r + 0x024)
85#define SSP_ITCR(r) (r + 0x080)
86#define SSP_ITIP(r) (r + 0x084)
87#define SSP_ITOP(r) (r + 0x088)
88#define SSP_TDR(r) (r + 0x08C)
89
90#define SSP_PID0(r) (r + 0xFE0)
91#define SSP_PID1(r) (r + 0xFE4)
92#define SSP_PID2(r) (r + 0xFE8)
93#define SSP_PID3(r) (r + 0xFEC)
94
95#define SSP_CID0(r) (r + 0xFF0)
96#define SSP_CID1(r) (r + 0xFF4)
97#define SSP_CID2(r) (r + 0xFF8)
98#define SSP_CID3(r) (r + 0xFFC)
99
100
101
102
103#define SSP_CR0_MASK_DSS (0x0FUL << 0)
104#define SSP_CR0_MASK_FRF (0x3UL << 4)
105#define SSP_CR0_MASK_SPO (0x1UL << 6)
106#define SSP_CR0_MASK_SPH (0x1UL << 7)
107#define SSP_CR0_MASK_SCR (0xFFUL << 8)
108
109
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111
112
113#define SSP_CR0_MASK_DSS_ST (0x1FUL << 0)
114#define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5)
115#define SSP_CR0_MASK_CSS_ST (0x1FUL << 16)
116#define SSP_CR0_MASK_FRF_ST (0x3UL << 21)
117
118
119
120
121#define SSP_CR1_MASK_LBM (0x1UL << 0)
122#define SSP_CR1_MASK_SSE (0x1UL << 1)
123#define SSP_CR1_MASK_MS (0x1UL << 2)
124#define SSP_CR1_MASK_SOD (0x1UL << 3)
125
126
127
128
129
130#define SSP_CR1_MASK_RENDN_ST (0x1UL << 4)
131#define SSP_CR1_MASK_TENDN_ST (0x1UL << 5)
132#define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6)
133#define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)
134#define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)
135
136#define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
137
138
139
140
141#define SSP_SR_MASK_TFE (0x1UL << 0)
142#define SSP_SR_MASK_TNF (0x1UL << 1)
143#define SSP_SR_MASK_RNE (0x1UL << 2)
144#define SSP_SR_MASK_RFF (0x1UL << 3)
145#define SSP_SR_MASK_BSY (0x1UL << 4)
146
147
148
149
150#define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0)
151
152
153
154
155#define SSP_IMSC_MASK_RORIM (0x1UL << 0)
156#define SSP_IMSC_MASK_RTIM (0x1UL << 1)
157#define SSP_IMSC_MASK_RXIM (0x1UL << 2)
158#define SSP_IMSC_MASK_TXIM (0x1UL << 3)
159
160
161
162
163
164#define SSP_RIS_MASK_RORRIS (0x1UL << 0)
165
166#define SSP_RIS_MASK_RTRIS (0x1UL << 1)
167
168#define SSP_RIS_MASK_RXRIS (0x1UL << 2)
169
170#define SSP_RIS_MASK_TXRIS (0x1UL << 3)
171
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174
175
176#define SSP_MIS_MASK_RORMIS (0x1UL << 0)
177
178#define SSP_MIS_MASK_RTMIS (0x1UL << 1)
179
180#define SSP_MIS_MASK_RXMIS (0x1UL << 2)
181
182#define SSP_MIS_MASK_TXMIS (0x1UL << 3)
183
184
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186
187
188#define SSP_ICR_MASK_RORIC (0x1UL << 0)
189
190#define SSP_ICR_MASK_RTIC (0x1UL << 1)
191
192
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194
195
196#define SSP_DMACR_MASK_RXDMAE (0x1UL << 0)
197
198#define SSP_DMACR_MASK_TXDMAE (0x1UL << 1)
199
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201
202
203#define SSP_ITCR_MASK_ITEN (0x1UL << 0)
204#define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1)
205
206
207
208
209#define ITIP_MASK_SSPRXD (0x1UL << 0)
210#define ITIP_MASK_SSPFSSIN (0x1UL << 1)
211#define ITIP_MASK_SSPCLKIN (0x1UL << 2)
212#define ITIP_MASK_RXDMAC (0x1UL << 3)
213#define ITIP_MASK_TXDMAC (0x1UL << 4)
214#define ITIP_MASK_SSPTXDIN (0x1UL << 5)
215
216
217
218
219#define ITOP_MASK_SSPTXD (0x1UL << 0)
220#define ITOP_MASK_SSPFSSOUT (0x1UL << 1)
221#define ITOP_MASK_SSPCLKOUT (0x1UL << 2)
222#define ITOP_MASK_SSPOEn (0x1UL << 3)
223#define ITOP_MASK_SSPCTLOEn (0x1UL << 4)
224#define ITOP_MASK_RORINTR (0x1UL << 5)
225#define ITOP_MASK_RTINTR (0x1UL << 6)
226#define ITOP_MASK_RXINTR (0x1UL << 7)
227#define ITOP_MASK_TXINTR (0x1UL << 8)
228#define ITOP_MASK_INTR (0x1UL << 9)
229#define ITOP_MASK_RXDMABREQ (0x1UL << 10)
230#define ITOP_MASK_RXDMASREQ (0x1UL << 11)
231#define ITOP_MASK_TXDMABREQ (0x1UL << 12)
232#define ITOP_MASK_TXDMASREQ (0x1UL << 13)
233
234
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236
237#define TDR_MASK_TESTDATA (0xFFFFFFFF)
238
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243
244
245#define STATE_START ((void *) 0)
246#define STATE_RUNNING ((void *) 1)
247#define STATE_DONE ((void *) 2)
248#define STATE_ERROR ((void *) -1)
249
250
251
252
253#define SSP_DISABLED (0)
254#define SSP_ENABLED (1)
255
256
257
258
259#define SSP_DMA_DISABLED (0)
260#define SSP_DMA_ENABLED (1)
261
262
263
264
265#define SSP_DEFAULT_CLKRATE 0x2
266#define SSP_DEFAULT_PRESCALE 0x40
267
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270
271#define CPSDVR_MIN 0x02
272#define CPSDVR_MAX 0xFE
273#define SCR_MIN 0x00
274#define SCR_MAX 0xFF
275
276
277
278
279#define DEFAULT_SSP_REG_IMSC 0x0UL
280#define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC
281#define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC)
282
283#define CLEAR_ALL_INTERRUPTS 0x3
284
285#define SPI_POLLING_TIMEOUT 1000
286
287
288
289
290enum ssp_reading {
291 READING_NULL,
292 READING_U8,
293 READING_U16,
294 READING_U32
295};
296
297
298
299
300enum ssp_writing {
301 WRITING_NULL,
302 WRITING_U8,
303 WRITING_U16,
304 WRITING_U32
305};
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316
317struct vendor_data {
318 int fifodepth;
319 int max_bpw;
320 bool unidir;
321 bool extended_cr;
322 bool pl023;
323 bool loopback;
324};
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365struct pl022 {
366 struct amba_device *adev;
367 struct vendor_data *vendor;
368 resource_size_t phybase;
369 void __iomem *virtbase;
370 struct clk *clk;
371
372 struct pinctrl *pinctrl;
373 struct pinctrl_state *pins_default;
374 struct pinctrl_state *pins_idle;
375 struct pinctrl_state *pins_sleep;
376 struct spi_master *master;
377 struct pl022_ssp_controller *master_info;
378
379 struct tasklet_struct pump_transfers;
380 struct spi_message *cur_msg;
381 struct spi_transfer *cur_transfer;
382 struct chip_data *cur_chip;
383 bool next_msg_cs_active;
384 void *tx;
385 void *tx_end;
386 void *rx;
387 void *rx_end;
388 enum ssp_reading read;
389 enum ssp_writing write;
390 u32 exp_fifo_level;
391 enum ssp_rx_level_trig rx_lev_trig;
392 enum ssp_tx_level_trig tx_lev_trig;
393
394#ifdef CONFIG_DMA_ENGINE
395 struct dma_chan *dma_rx_channel;
396 struct dma_chan *dma_tx_channel;
397 struct sg_table sgt_rx;
398 struct sg_table sgt_tx;
399 char *dummypage;
400 bool dma_running;
401#endif
402 int cur_cs;
403 int *chipselects;
404};
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422
423struct chip_data {
424 u32 cr0;
425 u16 cr1;
426 u16 dmacr;
427 u16 cpsr;
428 u8 n_bytes;
429 bool enable_dma;
430 enum ssp_reading read;
431 enum ssp_writing write;
432 void (*cs_control) (u32 command);
433 int xfer_type;
434};
435
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439
440
441
442
443static void null_cs_control(u32 command)
444{
445 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command);
446}
447
448static void pl022_cs_control(struct pl022 *pl022, u32 command)
449{
450 if (gpio_is_valid(pl022->cur_cs))
451 gpio_set_value(pl022->cur_cs, command);
452 else
453 pl022->cur_chip->cs_control(command);
454}
455
456
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459
460
461
462static void giveback(struct pl022 *pl022)
463{
464 struct spi_transfer *last_transfer;
465 pl022->next_msg_cs_active = false;
466
467 last_transfer = list_entry(pl022->cur_msg->transfers.prev,
468 struct spi_transfer,
469 transfer_list);
470
471
472 if (last_transfer->delay_usecs)
473
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477 udelay(last_transfer->delay_usecs);
478
479 if (!last_transfer->cs_change) {
480 struct spi_message *next_msg;
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493 next_msg = spi_get_next_queued_message(pl022->master);
494
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498
499 if (next_msg && next_msg->spi != pl022->cur_msg->spi)
500 next_msg = NULL;
501 if (!next_msg || pl022->cur_msg->state == STATE_ERROR)
502 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
503 else
504 pl022->next_msg_cs_active = true;
505
506 }
507
508 pl022->cur_msg = NULL;
509 pl022->cur_transfer = NULL;
510 pl022->cur_chip = NULL;
511 spi_finalize_current_message(pl022->master);
512
513
514 writew((readw(SSP_CR1(pl022->virtbase)) &
515 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
516
517}
518
519
520
521
522
523static int flush(struct pl022 *pl022)
524{
525 unsigned long limit = loops_per_jiffy << 1;
526
527 dev_dbg(&pl022->adev->dev, "flush\n");
528 do {
529 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
530 readw(SSP_DR(pl022->virtbase));
531 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
532
533 pl022->exp_fifo_level = 0;
534
535 return limit;
536}
537
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540
541
542static void restore_state(struct pl022 *pl022)
543{
544 struct chip_data *chip = pl022->cur_chip;
545
546 if (pl022->vendor->extended_cr)
547 writel(chip->cr0, SSP_CR0(pl022->virtbase));
548 else
549 writew(chip->cr0, SSP_CR0(pl022->virtbase));
550 writew(chip->cr1, SSP_CR1(pl022->virtbase));
551 writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
552 writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
553 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
554 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
555}
556
557
558
559
560#define DEFAULT_SSP_REG_CR0 ( \
561 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \
562 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \
563 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
564 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
565 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
566)
567
568
569#define DEFAULT_SSP_REG_CR0_ST ( \
570 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
571 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \
572 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
573 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
574 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
575 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \
576 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \
577)
578
579
580#define DEFAULT_SSP_REG_CR0_ST_PL023 ( \
581 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
582 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
583 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
584 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
585)
586
587#define DEFAULT_SSP_REG_CR1 ( \
588 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
589 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
590 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
591 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \
592)
593
594
595#define DEFAULT_SSP_REG_CR1_ST ( \
596 DEFAULT_SSP_REG_CR1 | \
597 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
598 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
599 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\
600 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
601 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \
602)
603
604
605
606
607
608#define DEFAULT_SSP_REG_CR1_ST_PL023 ( \
609 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
610 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
611 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
612 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
613 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
614 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
615 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \
616 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \
617)
618
619#define DEFAULT_SSP_REG_CPSR ( \
620 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
621)
622
623#define DEFAULT_SSP_REG_DMACR (\
624 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
625 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
626)
627
628
629
630
631
632static void load_ssp_default_config(struct pl022 *pl022)
633{
634 if (pl022->vendor->pl023) {
635 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
636 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
637 } else if (pl022->vendor->extended_cr) {
638 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
639 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
640 } else {
641 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
642 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
643 }
644 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
645 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
646 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
647 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
648}
649
650
651
652
653
654static void readwriter(struct pl022 *pl022)
655{
656
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664
665
666
667 dev_dbg(&pl022->adev->dev,
668 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n",
669 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
670
671
672 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
673 && (pl022->rx < pl022->rx_end)) {
674 switch (pl022->read) {
675 case READING_NULL:
676 readw(SSP_DR(pl022->virtbase));
677 break;
678 case READING_U8:
679 *(u8 *) (pl022->rx) =
680 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
681 break;
682 case READING_U16:
683 *(u16 *) (pl022->rx) =
684 (u16) readw(SSP_DR(pl022->virtbase));
685 break;
686 case READING_U32:
687 *(u32 *) (pl022->rx) =
688 readl(SSP_DR(pl022->virtbase));
689 break;
690 }
691 pl022->rx += (pl022->cur_chip->n_bytes);
692 pl022->exp_fifo_level--;
693 }
694
695
696
697 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth)
698 && (pl022->tx < pl022->tx_end)) {
699 switch (pl022->write) {
700 case WRITING_NULL:
701 writew(0x0, SSP_DR(pl022->virtbase));
702 break;
703 case WRITING_U8:
704 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
705 break;
706 case WRITING_U16:
707 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
708 break;
709 case WRITING_U32:
710 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
711 break;
712 }
713 pl022->tx += (pl022->cur_chip->n_bytes);
714 pl022->exp_fifo_level++;
715
716
717
718
719
720
721 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
722 && (pl022->rx < pl022->rx_end)) {
723 switch (pl022->read) {
724 case READING_NULL:
725 readw(SSP_DR(pl022->virtbase));
726 break;
727 case READING_U8:
728 *(u8 *) (pl022->rx) =
729 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
730 break;
731 case READING_U16:
732 *(u16 *) (pl022->rx) =
733 (u16) readw(SSP_DR(pl022->virtbase));
734 break;
735 case READING_U32:
736 *(u32 *) (pl022->rx) =
737 readl(SSP_DR(pl022->virtbase));
738 break;
739 }
740 pl022->rx += (pl022->cur_chip->n_bytes);
741 pl022->exp_fifo_level--;
742 }
743 }
744
745
746
747
748}
749
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758
759static void *next_transfer(struct pl022 *pl022)
760{
761 struct spi_message *msg = pl022->cur_msg;
762 struct spi_transfer *trans = pl022->cur_transfer;
763
764
765 if (trans->transfer_list.next != &msg->transfers) {
766 pl022->cur_transfer =
767 list_entry(trans->transfer_list.next,
768 struct spi_transfer, transfer_list);
769 return STATE_RUNNING;
770 }
771 return STATE_DONE;
772}
773
774
775
776
777
778#ifdef CONFIG_DMA_ENGINE
779static void unmap_free_dma_scatter(struct pl022 *pl022)
780{
781
782 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl,
783 pl022->sgt_tx.nents, DMA_TO_DEVICE);
784 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl,
785 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
786 sg_free_table(&pl022->sgt_rx);
787 sg_free_table(&pl022->sgt_tx);
788}
789
790static void dma_callback(void *data)
791{
792 struct pl022 *pl022 = data;
793 struct spi_message *msg = pl022->cur_msg;
794
795 BUG_ON(!pl022->sgt_rx.sgl);
796
797#ifdef VERBOSE_DEBUG
798
799
800
801
802
803
804 {
805 struct scatterlist *sg;
806 unsigned int i;
807
808 dma_sync_sg_for_cpu(&pl022->adev->dev,
809 pl022->sgt_rx.sgl,
810 pl022->sgt_rx.nents,
811 DMA_FROM_DEVICE);
812
813 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) {
814 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i);
815 print_hex_dump(KERN_ERR, "SPI RX: ",
816 DUMP_PREFIX_OFFSET,
817 16,
818 1,
819 sg_virt(sg),
820 sg_dma_len(sg),
821 1);
822 }
823 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) {
824 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i);
825 print_hex_dump(KERN_ERR, "SPI TX: ",
826 DUMP_PREFIX_OFFSET,
827 16,
828 1,
829 sg_virt(sg),
830 sg_dma_len(sg),
831 1);
832 }
833 }
834#endif
835
836 unmap_free_dma_scatter(pl022);
837
838
839 msg->actual_length += pl022->cur_transfer->len;
840 if (pl022->cur_transfer->cs_change)
841 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
842
843
844 msg->state = next_transfer(pl022);
845 tasklet_schedule(&pl022->pump_transfers);
846}
847
848static void setup_dma_scatter(struct pl022 *pl022,
849 void *buffer,
850 unsigned int length,
851 struct sg_table *sgtab)
852{
853 struct scatterlist *sg;
854 int bytesleft = length;
855 void *bufp = buffer;
856 int mapbytes;
857 int i;
858
859 if (buffer) {
860 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
861
862
863
864
865
866
867 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp)))
868 mapbytes = bytesleft;
869 else
870 mapbytes = PAGE_SIZE - offset_in_page(bufp);
871 sg_set_page(sg, virt_to_page(bufp),
872 mapbytes, offset_in_page(bufp));
873 bufp += mapbytes;
874 bytesleft -= mapbytes;
875 dev_dbg(&pl022->adev->dev,
876 "set RX/TX target page @ %p, %d bytes, %d left\n",
877 bufp, mapbytes, bytesleft);
878 }
879 } else {
880
881 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
882 if (bytesleft < PAGE_SIZE)
883 mapbytes = bytesleft;
884 else
885 mapbytes = PAGE_SIZE;
886 sg_set_page(sg, virt_to_page(pl022->dummypage),
887 mapbytes, 0);
888 bytesleft -= mapbytes;
889 dev_dbg(&pl022->adev->dev,
890 "set RX/TX to dummy page %d bytes, %d left\n",
891 mapbytes, bytesleft);
892
893 }
894 }
895 BUG_ON(bytesleft);
896}
897
898
899
900
901
902static int configure_dma(struct pl022 *pl022)
903{
904 struct dma_slave_config rx_conf = {
905 .src_addr = SSP_DR(pl022->phybase),
906 .direction = DMA_DEV_TO_MEM,
907 .device_fc = false,
908 };
909 struct dma_slave_config tx_conf = {
910 .dst_addr = SSP_DR(pl022->phybase),
911 .direction = DMA_MEM_TO_DEV,
912 .device_fc = false,
913 };
914 unsigned int pages;
915 int ret;
916 int rx_sglen, tx_sglen;
917 struct dma_chan *rxchan = pl022->dma_rx_channel;
918 struct dma_chan *txchan = pl022->dma_tx_channel;
919 struct dma_async_tx_descriptor *rxdesc;
920 struct dma_async_tx_descriptor *txdesc;
921
922
923 if (!rxchan || !txchan)
924 return -ENODEV;
925
926
927
928
929
930
931
932 switch (pl022->rx_lev_trig) {
933 case SSP_RX_1_OR_MORE_ELEM:
934 rx_conf.src_maxburst = 1;
935 break;
936 case SSP_RX_4_OR_MORE_ELEM:
937 rx_conf.src_maxburst = 4;
938 break;
939 case SSP_RX_8_OR_MORE_ELEM:
940 rx_conf.src_maxburst = 8;
941 break;
942 case SSP_RX_16_OR_MORE_ELEM:
943 rx_conf.src_maxburst = 16;
944 break;
945 case SSP_RX_32_OR_MORE_ELEM:
946 rx_conf.src_maxburst = 32;
947 break;
948 default:
949 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1;
950 break;
951 }
952
953 switch (pl022->tx_lev_trig) {
954 case SSP_TX_1_OR_MORE_EMPTY_LOC:
955 tx_conf.dst_maxburst = 1;
956 break;
957 case SSP_TX_4_OR_MORE_EMPTY_LOC:
958 tx_conf.dst_maxburst = 4;
959 break;
960 case SSP_TX_8_OR_MORE_EMPTY_LOC:
961 tx_conf.dst_maxburst = 8;
962 break;
963 case SSP_TX_16_OR_MORE_EMPTY_LOC:
964 tx_conf.dst_maxburst = 16;
965 break;
966 case SSP_TX_32_OR_MORE_EMPTY_LOC:
967 tx_conf.dst_maxburst = 32;
968 break;
969 default:
970 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1;
971 break;
972 }
973
974 switch (pl022->read) {
975 case READING_NULL:
976
977 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
978 break;
979 case READING_U8:
980 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
981 break;
982 case READING_U16:
983 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
984 break;
985 case READING_U32:
986 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
987 break;
988 }
989
990 switch (pl022->write) {
991 case WRITING_NULL:
992
993 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
994 break;
995 case WRITING_U8:
996 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
997 break;
998 case WRITING_U16:
999 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1000 break;
1001 case WRITING_U32:
1002 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1003 break;
1004 }
1005
1006
1007 if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
1008 rx_conf.src_addr_width = tx_conf.dst_addr_width;
1009 if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
1010 tx_conf.dst_addr_width = rx_conf.src_addr_width;
1011 BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width);
1012
1013 dmaengine_slave_config(rxchan, &rx_conf);
1014 dmaengine_slave_config(txchan, &tx_conf);
1015
1016
1017 pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE);
1018 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages);
1019
1020 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC);
1021 if (ret)
1022 goto err_alloc_rx_sg;
1023
1024 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC);
1025 if (ret)
1026 goto err_alloc_tx_sg;
1027
1028
1029 setup_dma_scatter(pl022, pl022->rx,
1030 pl022->cur_transfer->len, &pl022->sgt_rx);
1031 setup_dma_scatter(pl022, pl022->tx,
1032 pl022->cur_transfer->len, &pl022->sgt_tx);
1033
1034
1035 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
1036 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
1037 if (!rx_sglen)
1038 goto err_rx_sgmap;
1039
1040 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl,
1041 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1042 if (!tx_sglen)
1043 goto err_tx_sgmap;
1044
1045
1046 rxdesc = dmaengine_prep_slave_sg(rxchan,
1047 pl022->sgt_rx.sgl,
1048 rx_sglen,
1049 DMA_DEV_TO_MEM,
1050 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1051 if (!rxdesc)
1052 goto err_rxdesc;
1053
1054 txdesc = dmaengine_prep_slave_sg(txchan,
1055 pl022->sgt_tx.sgl,
1056 tx_sglen,
1057 DMA_MEM_TO_DEV,
1058 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1059 if (!txdesc)
1060 goto err_txdesc;
1061
1062
1063 rxdesc->callback = dma_callback;
1064 rxdesc->callback_param = pl022;
1065
1066
1067 dmaengine_submit(rxdesc);
1068 dmaengine_submit(txdesc);
1069 dma_async_issue_pending(rxchan);
1070 dma_async_issue_pending(txchan);
1071 pl022->dma_running = true;
1072
1073 return 0;
1074
1075err_txdesc:
1076 dmaengine_terminate_all(txchan);
1077err_rxdesc:
1078 dmaengine_terminate_all(rxchan);
1079 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl,
1080 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1081err_tx_sgmap:
1082 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
1083 pl022->sgt_tx.nents, DMA_FROM_DEVICE);
1084err_rx_sgmap:
1085 sg_free_table(&pl022->sgt_tx);
1086err_alloc_tx_sg:
1087 sg_free_table(&pl022->sgt_rx);
1088err_alloc_rx_sg:
1089 return -ENOMEM;
1090}
1091
1092static int pl022_dma_probe(struct pl022 *pl022)
1093{
1094 dma_cap_mask_t mask;
1095
1096
1097 dma_cap_zero(mask);
1098 dma_cap_set(DMA_SLAVE, mask);
1099
1100
1101
1102
1103 pl022->dma_rx_channel = dma_request_channel(mask,
1104 pl022->master_info->dma_filter,
1105 pl022->master_info->dma_rx_param);
1106 if (!pl022->dma_rx_channel) {
1107 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n");
1108 goto err_no_rxchan;
1109 }
1110
1111 pl022->dma_tx_channel = dma_request_channel(mask,
1112 pl022->master_info->dma_filter,
1113 pl022->master_info->dma_tx_param);
1114 if (!pl022->dma_tx_channel) {
1115 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n");
1116 goto err_no_txchan;
1117 }
1118
1119 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1120 if (!pl022->dummypage) {
1121 dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n");
1122 goto err_no_dummypage;
1123 }
1124
1125 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
1126 dma_chan_name(pl022->dma_rx_channel),
1127 dma_chan_name(pl022->dma_tx_channel));
1128
1129 return 0;
1130
1131err_no_dummypage:
1132 dma_release_channel(pl022->dma_tx_channel);
1133err_no_txchan:
1134 dma_release_channel(pl022->dma_rx_channel);
1135 pl022->dma_rx_channel = NULL;
1136err_no_rxchan:
1137 dev_err(&pl022->adev->dev,
1138 "Failed to work in dma mode, work without dma!\n");
1139 return -ENODEV;
1140}
1141
1142static int pl022_dma_autoprobe(struct pl022 *pl022)
1143{
1144 struct device *dev = &pl022->adev->dev;
1145
1146
1147 pl022->dma_rx_channel = dma_request_slave_channel(dev, "rx");
1148 if (!pl022->dma_rx_channel)
1149 goto err_no_rxchan;
1150
1151 pl022->dma_tx_channel = dma_request_slave_channel(dev, "tx");
1152 if (!pl022->dma_tx_channel)
1153 goto err_no_txchan;
1154
1155 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1156 if (!pl022->dummypage)
1157 goto err_no_dummypage;
1158
1159 return 0;
1160
1161err_no_dummypage:
1162 dma_release_channel(pl022->dma_tx_channel);
1163 pl022->dma_tx_channel = NULL;
1164err_no_txchan:
1165 dma_release_channel(pl022->dma_rx_channel);
1166 pl022->dma_rx_channel = NULL;
1167err_no_rxchan:
1168 return -ENODEV;
1169}
1170
1171static void terminate_dma(struct pl022 *pl022)
1172{
1173 struct dma_chan *rxchan = pl022->dma_rx_channel;
1174 struct dma_chan *txchan = pl022->dma_tx_channel;
1175
1176 dmaengine_terminate_all(rxchan);
1177 dmaengine_terminate_all(txchan);
1178 unmap_free_dma_scatter(pl022);
1179 pl022->dma_running = false;
1180}
1181
1182static void pl022_dma_remove(struct pl022 *pl022)
1183{
1184 if (pl022->dma_running)
1185 terminate_dma(pl022);
1186 if (pl022->dma_tx_channel)
1187 dma_release_channel(pl022->dma_tx_channel);
1188 if (pl022->dma_rx_channel)
1189 dma_release_channel(pl022->dma_rx_channel);
1190 kfree(pl022->dummypage);
1191}
1192
1193#else
1194static inline int configure_dma(struct pl022 *pl022)
1195{
1196 return -ENODEV;
1197}
1198
1199static inline int pl022_dma_autoprobe(struct pl022 *pl022)
1200{
1201 return 0;
1202}
1203
1204static inline int pl022_dma_probe(struct pl022 *pl022)
1205{
1206 return 0;
1207}
1208
1209static inline void pl022_dma_remove(struct pl022 *pl022)
1210{
1211}
1212#endif
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
1226{
1227 struct pl022 *pl022 = dev_id;
1228 struct spi_message *msg = pl022->cur_msg;
1229 u16 irq_status = 0;
1230 u16 flag = 0;
1231
1232 if (unlikely(!msg)) {
1233 dev_err(&pl022->adev->dev,
1234 "bad message state in interrupt handler");
1235
1236 return IRQ_HANDLED;
1237 }
1238
1239
1240 irq_status = readw(SSP_MIS(pl022->virtbase));
1241
1242 if (unlikely(!irq_status))
1243 return IRQ_NONE;
1244
1245
1246
1247
1248
1249
1250 if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) {
1251
1252
1253
1254
1255 dev_err(&pl022->adev->dev, "FIFO overrun\n");
1256 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
1257 dev_err(&pl022->adev->dev,
1258 "RXFIFO is full\n");
1259 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF)
1260 dev_err(&pl022->adev->dev,
1261 "TXFIFO is full\n");
1262
1263
1264
1265
1266
1267
1268 writew(DISABLE_ALL_INTERRUPTS,
1269 SSP_IMSC(pl022->virtbase));
1270 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1271 writew((readw(SSP_CR1(pl022->virtbase)) &
1272 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1273 msg->state = STATE_ERROR;
1274
1275
1276 tasklet_schedule(&pl022->pump_transfers);
1277 return IRQ_HANDLED;
1278 }
1279
1280 readwriter(pl022);
1281
1282 if ((pl022->tx == pl022->tx_end) && (flag == 0)) {
1283 flag = 1;
1284
1285 writew((readw(SSP_IMSC(pl022->virtbase)) &
1286 ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM,
1287 SSP_IMSC(pl022->virtbase));
1288 }
1289
1290
1291
1292
1293
1294
1295 if (pl022->rx >= pl022->rx_end) {
1296 writew(DISABLE_ALL_INTERRUPTS,
1297 SSP_IMSC(pl022->virtbase));
1298 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1299 if (unlikely(pl022->rx > pl022->rx_end)) {
1300 dev_warn(&pl022->adev->dev, "read %u surplus "
1301 "bytes (did you request an odd "
1302 "number of bytes on a 16bit bus?)\n",
1303 (u32) (pl022->rx - pl022->rx_end));
1304 }
1305
1306 msg->actual_length += pl022->cur_transfer->len;
1307 if (pl022->cur_transfer->cs_change)
1308 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
1309
1310 msg->state = next_transfer(pl022);
1311 tasklet_schedule(&pl022->pump_transfers);
1312 return IRQ_HANDLED;
1313 }
1314
1315 return IRQ_HANDLED;
1316}
1317
1318
1319
1320
1321
1322static int set_up_next_transfer(struct pl022 *pl022,
1323 struct spi_transfer *transfer)
1324{
1325 int residue;
1326
1327
1328 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes;
1329 if (unlikely(residue != 0)) {
1330 dev_err(&pl022->adev->dev,
1331 "message of %u bytes to transmit but the current "
1332 "chip bus has a data width of %u bytes!\n",
1333 pl022->cur_transfer->len,
1334 pl022->cur_chip->n_bytes);
1335 dev_err(&pl022->adev->dev, "skipping this message\n");
1336 return -EIO;
1337 }
1338 pl022->tx = (void *)transfer->tx_buf;
1339 pl022->tx_end = pl022->tx + pl022->cur_transfer->len;
1340 pl022->rx = (void *)transfer->rx_buf;
1341 pl022->rx_end = pl022->rx + pl022->cur_transfer->len;
1342 pl022->write =
1343 pl022->tx ? pl022->cur_chip->write : WRITING_NULL;
1344 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL;
1345 return 0;
1346}
1347
1348
1349
1350
1351
1352
1353
1354static void pump_transfers(unsigned long data)
1355{
1356 struct pl022 *pl022 = (struct pl022 *) data;
1357 struct spi_message *message = NULL;
1358 struct spi_transfer *transfer = NULL;
1359 struct spi_transfer *previous = NULL;
1360
1361
1362 message = pl022->cur_msg;
1363 transfer = pl022->cur_transfer;
1364
1365
1366 if (message->state == STATE_ERROR) {
1367 message->status = -EIO;
1368 giveback(pl022);
1369 return;
1370 }
1371
1372
1373 if (message->state == STATE_DONE) {
1374 message->status = 0;
1375 giveback(pl022);
1376 return;
1377 }
1378
1379
1380 if (message->state == STATE_RUNNING) {
1381 previous = list_entry(transfer->transfer_list.prev,
1382 struct spi_transfer,
1383 transfer_list);
1384 if (previous->delay_usecs)
1385
1386
1387
1388
1389 udelay(previous->delay_usecs);
1390
1391
1392 if (previous->cs_change)
1393 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1394 } else {
1395
1396 message->state = STATE_RUNNING;
1397 }
1398
1399 if (set_up_next_transfer(pl022, transfer)) {
1400 message->state = STATE_ERROR;
1401 message->status = -EIO;
1402 giveback(pl022);
1403 return;
1404 }
1405
1406 flush(pl022);
1407
1408 if (pl022->cur_chip->enable_dma) {
1409 if (configure_dma(pl022)) {
1410 dev_dbg(&pl022->adev->dev,
1411 "configuration of DMA failed, fall back to interrupt mode\n");
1412 goto err_config_dma;
1413 }
1414 return;
1415 }
1416
1417err_config_dma:
1418
1419 writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase));
1420}
1421
1422static void do_interrupt_dma_transfer(struct pl022 *pl022)
1423{
1424
1425
1426
1427
1428 u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM;
1429
1430
1431 if (!pl022->next_msg_cs_active)
1432 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1433
1434 if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
1435
1436 pl022->cur_msg->state = STATE_ERROR;
1437 pl022->cur_msg->status = -EIO;
1438 giveback(pl022);
1439 return;
1440 }
1441
1442 if (pl022->cur_chip->enable_dma) {
1443
1444 if (configure_dma(pl022)) {
1445 dev_dbg(&pl022->adev->dev,
1446 "configuration of DMA failed, fall back to interrupt mode\n");
1447 goto err_config_dma;
1448 }
1449
1450 irqflags = DISABLE_ALL_INTERRUPTS;
1451 }
1452err_config_dma:
1453
1454 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1455 SSP_CR1(pl022->virtbase));
1456 writew(irqflags, SSP_IMSC(pl022->virtbase));
1457}
1458
1459static void do_polling_transfer(struct pl022 *pl022)
1460{
1461 struct spi_message *message = NULL;
1462 struct spi_transfer *transfer = NULL;
1463 struct spi_transfer *previous = NULL;
1464 struct chip_data *chip;
1465 unsigned long time, timeout;
1466
1467 chip = pl022->cur_chip;
1468 message = pl022->cur_msg;
1469
1470 while (message->state != STATE_DONE) {
1471
1472 if (message->state == STATE_ERROR)
1473 break;
1474 transfer = pl022->cur_transfer;
1475
1476
1477 if (message->state == STATE_RUNNING) {
1478 previous =
1479 list_entry(transfer->transfer_list.prev,
1480 struct spi_transfer, transfer_list);
1481 if (previous->delay_usecs)
1482 udelay(previous->delay_usecs);
1483 if (previous->cs_change)
1484 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1485 } else {
1486
1487 message->state = STATE_RUNNING;
1488 if (!pl022->next_msg_cs_active)
1489 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1490 }
1491
1492
1493 if (set_up_next_transfer(pl022, transfer)) {
1494
1495 message->state = STATE_ERROR;
1496 break;
1497 }
1498
1499 flush(pl022);
1500 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1501 SSP_CR1(pl022->virtbase));
1502
1503 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
1504
1505 timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT);
1506 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) {
1507 time = jiffies;
1508 readwriter(pl022);
1509 if (time_after(time, timeout)) {
1510 dev_warn(&pl022->adev->dev,
1511 "%s: timeout!\n", __func__);
1512 message->state = STATE_ERROR;
1513 goto out;
1514 }
1515 cpu_relax();
1516 }
1517
1518
1519 message->actual_length += pl022->cur_transfer->len;
1520 if (pl022->cur_transfer->cs_change)
1521 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
1522
1523 message->state = next_transfer(pl022);
1524 }
1525out:
1526
1527 if (message->state == STATE_DONE)
1528 message->status = 0;
1529 else
1530 message->status = -EIO;
1531
1532 giveback(pl022);
1533 return;
1534}
1535
1536static int pl022_transfer_one_message(struct spi_master *master,
1537 struct spi_message *msg)
1538{
1539 struct pl022 *pl022 = spi_master_get_devdata(master);
1540
1541
1542 pl022->cur_msg = msg;
1543 msg->state = STATE_START;
1544
1545 pl022->cur_transfer = list_entry(msg->transfers.next,
1546 struct spi_transfer, transfer_list);
1547
1548
1549 pl022->cur_chip = spi_get_ctldata(msg->spi);
1550 pl022->cur_cs = pl022->chipselects[msg->spi->chip_select];
1551
1552 restore_state(pl022);
1553 flush(pl022);
1554
1555 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
1556 do_polling_transfer(pl022);
1557 else
1558 do_interrupt_dma_transfer(pl022);
1559
1560 return 0;
1561}
1562
1563static int pl022_prepare_transfer_hardware(struct spi_master *master)
1564{
1565 struct pl022 *pl022 = spi_master_get_devdata(master);
1566
1567
1568
1569
1570
1571 pm_runtime_get_sync(&pl022->adev->dev);
1572 return 0;
1573}
1574
1575static int pl022_unprepare_transfer_hardware(struct spi_master *master)
1576{
1577 struct pl022 *pl022 = spi_master_get_devdata(master);
1578
1579
1580 writew((readw(SSP_CR1(pl022->virtbase)) &
1581 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1582
1583 if (pl022->master_info->autosuspend_delay > 0) {
1584 pm_runtime_mark_last_busy(&pl022->adev->dev);
1585 pm_runtime_put_autosuspend(&pl022->adev->dev);
1586 } else {
1587 pm_runtime_put(&pl022->adev->dev);
1588 }
1589
1590 return 0;
1591}
1592
1593static int verify_controller_parameters(struct pl022 *pl022,
1594 struct pl022_config_chip const *chip_info)
1595{
1596 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI)
1597 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) {
1598 dev_err(&pl022->adev->dev,
1599 "interface is configured incorrectly\n");
1600 return -EINVAL;
1601 }
1602 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) &&
1603 (!pl022->vendor->unidir)) {
1604 dev_err(&pl022->adev->dev,
1605 "unidirectional mode not supported in this "
1606 "hardware version\n");
1607 return -EINVAL;
1608 }
1609 if ((chip_info->hierarchy != SSP_MASTER)
1610 && (chip_info->hierarchy != SSP_SLAVE)) {
1611 dev_err(&pl022->adev->dev,
1612 "hierarchy is configured incorrectly\n");
1613 return -EINVAL;
1614 }
1615 if ((chip_info->com_mode != INTERRUPT_TRANSFER)
1616 && (chip_info->com_mode != DMA_TRANSFER)
1617 && (chip_info->com_mode != POLLING_TRANSFER)) {
1618 dev_err(&pl022->adev->dev,
1619 "Communication mode is configured incorrectly\n");
1620 return -EINVAL;
1621 }
1622 switch (chip_info->rx_lev_trig) {
1623 case SSP_RX_1_OR_MORE_ELEM:
1624 case SSP_RX_4_OR_MORE_ELEM:
1625 case SSP_RX_8_OR_MORE_ELEM:
1626
1627 break;
1628 case SSP_RX_16_OR_MORE_ELEM:
1629 if (pl022->vendor->fifodepth < 16) {
1630 dev_err(&pl022->adev->dev,
1631 "RX FIFO Trigger Level is configured incorrectly\n");
1632 return -EINVAL;
1633 }
1634 break;
1635 case SSP_RX_32_OR_MORE_ELEM:
1636 if (pl022->vendor->fifodepth < 32) {
1637 dev_err(&pl022->adev->dev,
1638 "RX FIFO Trigger Level is configured incorrectly\n");
1639 return -EINVAL;
1640 }
1641 break;
1642 default:
1643 dev_err(&pl022->adev->dev,
1644 "RX FIFO Trigger Level is configured incorrectly\n");
1645 return -EINVAL;
1646 break;
1647 }
1648 switch (chip_info->tx_lev_trig) {
1649 case SSP_TX_1_OR_MORE_EMPTY_LOC:
1650 case SSP_TX_4_OR_MORE_EMPTY_LOC:
1651 case SSP_TX_8_OR_MORE_EMPTY_LOC:
1652
1653 break;
1654 case SSP_TX_16_OR_MORE_EMPTY_LOC:
1655 if (pl022->vendor->fifodepth < 16) {
1656 dev_err(&pl022->adev->dev,
1657 "TX FIFO Trigger Level is configured incorrectly\n");
1658 return -EINVAL;
1659 }
1660 break;
1661 case SSP_TX_32_OR_MORE_EMPTY_LOC:
1662 if (pl022->vendor->fifodepth < 32) {
1663 dev_err(&pl022->adev->dev,
1664 "TX FIFO Trigger Level is configured incorrectly\n");
1665 return -EINVAL;
1666 }
1667 break;
1668 default:
1669 dev_err(&pl022->adev->dev,
1670 "TX FIFO Trigger Level is configured incorrectly\n");
1671 return -EINVAL;
1672 break;
1673 }
1674 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {
1675 if ((chip_info->ctrl_len < SSP_BITS_4)
1676 || (chip_info->ctrl_len > SSP_BITS_32)) {
1677 dev_err(&pl022->adev->dev,
1678 "CTRL LEN is configured incorrectly\n");
1679 return -EINVAL;
1680 }
1681 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO)
1682 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) {
1683 dev_err(&pl022->adev->dev,
1684 "Wait State is configured incorrectly\n");
1685 return -EINVAL;
1686 }
1687
1688 if (pl022->vendor->extended_cr) {
1689 if ((chip_info->duplex !=
1690 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1691 && (chip_info->duplex !=
1692 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) {
1693 dev_err(&pl022->adev->dev,
1694 "Microwire duplex mode is configured incorrectly\n");
1695 return -EINVAL;
1696 }
1697 } else {
1698 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1699 dev_err(&pl022->adev->dev,
1700 "Microwire half duplex mode requested,"
1701 " but this is only available in the"
1702 " ST version of PL022\n");
1703 return -EINVAL;
1704 }
1705 }
1706 return 0;
1707}
1708
1709static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
1710{
1711 return rate / (cpsdvsr * (1 + scr));
1712}
1713
1714static int calculate_effective_freq(struct pl022 *pl022, int freq, struct
1715 ssp_clock_params * clk_freq)
1716{
1717
1718 u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN;
1719 u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0,
1720 best_scr = 0, tmp, found = 0;
1721
1722 rate = clk_get_rate(pl022->clk);
1723
1724 max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN);
1725
1726 min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX);
1727
1728 if (freq > max_tclk)
1729 dev_warn(&pl022->adev->dev,
1730 "Max speed that can be programmed is %d Hz, you requested %d\n",
1731 max_tclk, freq);
1732
1733 if (freq < min_tclk) {
1734 dev_err(&pl022->adev->dev,
1735 "Requested frequency: %d Hz is less than minimum possible %d Hz\n",
1736 freq, min_tclk);
1737 return -EINVAL;
1738 }
1739
1740
1741
1742
1743
1744 while ((cpsdvsr <= CPSDVR_MAX) && !found) {
1745 while (scr <= SCR_MAX) {
1746 tmp = spi_rate(rate, cpsdvsr, scr);
1747
1748 if (tmp > freq) {
1749
1750 scr++;
1751 continue;
1752 }
1753
1754
1755
1756
1757
1758 if (tmp > best_freq) {
1759 best_freq = tmp;
1760 best_cpsdvsr = cpsdvsr;
1761 best_scr = scr;
1762
1763 if (tmp == freq)
1764 found = 1;
1765 }
1766
1767
1768
1769
1770 break;
1771 }
1772 cpsdvsr += 2;
1773 scr = SCR_MIN;
1774 }
1775
1776 WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n",
1777 freq);
1778
1779 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF);
1780 clk_freq->scr = (u8) (best_scr & 0xFF);
1781 dev_dbg(&pl022->adev->dev,
1782 "SSP Target Frequency is: %u, Effective Frequency is %u\n",
1783 freq, best_freq);
1784 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n",
1785 clk_freq->cpsdvsr, clk_freq->scr);
1786
1787 return 0;
1788}
1789
1790
1791
1792
1793
1794static const struct pl022_config_chip pl022_default_chip_info = {
1795 .com_mode = POLLING_TRANSFER,
1796 .iface = SSP_INTERFACE_MOTOROLA_SPI,
1797 .hierarchy = SSP_SLAVE,
1798 .slave_tx_disable = DO_NOT_DRIVE_TX,
1799 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
1800 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
1801 .ctrl_len = SSP_BITS_8,
1802 .wait_state = SSP_MWIRE_WAIT_ZERO,
1803 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
1804 .cs_control = null_cs_control,
1805};
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819static int pl022_setup(struct spi_device *spi)
1820{
1821 struct pl022_config_chip const *chip_info;
1822 struct pl022_config_chip chip_info_dt;
1823 struct chip_data *chip;
1824 struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0};
1825 int status = 0;
1826 struct pl022 *pl022 = spi_master_get_devdata(spi->master);
1827 unsigned int bits = spi->bits_per_word;
1828 u32 tmp;
1829 struct device_node *np = spi->dev.of_node;
1830
1831 if (!spi->max_speed_hz)
1832 return -EINVAL;
1833
1834
1835 chip = spi_get_ctldata(spi);
1836
1837 if (chip == NULL) {
1838 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1839 if (!chip) {
1840 dev_err(&spi->dev,
1841 "cannot allocate controller state\n");
1842 return -ENOMEM;
1843 }
1844 dev_dbg(&spi->dev,
1845 "allocated memory for controller's runtime state\n");
1846 }
1847
1848
1849 chip_info = spi->controller_data;
1850
1851 if (chip_info == NULL) {
1852 if (np) {
1853 chip_info_dt = pl022_default_chip_info;
1854
1855 chip_info_dt.hierarchy = SSP_MASTER;
1856 of_property_read_u32(np, "pl022,interface",
1857 &chip_info_dt.iface);
1858 of_property_read_u32(np, "pl022,com-mode",
1859 &chip_info_dt.com_mode);
1860 of_property_read_u32(np, "pl022,rx-level-trig",
1861 &chip_info_dt.rx_lev_trig);
1862 of_property_read_u32(np, "pl022,tx-level-trig",
1863 &chip_info_dt.tx_lev_trig);
1864 of_property_read_u32(np, "pl022,ctrl-len",
1865 &chip_info_dt.ctrl_len);
1866 of_property_read_u32(np, "pl022,wait-state",
1867 &chip_info_dt.wait_state);
1868 of_property_read_u32(np, "pl022,duplex",
1869 &chip_info_dt.duplex);
1870
1871 chip_info = &chip_info_dt;
1872 } else {
1873 chip_info = &pl022_default_chip_info;
1874
1875 dev_dbg(&spi->dev,
1876 "using default controller_data settings\n");
1877 }
1878 } else
1879 dev_dbg(&spi->dev,
1880 "using user supplied controller_data settings\n");
1881
1882
1883
1884
1885
1886 if ((0 == chip_info->clk_freq.cpsdvsr)
1887 && (0 == chip_info->clk_freq.scr)) {
1888 status = calculate_effective_freq(pl022,
1889 spi->max_speed_hz,
1890 &clk_freq);
1891 if (status < 0)
1892 goto err_config_params;
1893 } else {
1894 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq));
1895 if ((clk_freq.cpsdvsr % 2) != 0)
1896 clk_freq.cpsdvsr =
1897 clk_freq.cpsdvsr - 1;
1898 }
1899 if ((clk_freq.cpsdvsr < CPSDVR_MIN)
1900 || (clk_freq.cpsdvsr > CPSDVR_MAX)) {
1901 status = -EINVAL;
1902 dev_err(&spi->dev,
1903 "cpsdvsr is configured incorrectly\n");
1904 goto err_config_params;
1905 }
1906
1907 status = verify_controller_parameters(pl022, chip_info);
1908 if (status) {
1909 dev_err(&spi->dev, "controller data is incorrect");
1910 goto err_config_params;
1911 }
1912
1913 pl022->rx_lev_trig = chip_info->rx_lev_trig;
1914 pl022->tx_lev_trig = chip_info->tx_lev_trig;
1915
1916
1917 chip->xfer_type = chip_info->com_mode;
1918 if (!chip_info->cs_control) {
1919 chip->cs_control = null_cs_control;
1920 if (!gpio_is_valid(pl022->chipselects[spi->chip_select]))
1921 dev_warn(&spi->dev,
1922 "invalid chip select\n");
1923 } else
1924 chip->cs_control = chip_info->cs_control;
1925
1926
1927 if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) {
1928 status = -ENOTSUPP;
1929 dev_err(&spi->dev, "illegal data size for this controller!\n");
1930 dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n",
1931 pl022->vendor->max_bpw);
1932 goto err_config_params;
1933 } else if (bits <= 8) {
1934 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n");
1935 chip->n_bytes = 1;
1936 chip->read = READING_U8;
1937 chip->write = WRITING_U8;
1938 } else if (bits <= 16) {
1939 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n");
1940 chip->n_bytes = 2;
1941 chip->read = READING_U16;
1942 chip->write = WRITING_U16;
1943 } else {
1944 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n");
1945 chip->n_bytes = 4;
1946 chip->read = READING_U32;
1947 chip->write = WRITING_U32;
1948 }
1949
1950
1951 chip->cr0 = 0;
1952 chip->cr1 = 0;
1953 chip->dmacr = 0;
1954 chip->cpsr = 0;
1955 if ((chip_info->com_mode == DMA_TRANSFER)
1956 && ((pl022->master_info)->enable_dma)) {
1957 chip->enable_dma = true;
1958 dev_dbg(&spi->dev, "DMA mode set in controller state\n");
1959 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1960 SSP_DMACR_MASK_RXDMAE, 0);
1961 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1962 SSP_DMACR_MASK_TXDMAE, 1);
1963 } else {
1964 chip->enable_dma = false;
1965 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n");
1966 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1967 SSP_DMACR_MASK_RXDMAE, 0);
1968 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1969 SSP_DMACR_MASK_TXDMAE, 1);
1970 }
1971
1972 chip->cpsr = clk_freq.cpsdvsr;
1973
1974
1975 if (pl022->vendor->extended_cr) {
1976 u32 etx;
1977
1978 if (pl022->vendor->pl023) {
1979
1980 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
1981 SSP_CR1_MASK_FBCLKDEL_ST, 13);
1982 } else {
1983
1984 SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
1985 SSP_CR0_MASK_HALFDUP_ST, 5);
1986 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
1987 SSP_CR0_MASK_CSS_ST, 16);
1988 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
1989 SSP_CR0_MASK_FRF_ST, 21);
1990 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
1991 SSP_CR1_MASK_MWAIT_ST, 6);
1992 }
1993 SSP_WRITE_BITS(chip->cr0, bits - 1,
1994 SSP_CR0_MASK_DSS_ST, 0);
1995
1996 if (spi->mode & SPI_LSB_FIRST) {
1997 tmp = SSP_RX_LSB;
1998 etx = SSP_TX_LSB;
1999 } else {
2000 tmp = SSP_RX_MSB;
2001 etx = SSP_TX_MSB;
2002 }
2003 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);
2004 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);
2005 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
2006 SSP_CR1_MASK_RXIFLSEL_ST, 7);
2007 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
2008 SSP_CR1_MASK_TXIFLSEL_ST, 10);
2009 } else {
2010 SSP_WRITE_BITS(chip->cr0, bits - 1,
2011 SSP_CR0_MASK_DSS, 0);
2012 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
2013 SSP_CR0_MASK_FRF, 4);
2014 }
2015
2016
2017 if (spi->mode & SPI_CPOL)
2018 tmp = SSP_CLK_POL_IDLE_HIGH;
2019 else
2020 tmp = SSP_CLK_POL_IDLE_LOW;
2021 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);
2022
2023 if (spi->mode & SPI_CPHA)
2024 tmp = SSP_CLK_SECOND_EDGE;
2025 else
2026 tmp = SSP_CLK_FIRST_EDGE;
2027 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);
2028
2029 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8);
2030
2031 if (pl022->vendor->loopback) {
2032 if (spi->mode & SPI_LOOP)
2033 tmp = LOOPBACK_ENABLED;
2034 else
2035 tmp = LOOPBACK_DISABLED;
2036 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);
2037 }
2038 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
2039 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
2040 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD,
2041 3);
2042
2043
2044 spi_set_ctldata(spi, chip);
2045 return status;
2046 err_config_params:
2047 spi_set_ctldata(spi, NULL);
2048 kfree(chip);
2049 return status;
2050}
2051
2052
2053
2054
2055
2056
2057
2058
2059static void pl022_cleanup(struct spi_device *spi)
2060{
2061 struct chip_data *chip = spi_get_ctldata(spi);
2062
2063 spi_set_ctldata(spi, NULL);
2064 kfree(chip);
2065}
2066
2067static struct pl022_ssp_controller *
2068pl022_platform_data_dt_get(struct device *dev)
2069{
2070 struct device_node *np = dev->of_node;
2071 struct pl022_ssp_controller *pd;
2072 u32 tmp;
2073
2074 if (!np) {
2075 dev_err(dev, "no dt node defined\n");
2076 return NULL;
2077 }
2078
2079 pd = devm_kzalloc(dev, sizeof(struct pl022_ssp_controller), GFP_KERNEL);
2080 if (!pd) {
2081 dev_err(dev, "cannot allocate platform data memory\n");
2082 return NULL;
2083 }
2084
2085 pd->bus_id = -1;
2086 of_property_read_u32(np, "num-cs", &tmp);
2087 pd->num_chipselect = tmp;
2088 of_property_read_u32(np, "pl022,autosuspend-delay",
2089 &pd->autosuspend_delay);
2090 pd->rt = of_property_read_bool(np, "pl022,rt");
2091
2092 return pd;
2093}
2094
2095static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
2096{
2097 struct device *dev = &adev->dev;
2098 struct pl022_ssp_controller *platform_info = adev->dev.platform_data;
2099 struct spi_master *master;
2100 struct pl022 *pl022 = NULL;
2101 struct device_node *np = adev->dev.of_node;
2102 int status = 0, i, num_cs;
2103
2104 dev_info(&adev->dev,
2105 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid);
2106 if (!platform_info && IS_ENABLED(CONFIG_OF))
2107 platform_info = pl022_platform_data_dt_get(dev);
2108
2109 if (!platform_info) {
2110 dev_err(dev, "probe: no platform data defined\n");
2111 return -ENODEV;
2112 }
2113
2114 if (platform_info->num_chipselect) {
2115 num_cs = platform_info->num_chipselect;
2116 } else {
2117 dev_err(dev, "probe: no chip select defined\n");
2118 return -ENODEV;
2119 }
2120
2121
2122 master = spi_alloc_master(dev, sizeof(struct pl022));
2123 if (master == NULL) {
2124 dev_err(&adev->dev, "probe - cannot alloc SPI master\n");
2125 return -ENOMEM;
2126 }
2127
2128 pl022 = spi_master_get_devdata(master);
2129 pl022->master = master;
2130 pl022->master_info = platform_info;
2131 pl022->adev = adev;
2132 pl022->vendor = id->data;
2133 pl022->chipselects = devm_kzalloc(dev, num_cs * sizeof(int),
2134 GFP_KERNEL);
2135
2136 pl022->pinctrl = devm_pinctrl_get(dev);
2137 if (IS_ERR(pl022->pinctrl)) {
2138 status = PTR_ERR(pl022->pinctrl);
2139 goto err_no_pinctrl;
2140 }
2141
2142 pl022->pins_default = pinctrl_lookup_state(pl022->pinctrl,
2143 PINCTRL_STATE_DEFAULT);
2144
2145 if (!IS_ERR(pl022->pins_default)) {
2146 status = pinctrl_select_state(pl022->pinctrl,
2147 pl022->pins_default);
2148 if (status)
2149 dev_err(dev, "could not set default pins\n");
2150 } else
2151 dev_err(dev, "could not get default pinstate\n");
2152
2153 pl022->pins_idle = pinctrl_lookup_state(pl022->pinctrl,
2154 PINCTRL_STATE_IDLE);
2155 if (IS_ERR(pl022->pins_idle))
2156 dev_dbg(dev, "could not get idle pinstate\n");
2157
2158 pl022->pins_sleep = pinctrl_lookup_state(pl022->pinctrl,
2159 PINCTRL_STATE_SLEEP);
2160 if (IS_ERR(pl022->pins_sleep))
2161 dev_dbg(dev, "could not get sleep pinstate\n");
2162
2163
2164
2165
2166
2167 master->bus_num = platform_info->bus_id;
2168 master->num_chipselect = num_cs;
2169 master->cleanup = pl022_cleanup;
2170 master->setup = pl022_setup;
2171 master->prepare_transfer_hardware = pl022_prepare_transfer_hardware;
2172 master->transfer_one_message = pl022_transfer_one_message;
2173 master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware;
2174 master->rt = platform_info->rt;
2175 master->dev.of_node = dev->of_node;
2176
2177 if (platform_info->num_chipselect && platform_info->chipselects) {
2178 for (i = 0; i < num_cs; i++)
2179 pl022->chipselects[i] = platform_info->chipselects[i];
2180 } else if (IS_ENABLED(CONFIG_OF)) {
2181 for (i = 0; i < num_cs; i++) {
2182 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
2183
2184 if (cs_gpio == -EPROBE_DEFER) {
2185 status = -EPROBE_DEFER;
2186 goto err_no_gpio;
2187 }
2188
2189 pl022->chipselects[i] = cs_gpio;
2190
2191 if (gpio_is_valid(cs_gpio)) {
2192 if (devm_gpio_request(dev, cs_gpio, "ssp-pl022"))
2193 dev_err(&adev->dev,
2194 "could not request %d gpio\n",
2195 cs_gpio);
2196 else if (gpio_direction_output(cs_gpio, 1))
2197 dev_err(&adev->dev,
2198 "could set gpio %d as output\n",
2199 cs_gpio);
2200 }
2201 }
2202 }
2203
2204
2205
2206
2207
2208 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
2209 if (pl022->vendor->extended_cr)
2210 master->mode_bits |= SPI_LSB_FIRST;
2211
2212 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num);
2213
2214 status = amba_request_regions(adev, NULL);
2215 if (status)
2216 goto err_no_ioregion;
2217
2218 pl022->phybase = adev->res.start;
2219 pl022->virtbase = devm_ioremap(dev, adev->res.start,
2220 resource_size(&adev->res));
2221 if (pl022->virtbase == NULL) {
2222 status = -ENOMEM;
2223 goto err_no_ioremap;
2224 }
2225 printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n",
2226 adev->res.start, pl022->virtbase);
2227
2228 pl022->clk = devm_clk_get(&adev->dev, NULL);
2229 if (IS_ERR(pl022->clk)) {
2230 status = PTR_ERR(pl022->clk);
2231 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n");
2232 goto err_no_clk;
2233 }
2234
2235 status = clk_prepare(pl022->clk);
2236 if (status) {
2237 dev_err(&adev->dev, "could not prepare SSP/SPI bus clock\n");
2238 goto err_clk_prep;
2239 }
2240
2241 status = clk_enable(pl022->clk);
2242 if (status) {
2243 dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n");
2244 goto err_no_clk_en;
2245 }
2246
2247
2248 tasklet_init(&pl022->pump_transfers, pump_transfers,
2249 (unsigned long)pl022);
2250
2251
2252 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
2253 SSP_CR1(pl022->virtbase));
2254 load_ssp_default_config(pl022);
2255
2256 status = devm_request_irq(dev, adev->irq[0], pl022_interrupt_handler,
2257 0, "pl022", pl022);
2258 if (status < 0) {
2259 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status);
2260 goto err_no_irq;
2261 }
2262
2263
2264 status = pl022_dma_autoprobe(pl022);
2265
2266
2267 if (status == 0)
2268 platform_info->enable_dma = 1;
2269 else if (platform_info->enable_dma) {
2270 status = pl022_dma_probe(pl022);
2271 if (status != 0)
2272 platform_info->enable_dma = 0;
2273 }
2274
2275
2276 amba_set_drvdata(adev, pl022);
2277 status = spi_register_master(master);
2278 if (status != 0) {
2279 dev_err(&adev->dev,
2280 "probe - problem registering spi master\n");
2281 goto err_spi_register;
2282 }
2283 dev_dbg(dev, "probe succeeded\n");
2284
2285
2286 if (platform_info->autosuspend_delay > 0) {
2287 dev_info(&adev->dev,
2288 "will use autosuspend for runtime pm, delay %dms\n",
2289 platform_info->autosuspend_delay);
2290 pm_runtime_set_autosuspend_delay(dev,
2291 platform_info->autosuspend_delay);
2292 pm_runtime_use_autosuspend(dev);
2293 }
2294 pm_runtime_put(dev);
2295
2296 return 0;
2297
2298 err_spi_register:
2299 if (platform_info->enable_dma)
2300 pl022_dma_remove(pl022);
2301 err_no_irq:
2302 clk_disable(pl022->clk);
2303 err_no_clk_en:
2304 clk_unprepare(pl022->clk);
2305 err_clk_prep:
2306 err_no_clk:
2307 err_no_ioremap:
2308 amba_release_regions(adev);
2309 err_no_ioregion:
2310 err_no_gpio:
2311 err_no_pinctrl:
2312 spi_master_put(master);
2313 return status;
2314}
2315
2316static int
2317pl022_remove(struct amba_device *adev)
2318{
2319 struct pl022 *pl022 = amba_get_drvdata(adev);
2320
2321 if (!pl022)
2322 return 0;
2323
2324
2325
2326
2327
2328 pm_runtime_get_noresume(&adev->dev);
2329
2330 load_ssp_default_config(pl022);
2331 if (pl022->master_info->enable_dma)
2332 pl022_dma_remove(pl022);
2333
2334 clk_disable(pl022->clk);
2335 clk_unprepare(pl022->clk);
2336 amba_release_regions(adev);
2337 tasklet_disable(&pl022->pump_transfers);
2338 spi_unregister_master(pl022->master);
2339 amba_set_drvdata(adev, NULL);
2340 return 0;
2341}
2342
2343#if defined(CONFIG_SUSPEND) || defined(CONFIG_PM_RUNTIME)
2344
2345
2346
2347
2348
2349static void pl022_suspend_resources(struct pl022 *pl022, bool runtime)
2350{
2351 int ret;
2352 struct pinctrl_state *pins_state;
2353
2354 clk_disable(pl022->clk);
2355
2356 pins_state = runtime ? pl022->pins_idle : pl022->pins_sleep;
2357
2358 if (!IS_ERR(pins_state)) {
2359 ret = pinctrl_select_state(pl022->pinctrl, pins_state);
2360 if (ret)
2361 dev_err(&pl022->adev->dev, "could not set %s pins\n",
2362 runtime ? "idle" : "sleep");
2363 }
2364}
2365
2366static void pl022_resume_resources(struct pl022 *pl022, bool runtime)
2367{
2368 int ret;
2369
2370
2371
2372 if (!IS_ERR(pl022->pins_default)) {
2373 ret = pinctrl_select_state(pl022->pinctrl, pl022->pins_default);
2374 if (ret)
2375 dev_err(&pl022->adev->dev,
2376 "could not set default pins\n");
2377 }
2378
2379 if (!runtime) {
2380
2381 if (!IS_ERR(pl022->pins_idle)) {
2382 ret = pinctrl_select_state(pl022->pinctrl,
2383 pl022->pins_idle);
2384 if (ret)
2385 dev_err(&pl022->adev->dev,
2386 "could not set idle pins\n");
2387 }
2388 }
2389
2390 clk_enable(pl022->clk);
2391}
2392#endif
2393
2394#ifdef CONFIG_SUSPEND
2395static int pl022_suspend(struct device *dev)
2396{
2397 struct pl022 *pl022 = dev_get_drvdata(dev);
2398 int ret;
2399
2400 ret = spi_master_suspend(pl022->master);
2401 if (ret) {
2402 dev_warn(dev, "cannot suspend master\n");
2403 return ret;
2404 }
2405
2406 pm_runtime_get_sync(dev);
2407 pl022_suspend_resources(pl022, false);
2408
2409 dev_dbg(dev, "suspended\n");
2410 return 0;
2411}
2412
2413static int pl022_resume(struct device *dev)
2414{
2415 struct pl022 *pl022 = dev_get_drvdata(dev);
2416 int ret;
2417
2418 pl022_resume_resources(pl022, false);
2419 pm_runtime_put(dev);
2420
2421
2422 ret = spi_master_resume(pl022->master);
2423 if (ret)
2424 dev_err(dev, "problem starting queue (%d)\n", ret);
2425 else
2426 dev_dbg(dev, "resumed\n");
2427
2428 return ret;
2429}
2430#endif
2431
2432#ifdef CONFIG_PM_RUNTIME
2433static int pl022_runtime_suspend(struct device *dev)
2434{
2435 struct pl022 *pl022 = dev_get_drvdata(dev);
2436
2437 pl022_suspend_resources(pl022, true);
2438 return 0;
2439}
2440
2441static int pl022_runtime_resume(struct device *dev)
2442{
2443 struct pl022 *pl022 = dev_get_drvdata(dev);
2444
2445 pl022_resume_resources(pl022, true);
2446 return 0;
2447}
2448#endif
2449
2450static const struct dev_pm_ops pl022_dev_pm_ops = {
2451 SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume)
2452 SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL)
2453};
2454
2455static struct vendor_data vendor_arm = {
2456 .fifodepth = 8,
2457 .max_bpw = 16,
2458 .unidir = false,
2459 .extended_cr = false,
2460 .pl023 = false,
2461 .loopback = true,
2462};
2463
2464static struct vendor_data vendor_st = {
2465 .fifodepth = 32,
2466 .max_bpw = 32,
2467 .unidir = false,
2468 .extended_cr = true,
2469 .pl023 = false,
2470 .loopback = true,
2471};
2472
2473static struct vendor_data vendor_st_pl023 = {
2474 .fifodepth = 32,
2475 .max_bpw = 32,
2476 .unidir = false,
2477 .extended_cr = true,
2478 .pl023 = true,
2479 .loopback = false,
2480};
2481
2482static struct amba_id pl022_ids[] = {
2483 {
2484
2485
2486
2487
2488 .id = 0x00041022,
2489 .mask = 0x000fffff,
2490 .data = &vendor_arm,
2491 },
2492 {
2493
2494
2495
2496
2497 .id = 0x01080022,
2498 .mask = 0xffffffff,
2499 .data = &vendor_st,
2500 },
2501 {
2502
2503
2504
2505
2506
2507
2508
2509 .id = 0x00080023,
2510 .mask = 0xffffffff,
2511 .data = &vendor_st_pl023,
2512 },
2513 { 0, 0 },
2514};
2515
2516MODULE_DEVICE_TABLE(amba, pl022_ids);
2517
2518static struct amba_driver pl022_driver = {
2519 .drv = {
2520 .name = "ssp-pl022",
2521 .pm = &pl022_dev_pm_ops,
2522 },
2523 .id_table = pl022_ids,
2524 .probe = pl022_probe,
2525 .remove = pl022_remove,
2526};
2527
2528static int __init pl022_init(void)
2529{
2530 return amba_driver_register(&pl022_driver);
2531}
2532subsys_initcall(pl022_init);
2533
2534static void __exit pl022_exit(void)
2535{
2536 amba_driver_unregister(&pl022_driver);
2537}
2538module_exit(pl022_exit);
2539
2540MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
2541MODULE_DESCRIPTION("PL022 SSP Controller Driver");
2542MODULE_LICENSE("GPL");
2543