LXR linux/drivers/staging/comedi/drivers/me

   1/*
   2 * comedi/drivers/me_daq.c
   3 * Hardware driver for Meilhaus data acquisition cards:
   4 *   ME-2000i, ME-2600i, ME-3000vm1
   5 *
   6 * Copyright (C) 2002 Michael Hillmann <hillmann@syscongroup.de>
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License as published by
  10 * the Free Software Foundation; either version 2 of the License, or
  11 * (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21 */
  22
  23/*
  24 * Driver: me_daq
  25 * Description: Meilhaus PCI data acquisition cards
  26 * Devices: (Meilhaus) ME-2600i [me-2600i]
  27 *          (Meilhaus) ME-2000i [me-2000i]
  28 * Author: Michael Hillmann <hillmann@syscongroup.de>
  29 * Status: experimental
  30 *
  31 * Configuration options: not applicable, uses PCI auto config
  32 *
  33 * Supports:
  34 *    Analog Input, Analog Output, Digital I/O
  35 */
  36
  37#include <linux/pci.h>
  38#include <linux/interrupt.h>
  39#include <linux/sched.h>
  40#include <linux/firmware.h>
  41
  42#include "../comedidev.h"
  43
  44#include "plx9052.h"
  45
  46#define ME2600_FIRMWARE         "me2600_firmware.bin"
  47
  48#define XILINX_DOWNLOAD_RESET   0x42    /* Xilinx registers */
  49
  50#define ME_CONTROL_1                    0x0000  /* - | W */
  51#define   INTERRUPT_ENABLE              (1<<15)
  52#define   COUNTER_B_IRQ                 (1<<12)
  53#define   COUNTER_A_IRQ                 (1<<11)
  54#define   CHANLIST_READY_IRQ            (1<<10)
  55#define   EXT_IRQ                       (1<<9)
  56#define   ADFIFO_HALFFULL_IRQ           (1<<8)
  57#define   SCAN_COUNT_ENABLE             (1<<5)
  58#define   SIMULTANEOUS_ENABLE           (1<<4)
  59#define   TRIGGER_FALLING_EDGE          (1<<3)
  60#define   CONTINUOUS_MODE               (1<<2)
  61#define   DISABLE_ADC                   (0<<0)
  62#define   SOFTWARE_TRIGGERED_ADC        (1<<0)
  63#define   SCAN_TRIGGERED_ADC            (2<<0)
  64#define   EXT_TRIGGERED_ADC             (3<<0)
  65#define ME_ADC_START                    0x0000  /* R | - */
  66#define ME_CONTROL_2                    0x0002  /* - | W */
  67#define   ENABLE_ADFIFO                 (1<<10)
  68#define   ENABLE_CHANLIST               (1<<9)
  69#define   ENABLE_PORT_B                 (1<<7)
  70#define   ENABLE_PORT_A                 (1<<6)
  71#define   ENABLE_COUNTER_B              (1<<4)
  72#define   ENABLE_COUNTER_A              (1<<3)
  73#define   ENABLE_DAC                    (1<<1)
  74#define   BUFFERED_DAC                  (1<<0)
  75#define ME_DAC_UPDATE                   0x0002  /* R | - */
  76#define ME_STATUS                       0x0004  /* R | - */
  77#define   COUNTER_B_IRQ_PENDING         (1<<12)
  78#define   COUNTER_A_IRQ_PENDING         (1<<11)
  79#define   CHANLIST_READY_IRQ_PENDING    (1<<10)
  80#define   EXT_IRQ_PENDING               (1<<9)
  81#define   ADFIFO_HALFFULL_IRQ_PENDING   (1<<8)
  82#define   ADFIFO_FULL                   (1<<4)
  83#define   ADFIFO_HALFFULL               (1<<3)
  84#define   ADFIFO_EMPTY                  (1<<2)
  85#define   CHANLIST_FULL                 (1<<1)
  86#define   FST_ACTIVE                    (1<<0)
  87#define ME_RESET_INTERRUPT              0x0004  /* - | W */
  88#define ME_DIO_PORT_A                   0x0006  /* R | W */
  89#define ME_DIO_PORT_B                   0x0008  /* R | W */
  90#define ME_TIMER_DATA_0                 0x000A  /* - | W */
  91#define ME_TIMER_DATA_1                 0x000C  /* - | W */
  92#define ME_TIMER_DATA_2                 0x000E  /* - | W */
  93#define ME_CHANNEL_LIST                 0x0010  /* - | W */
  94#define   ADC_UNIPOLAR                  (1<<6)
  95#define   ADC_GAIN_0                    (0<<4)
  96#define   ADC_GAIN_1                    (1<<4)
  97#define   ADC_GAIN_2                    (2<<4)
  98#define   ADC_GAIN_3                    (3<<4)
  99#define ME_READ_AD_FIFO                 0x0010  /* R | - */
 100#define ME_DAC_CONTROL                  0x0012  /* - | W */
 101#define   DAC_UNIPOLAR_D                (0<<4)
 102#define   DAC_BIPOLAR_D                 (1<<4)
 103#define   DAC_UNIPOLAR_C                (0<<5)
 104#define   DAC_BIPOLAR_C                 (1<<5)
 105#define   DAC_UNIPOLAR_B                (0<<6)
 106#define   DAC_BIPOLAR_B                 (1<<6)
 107#define   DAC_UNIPOLAR_A                (0<<7)
 108#define   DAC_BIPOLAR_A                 (1<<7)
 109#define   DAC_GAIN_0_D                  (0<<8)
 110#define   DAC_GAIN_1_D                  (1<<8)
 111#define   DAC_GAIN_0_C                  (0<<9)
 112#define   DAC_GAIN_1_C                  (1<<9)
 113#define   DAC_GAIN_0_B                  (0<<10)
 114#define   DAC_GAIN_1_B                  (1<<10)
 115#define   DAC_GAIN_0_A                  (0<<11)
 116#define   DAC_GAIN_1_A                  (1<<11)
 117#define ME_DAC_CONTROL_UPDATE           0x0012  /* R | - */
 118#define ME_DAC_DATA_A                   0x0014  /* - | W */
 119#define ME_DAC_DATA_B                   0x0016  /* - | W */
 120#define ME_DAC_DATA_C                   0x0018  /* - | W */
 121#define ME_DAC_DATA_D                   0x001A  /* - | W */
 122#define ME_COUNTER_ENDDATA_A            0x001C  /* - | W */
 123#define ME_COUNTER_ENDDATA_B            0x001E  /* - | W */
 124#define ME_COUNTER_STARTDATA_A          0x0020  /* - | W */
 125#define ME_COUNTER_VALUE_A              0x0020  /* R | - */
 126#define ME_COUNTER_STARTDATA_B          0x0022  /* - | W */
 127#define ME_COUNTER_VALUE_B              0x0022  /* R | - */
 128
 129static const struct comedi_lrange me_ai_range = {
 130        8, {
 131                BIP_RANGE(10),
 132                BIP_RANGE(5),
 133                BIP_RANGE(2.5),
 134                BIP_RANGE(1.25),
 135                UNI_RANGE(10),
 136                UNI_RANGE(5),
 137                UNI_RANGE(2.5),
 138                UNI_RANGE(1.25)
 139        }
 140};
 141
 142static const struct comedi_lrange me_ao_range = {
 143        3, {
 144                BIP_RANGE(10),
 145                BIP_RANGE(5),
 146                UNI_RANGE(10)
 147        }
 148};
 149
 150enum me_boardid {
 151        BOARD_ME2600,
 152        BOARD_ME2000,
 153};
 154
 155struct me_board {
 156        const char *name;
 157        int needs_firmware;
 158        int has_ao;
 159};
 160
 161static const struct me_board me_boards[] = {
 162        [BOARD_ME2600] = {
 163                .name           = "me-2600i",
 164                .needs_firmware = 1,
 165                .has_ao         = 1,
 166        },
 167        [BOARD_ME2000] = {
 168                .name           = "me-2000i",
 169        },
 170};
 171
 172struct me_private_data {
 173        void __iomem *plx_regbase;      /* PLX configuration base address */
 174        void __iomem *me_regbase;       /* Base address of the Meilhaus card */
 175
 176        unsigned short control_1;       /* Mirror of CONTROL_1 register */
 177        unsigned short control_2;       /* Mirror of CONTROL_2 register */
 178        unsigned short dac_control;     /* Mirror of the DAC_CONTROL register */
 179        int ao_readback[4];     /* Mirror of analog output data */
 180};
 181
 182static inline void sleep(unsigned sec)
 183{
 184        current->state = TASK_INTERRUPTIBLE;
 185        schedule_timeout(sec * HZ);
 186}
 187
 188static int me_dio_insn_config(struct comedi_device *dev,
 189                              struct comedi_subdevice *s,
 190                              struct comedi_insn *insn,
 191                              unsigned int *data)
 192{
 193        struct me_private_data *dev_private = dev->private;
 194        unsigned int mask = 1 << CR_CHAN(insn->chanspec);
 195        unsigned int bits;
 196        unsigned int port;
 197
 198        if (mask & 0x0000ffff) {
 199                bits = 0x0000ffff;
 200                port = ENABLE_PORT_A;
 201        } else {
 202                bits = 0xffff0000;
 203                port = ENABLE_PORT_B;
 204        }
 205
 206        switch (data[0]) {
 207        case INSN_CONFIG_DIO_INPUT:
 208                s->io_bits &= ~bits;
 209                dev_private->control_2 &= ~port;
 210                break;
 211        case INSN_CONFIG_DIO_OUTPUT:
 212                s->io_bits |= bits;
 213                dev_private->control_2 |= port;
 214                break;
 215        case INSN_CONFIG_DIO_QUERY:
 216                data[1] = (s->io_bits & bits) ? COMEDI_OUTPUT : COMEDI_INPUT;
 217                return insn->n;
 218                break;
 219        default:
 220                return -EINVAL;
 221        }
 222
 223        /* Update the port configuration */
 224        writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
 225
 226        return insn->n;
 227}
 228
 229static int me_dio_insn_bits(struct comedi_device *dev,
 230                            struct comedi_subdevice *s,
 231                            struct comedi_insn *insn,
 232                            unsigned int *data)
 233{
 234        struct me_private_data *dev_private = dev->private;
 235        void __iomem *mmio_porta = dev_private->me_regbase + ME_DIO_PORT_A;
 236        void __iomem *mmio_portb = dev_private->me_regbase + ME_DIO_PORT_B;
 237        unsigned int mask = data[0];
 238        unsigned int bits = data[1];
 239        unsigned int val;
 240
 241        mask &= s->io_bits;     /* only update the COMEDI_OUTPUT channels */
 242        if (mask) {
 243                s->state &= ~mask;
 244                s->state |= (bits & mask);
 245
 246                if (mask & 0x0000ffff)
 247                        writew((s->state & 0xffff), mmio_porta);
 248                if (mask & 0xffff0000)
 249                        writew(((s->state >> 16) & 0xffff), mmio_portb);
 250        }
 251
 252        if (s->io_bits & 0x0000ffff)
 253                val = s->state & 0xffff;
 254        else
 255                val = readw(mmio_porta);
 256
 257        if (s->io_bits & 0xffff0000)
 258                val |= (s->state & 0xffff0000);
 259        else
 260                val |= (readw(mmio_portb) << 16);
 261
 262        data[1] = val;
 263
 264        return insn->n;
 265}
 266
 267static int me_ai_insn_read(struct comedi_device *dev,
 268                           struct comedi_subdevice *s,
 269                           struct comedi_insn *insn,
 270                           unsigned int *data)
 271{
 272        struct me_private_data *dev_private = dev->private;
 273        unsigned int chan = CR_CHAN(insn->chanspec);
 274        unsigned int rang = CR_RANGE(insn->chanspec);
 275        unsigned int aref = CR_AREF(insn->chanspec);
 276        unsigned short val;
 277        int i;
 278
 279        /* stop any running conversion */
 280        dev_private->control_1 &= 0xFFFC;
 281        writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
 282
 283        /* clear chanlist and ad fifo */
 284        dev_private->control_2 &= ~(ENABLE_ADFIFO | ENABLE_CHANLIST);
 285        writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
 286
 287        /* reset any pending interrupt */
 288        writew(0x00, dev_private->me_regbase + ME_RESET_INTERRUPT);
 289
 290        /* enable the chanlist and ADC fifo */
 291        dev_private->control_2 |= (ENABLE_ADFIFO | ENABLE_CHANLIST);
 292        writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
 293
 294        /* write to channel list fifo */
 295        val = chan & 0x0f;                      /* b3:b0 channel */
 296        val |= (rang & 0x03) << 4;              /* b5:b4 gain */
 297        val |= (rang & 0x04) << 4;              /* b6 polarity */
 298        val |= ((aref & AREF_DIFF) ? 0x80 : 0); /* b7 differential */
 299        writew(val & 0xff, dev_private->me_regbase + ME_CHANNEL_LIST);
 300
 301        /* set ADC mode to software trigger */
 302        dev_private->control_1 |= SOFTWARE_TRIGGERED_ADC;
 303        writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
 304
 305        /* start conversion by reading from ADC_START */
 306        readw(dev_private->me_regbase + ME_ADC_START);
 307
 308        /* wait for ADC fifo not empty flag */
 309        for (i = 100000; i > 0; i--)
 310                if (!(readw(dev_private->me_regbase + ME_STATUS) & 0x0004))
 311                        break;
 312
 313        /* get value from ADC fifo */
 314        if (i) {
 315                val = readw(dev_private->me_regbase + ME_READ_AD_FIFO);
 316                val = (val ^ 0x800) & 0x0fff;
 317                data[0] = val;
 318        } else {
 319                dev_err(dev->class_dev, "Cannot get single value\n");
 320                return -EIO;
 321        }
 322
 323        /* stop any running conversion */
 324        dev_private->control_1 &= 0xFFFC;
 325        writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
 326
 327        return 1;
 328}
 329
 330static int me_ao_insn_write(struct comedi_device *dev,
 331                            struct comedi_subdevice *s,
 332                            struct comedi_insn *insn,
 333                            unsigned int *data)
 334{
 335        struct me_private_data *dev_private = dev->private;
 336        unsigned int chan = CR_CHAN(insn->chanspec);
 337        unsigned int rang = CR_RANGE(insn->chanspec);
 338        int i;
 339
 340        /* Enable all DAC */
 341        dev_private->control_2 |= ENABLE_DAC;
 342        writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
 343
 344        /* and set DAC to "buffered" mode */
 345        dev_private->control_2 |= BUFFERED_DAC;
 346        writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
 347
 348        /* Set dac-control register */
 349        for (i = 0; i < insn->n; i++) {
 350                /* clear bits for this channel */
 351                dev_private->dac_control &= ~(0x0880 >> chan);
 352                if (rang == 0)
 353                        dev_private->dac_control |=
 354                            ((DAC_BIPOLAR_A | DAC_GAIN_1_A) >> chan);
 355                else if (rang == 1)
 356                        dev_private->dac_control |=
 357                            ((DAC_BIPOLAR_A | DAC_GAIN_0_A) >> chan);
 358        }
 359        writew(dev_private->dac_control,
 360               dev_private->me_regbase + ME_DAC_CONTROL);
 361
 362        /* Update dac-control register */
 363        readw(dev_private->me_regbase + ME_DAC_CONTROL_UPDATE);
 364
 365        /* Set data register */
 366        for (i = 0; i < insn->n; i++) {
 367                writew((data[0] & s->maxdata),
 368                       dev_private->me_regbase + ME_DAC_DATA_A + (chan << 1));
 369                dev_private->ao_readback[chan] = (data[0] & s->maxdata);
 370        }
 371
 372        /* Update dac with data registers */
 373        readw(dev_private->me_regbase + ME_DAC_UPDATE);
 374
 375        return insn->n;
 376}
 377
 378static int me_ao_insn_read(struct comedi_device *dev,
 379                           struct comedi_subdevice *s,
 380                           struct comedi_insn *insn,
 381                           unsigned int *data)
 382{
 383        struct me_private_data *dev_private = dev->private;
 384        unsigned int chan = CR_CHAN(insn->chanspec);
 385        int i;
 386
 387        for (i = 0; i < insn->n; i++)
 388                data[i] = dev_private->ao_readback[chan];
 389
 390        return insn->n;
 391}
 392
 393static int me2600_xilinx_download(struct comedi_device *dev,
 394                                  const u8 *data, size_t size)
 395{
 396        struct me_private_data *dev_private = dev->private;
 397        unsigned int value;
 398        unsigned int file_length;
 399        unsigned int i;
 400
 401        /* disable irq's on PLX */
 402        writel(0x00, dev_private->plx_regbase + PLX9052_INTCSR);
 403
 404        /* First, make a dummy read to reset xilinx */
 405        value = readw(dev_private->me_regbase + XILINX_DOWNLOAD_RESET);
 406
 407        /* Wait until reset is over */
 408        sleep(1);
 409
 410        /* Write a dummy value to Xilinx */
 411        writeb(0x00, dev_private->me_regbase + 0x0);
 412        sleep(1);
 413
 414        /*
 415         * Format of the firmware
 416         * Build longs from the byte-wise coded header
 417         * Byte 1-3:   length of the array
 418         * Byte 4-7:   version
 419         * Byte 8-11:  date
 420         * Byte 12-15: reserved
 421         */
 422        if (size < 16)
 423                return -EINVAL;
 424
 425        file_length = (((unsigned int)data[0] & 0xff) << 24) +
 426            (((unsigned int)data[1] & 0xff) << 16) +
 427            (((unsigned int)data[2] & 0xff) << 8) +
 428            ((unsigned int)data[3] & 0xff);
 429
 430        /*
 431         * Loop for writing firmware byte by byte to xilinx
 432         * Firmware data start at offset 16
 433         */
 434        for (i = 0; i < file_length; i++)
 435                writeb((data[16 + i] & 0xff),
 436                       dev_private->me_regbase + 0x0);
 437
 438        /* Write 5 dummy values to xilinx */
 439        for (i = 0; i < 5; i++)
 440                writeb(0x00, dev_private->me_regbase + 0x0);
 441
 442        /* Test if there was an error during download -> INTB was thrown */
 443        value = readl(dev_private->plx_regbase + PLX9052_INTCSR);
 444        if (value & PLX9052_INTCSR_LI2STAT) {
 445                /* Disable interrupt */
 446                writel(0x00, dev_private->plx_regbase + PLX9052_INTCSR);
 447                dev_err(dev->class_dev, "Xilinx download failed\n");
 448                return -EIO;
 449        }
 450
 451        /* Wait until the Xilinx is ready for real work */
 452        sleep(1);
 453
 454        /* Enable PLX-Interrupts */
 455        writel(PLX9052_INTCSR_LI1ENAB |
 456               PLX9052_INTCSR_LI1POL |
 457               PLX9052_INTCSR_PCIENAB,
 458               dev_private->plx_regbase + PLX9052_INTCSR);
 459
 460        return 0;
 461}
 462
 463static int me2600_upload_firmware(struct comedi_device *dev)
 464{
 465        struct pci_dev *pcidev = comedi_to_pci_dev(dev);
 466        const struct firmware *fw;
 467        int ret;
 468
 469        ret = request_firmware(&fw, ME2600_FIRMWARE, &pcidev->dev);
 470        if (ret)
 471                return ret;
 472
 473        ret = me2600_xilinx_download(dev, fw->data, fw->size);
 474        release_firmware(fw);
 475
 476        return ret;
 477}
 478
 479static int me_reset(struct comedi_device *dev)
 480{
 481        struct me_private_data *dev_private = dev->private;
 482
 483        /* Reset board */
 484        writew(0x00, dev_private->me_regbase + ME_CONTROL_1);
 485        writew(0x00, dev_private->me_regbase + ME_CONTROL_2);
 486        writew(0x00, dev_private->me_regbase + ME_RESET_INTERRUPT);
 487        writew(0x00, dev_private->me_regbase + ME_DAC_CONTROL);
 488
 489        /* Save values in the board context */
 490        dev_private->dac_control = 0;
 491        dev_private->control_1 = 0;
 492        dev_private->control_2 = 0;
 493
 494        return 0;
 495}
 496
 497static int me_auto_attach(struct comedi_device *dev,
 498                          unsigned long context)
 499{
 500        struct pci_dev *pcidev = comedi_to_pci_dev(dev);
 501        const struct me_board *board = NULL;
 502        struct me_private_data *dev_private;
 503        struct comedi_subdevice *s;
 504        int ret;
 505
 506        if (context < ARRAY_SIZE(me_boards))
 507                board = &me_boards[context];
 508        if (!board)
 509                return -ENODEV;
 510        dev->board_ptr = board;
 511        dev->board_name = board->name;
 512
 513        dev_private = kzalloc(sizeof(*dev_private), GFP_KERNEL);
 514        if (!dev_private)
 515                return -ENOMEM;
 516        dev->private = dev_private;
 517
 518        ret = comedi_pci_enable(dev);
 519        if (ret)
 520                return ret;
 521
 522        dev_private->plx_regbase = pci_ioremap_bar(pcidev, 0);
 523        if (!dev_private->plx_regbase)
 524                return -ENOMEM;
 525
 526        dev_private->me_regbase = pci_ioremap_bar(pcidev, 2);
 527        if (!dev_private->me_regbase)
 528                return -ENOMEM;
 529
 530        /* Download firmware and reset card */
 531        if (board->needs_firmware) {
 532                ret = me2600_upload_firmware(dev);
 533                if (ret < 0)
 534                        return ret;
 535        }
 536        me_reset(dev);
 537
 538        ret = comedi_alloc_subdevices(dev, 3);
 539        if (ret)
 540                return ret;
 541
 542        s = &dev->subdevices[0];
 543        s->type         = COMEDI_SUBD_AI;
 544        s->subdev_flags = SDF_READABLE | SDF_COMMON;
 545        s->n_chan       = 16;
 546        s->maxdata      = 0x0fff;
 547        s->len_chanlist = 16;
 548        s->range_table  = &me_ai_range;
 549        s->insn_read    = me_ai_insn_read;
 550
 551        s = &dev->subdevices[1];
 552        if (board->has_ao) {
 553                s->type         = COMEDI_SUBD_AO;
 554                s->subdev_flags = SDF_WRITEABLE | SDF_COMMON;
 555                s->n_chan       = 4;
 556                s->maxdata      = 0x0fff;
 557                s->len_chanlist = 4;
 558                s->range_table  = &me_ao_range;
 559                s->insn_read    = me_ao_insn_read;
 560                s->insn_write   = me_ao_insn_write;
 561        } else {
 562                s->type = COMEDI_SUBD_UNUSED;
 563        }
 564
 565        s = &dev->subdevices[2];
 566        s->type         = COMEDI_SUBD_DIO;
 567        s->subdev_flags = SDF_READABLE | SDF_WRITEABLE;
 568        s->n_chan       = 32;
 569        s->maxdata      = 1;
 570        s->len_chanlist = 32;
 571        s->range_table  = &range_digital;
 572        s->insn_bits    = me_dio_insn_bits;
 573        s->insn_config  = me_dio_insn_config;
 574        s->io_bits      = 0;
 575
 576        dev_info(dev->class_dev, "%s: %s attached\n",
 577                dev->driver->driver_name, dev->board_name);
 578
 579        return 0;
 580}
 581
 582static void me_detach(struct comedi_device *dev)
 583{
 584        struct me_private_data *dev_private = dev->private;
 585
 586        if (dev_private) {
 587                if (dev_private->me_regbase) {
 588                        me_reset(dev);
 589                        iounmap(dev_private->me_regbase);
 590                }
 591                if (dev_private->plx_regbase)
 592                        iounmap(dev_private->plx_regbase);
 593        }
 594        comedi_pci_disable(dev);
 595}
 596
 597static struct comedi_driver me_daq_driver = {
 598        .driver_name    = "me_daq",
 599        .module         = THIS_MODULE,
 600        .auto_attach    = me_auto_attach,
 601        .detach         = me_detach,
 602};
 603
 604static int me_daq_pci_probe(struct pci_dev *dev,
 605                            const struct pci_device_id *id)
 606{
 607        return comedi_pci_auto_config(dev, &me_daq_driver, id->driver_data);
 608}
 609
 610static DEFINE_PCI_DEVICE_TABLE(me_daq_pci_table) = {
 611        { PCI_VDEVICE(MEILHAUS, 0x2600), BOARD_ME2600 },
 612        { PCI_VDEVICE(MEILHAUS, 0x2000), BOARD_ME2000 },
 613        { 0 }
 614};
 615MODULE_DEVICE_TABLE(pci, me_daq_pci_table);
 616
 617static struct pci_driver me_daq_pci_driver = {
 618        .name           = "me_daq",
 619        .id_table       = me_daq_pci_table,
 620        .probe          = me_daq_pci_probe,
 621        .remove         = comedi_pci_auto_unconfig,
 622};
 623module_comedi_pci_driver(me_daq_driver, me_daq_pci_driver);
 624
 625MODULE_AUTHOR("Comedi http://www.comedi.org");
 626MODULE_DESCRIPTION("Comedi low-level driver");
 627MODULE_LICENSE("GPL");
 628MODULE_FIRMWARE(ME2600_FIRMWARE);
 629