linux/drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c
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   1/******************************************************************************
   2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
   3 *
   4 * Based on the r8180 driver, which is:
   5 * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al.
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms of version 2 of the GNU General Public License as
   8 * published by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope that it will be useful, but WITHOUT
  11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13 * more details.
  14 *
  15 * You should have received a copy of the GNU General Public License along with
  16 * this program; if not, write to the Free Software Foundation, Inc.,
  17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  18 *
  19 * The full GNU General Public License is included in this distribution in the
  20 * file called LICENSE.
  21 *
  22 * Contact Information:
  23 * wlanfae <wlanfae@realtek.com>
  24******************************************************************************/
  25#include "rtl_core.h"
  26#include "r8192E_phy.h"
  27#include "r8192E_phyreg.h"
  28#include "r8190P_rtl8256.h"
  29#include "r8192E_cmdpkt.h"
  30#include "rtl_dm.h"
  31#include "rtl_wx.h"
  32
  33extern int WDCAPARA_ADD[];
  34
  35void rtl8192e_start_beacon(struct net_device *dev)
  36{
  37        struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
  38        struct rtllib_network *net = &priv->rtllib->current_network;
  39        u16 BcnTimeCfg = 0;
  40        u16 BcnCW = 6;
  41        u16 BcnIFS = 0xf;
  42
  43        DMESG("Enabling beacon TX");
  44        rtl8192_irq_disable(dev);
  45
  46        write_nic_word(dev, ATIMWND, 2);
  47
  48        write_nic_word(dev, BCN_INTERVAL, net->beacon_interval);
  49        write_nic_word(dev, BCN_DRV_EARLY_INT, 10);
  50        write_nic_word(dev, BCN_DMATIME, 256);
  51
  52        write_nic_byte(dev, BCN_ERR_THRESH, 100);
  53
  54        BcnTimeCfg |= BcnCW<<BCN_TCFG_CW_SHIFT;
  55        BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
  56        write_nic_word(dev, BCN_TCFG, BcnTimeCfg);
  57        rtl8192_irq_enable(dev);
  58}
  59
  60static void rtl8192e_update_msr(struct net_device *dev)
  61{
  62        struct r8192_priv *priv = rtllib_priv(dev);
  63        u8 msr;
  64        enum led_ctl_mode LedAction = LED_CTL_NO_LINK;
  65        msr  = read_nic_byte(dev, MSR);
  66        msr &= ~MSR_LINK_MASK;
  67
  68        switch (priv->rtllib->iw_mode) {
  69        case IW_MODE_INFRA:
  70                if (priv->rtllib->state == RTLLIB_LINKED)
  71                        msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
  72                else
  73                        msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
  74                LedAction = LED_CTL_LINK;
  75                break;
  76        case IW_MODE_ADHOC:
  77                if (priv->rtllib->state == RTLLIB_LINKED)
  78                        msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
  79                else
  80                        msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
  81                break;
  82        case IW_MODE_MASTER:
  83                if (priv->rtllib->state == RTLLIB_LINKED)
  84                        msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
  85                else
  86                        msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
  87                break;
  88        default:
  89                break;
  90        }
  91
  92        write_nic_byte(dev, MSR, msr);
  93        if (priv->rtllib->LedControlHandler)
  94                priv->rtllib->LedControlHandler(dev, LedAction);
  95}
  96
  97void rtl8192e_SetHwReg(struct net_device *dev, u8 variable, u8 *val)
  98{
  99        struct r8192_priv *priv = rtllib_priv(dev);
 100
 101        switch (variable) {
 102        case HW_VAR_BSSID:
 103                write_nic_dword(dev, BSSIDR, ((u32 *)(val))[0]);
 104                write_nic_word(dev, BSSIDR+2, ((u16 *)(val+2))[0]);
 105                break;
 106
 107        case HW_VAR_MEDIA_STATUS:
 108        {
 109                enum rt_op_mode OpMode = *((enum rt_op_mode *)(val));
 110                enum led_ctl_mode LedAction = LED_CTL_NO_LINK;
 111                u8              btMsr = read_nic_byte(dev, MSR);
 112
 113                btMsr &= 0xfc;
 114
 115                switch (OpMode) {
 116                case RT_OP_MODE_INFRASTRUCTURE:
 117                        btMsr |= MSR_INFRA;
 118                        LedAction = LED_CTL_LINK;
 119                        break;
 120
 121                case RT_OP_MODE_IBSS:
 122                        btMsr |= MSR_ADHOC;
 123                        break;
 124
 125                case RT_OP_MODE_AP:
 126                        btMsr |= MSR_AP;
 127                        LedAction = LED_CTL_LINK;
 128                        break;
 129
 130                default:
 131                        btMsr |= MSR_NOLINK;
 132                        break;
 133                }
 134
 135                write_nic_byte(dev, MSR, btMsr);
 136
 137        }
 138        break;
 139
 140        case HW_VAR_CECHK_BSSID:
 141        {
 142                u32     RegRCR, Type;
 143
 144                Type = ((u8 *)(val))[0];
 145                RegRCR = read_nic_dword(dev, RCR);
 146                priv->ReceiveConfig = RegRCR;
 147
 148                if (Type == true)
 149                        RegRCR |= (RCR_CBSSID);
 150                else if (Type == false)
 151                        RegRCR &= (~RCR_CBSSID);
 152
 153                write_nic_dword(dev, RCR, RegRCR);
 154                priv->ReceiveConfig = RegRCR;
 155
 156        }
 157        break;
 158
 159        case HW_VAR_SLOT_TIME:
 160
 161                priv->slot_time = val[0];
 162                write_nic_byte(dev, SLOT_TIME, val[0]);
 163
 164                break;
 165
 166        case HW_VAR_ACK_PREAMBLE:
 167        {
 168                u32 regTmp;
 169                priv->short_preamble = (bool)(*(u8 *)val);
 170                regTmp = priv->basic_rate;
 171                if (priv->short_preamble)
 172                        regTmp |= BRSR_AckShortPmb;
 173                write_nic_dword(dev, RRSR, regTmp);
 174                break;
 175        }
 176
 177        case HW_VAR_CPU_RST:
 178                write_nic_dword(dev, CPU_GEN, ((u32 *)(val))[0]);
 179                break;
 180
 181        case HW_VAR_AC_PARAM:
 182        {
 183                u8      pAcParam = *((u8 *)val);
 184                u32     eACI = pAcParam;
 185                u8              u1bAIFS;
 186                u32             u4bAcParam;
 187                u8 mode = priv->rtllib->mode;
 188                struct rtllib_qos_parameters *qos_parameters =
 189                         &priv->rtllib->current_network.qos_data.parameters;
 190
 191                u1bAIFS = qos_parameters->aifs[pAcParam] *
 192                          ((mode&(IEEE_G|IEEE_N_24G)) ? 9 : 20) + aSifsTime;
 193
 194                dm_init_edca_turbo(dev);
 195
 196                u4bAcParam = ((((u32)(qos_parameters->tx_op_limit[pAcParam])) <<
 197                             AC_PARAM_TXOP_LIMIT_OFFSET) |
 198                             (((u32)(qos_parameters->cw_max[pAcParam])) <<
 199                             AC_PARAM_ECW_MAX_OFFSET) |
 200                             (((u32)(qos_parameters->cw_min[pAcParam])) <<
 201                             AC_PARAM_ECW_MIN_OFFSET) |
 202                             (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
 203
 204                RT_TRACE(COMP_DBG, "%s():HW_VAR_AC_PARAM eACI:%x:%x\n",
 205                         __func__, eACI, u4bAcParam);
 206                switch (eACI) {
 207                case AC1_BK:
 208                        write_nic_dword(dev, EDCAPARA_BK, u4bAcParam);
 209                        break;
 210
 211                case AC0_BE:
 212                        write_nic_dword(dev, EDCAPARA_BE, u4bAcParam);
 213                        break;
 214
 215                case AC2_VI:
 216                        write_nic_dword(dev, EDCAPARA_VI, u4bAcParam);
 217                        break;
 218
 219                case AC3_VO:
 220                        write_nic_dword(dev, EDCAPARA_VO, u4bAcParam);
 221                        break;
 222
 223                default:
 224                        printk(KERN_INFO "SetHwReg8185(): invalid ACI: %d !\n",
 225                               eACI);
 226                        break;
 227                }
 228                priv->rtllib->SetHwRegHandler(dev, HW_VAR_ACM_CTRL,
 229                                              (u8 *)(&pAcParam));
 230                break;
 231        }
 232
 233        case HW_VAR_ACM_CTRL:
 234        {
 235                struct rtllib_qos_parameters *qos_parameters =
 236                         &priv->rtllib->current_network.qos_data.parameters;
 237                u8 pAcParam = *((u8 *)val);
 238                u32 eACI = pAcParam;
 239                union aci_aifsn *pAciAifsn = (union aci_aifsn *) &
 240                                              (qos_parameters->aifs[0]);
 241                u8 acm = pAciAifsn->f.acm;
 242                u8 AcmCtrl = read_nic_byte(dev, AcmHwCtrl);
 243
 244                RT_TRACE(COMP_DBG, "===========>%s():HW_VAR_ACM_CTRL:%x\n",
 245                         __func__, eACI);
 246                AcmCtrl = AcmCtrl | ((priv->AcmMethod == 2) ? 0x0 : 0x1);
 247
 248                if (acm) {
 249                        switch (eACI) {
 250                        case AC0_BE:
 251                                AcmCtrl |= AcmHw_BeqEn;
 252                                break;
 253
 254                        case AC2_VI:
 255                                AcmCtrl |= AcmHw_ViqEn;
 256                                break;
 257
 258                        case AC3_VO:
 259                                AcmCtrl |= AcmHw_VoqEn;
 260                                break;
 261
 262                        default:
 263                                RT_TRACE(COMP_QOS, "SetHwReg8185(): [HW_VAR_"
 264                                         "ACM_CTRL] acm set failed: eACI is "
 265                                         "%d\n", eACI);
 266                                break;
 267                        }
 268                } else {
 269                        switch (eACI) {
 270                        case AC0_BE:
 271                                AcmCtrl &= (~AcmHw_BeqEn);
 272                                break;
 273
 274                        case AC2_VI:
 275                                AcmCtrl &= (~AcmHw_ViqEn);
 276                                break;
 277
 278                        case AC3_VO:
 279                                AcmCtrl &= (~AcmHw_BeqEn);
 280                                break;
 281
 282                        default:
 283                                break;
 284                        }
 285                }
 286
 287                RT_TRACE(COMP_QOS, "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write"
 288                         " 0x%X\n", AcmCtrl);
 289                write_nic_byte(dev, AcmHwCtrl, AcmCtrl);
 290                break;
 291        }
 292
 293        case HW_VAR_SIFS:
 294                write_nic_byte(dev, SIFS, val[0]);
 295                write_nic_byte(dev, SIFS+1, val[0]);
 296                break;
 297
 298        case HW_VAR_RF_TIMING:
 299        {
 300                u8 Rf_Timing = *((u8 *)val);
 301                write_nic_byte(dev, rFPGA0_RFTiming1, Rf_Timing);
 302                break;
 303        }
 304
 305        default:
 306                break;
 307        }
 308
 309}
 310
 311static void rtl8192_read_eeprom_info(struct net_device *dev)
 312{
 313        struct r8192_priv *priv = rtllib_priv(dev);
 314
 315        u8 tempval;
 316        u8 ICVer8192, ICVer8256;
 317        u16 i, usValue, IC_Version;
 318        u16 EEPROMId;
 319        u8 bMac_Tmp_Addr[6] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x01};
 320        RT_TRACE(COMP_INIT, "====> rtl8192_read_eeprom_info\n");
 321
 322        EEPROMId = eprom_read(dev, 0);
 323        if (EEPROMId != RTL8190_EEPROM_ID) {
 324                RT_TRACE(COMP_ERR, "EEPROM ID is invalid:%x, %x\n",
 325                         EEPROMId, RTL8190_EEPROM_ID);
 326                priv->AutoloadFailFlag = true;
 327        } else {
 328                priv->AutoloadFailFlag = false;
 329        }
 330
 331        if (!priv->AutoloadFailFlag) {
 332                priv->eeprom_vid = eprom_read(dev, (EEPROM_VID >> 1));
 333                priv->eeprom_did = eprom_read(dev, (EEPROM_DID >> 1));
 334
 335                usValue = eprom_read(dev, (u16)(EEPROM_Customer_ID>>1)) >> 8;
 336                priv->eeprom_CustomerID = (u8)(usValue & 0xff);
 337                usValue = eprom_read(dev, (EEPROM_ICVersion_ChannelPlan>>1));
 338                priv->eeprom_ChannelPlan = usValue&0xff;
 339                IC_Version = ((usValue&0xff00)>>8);
 340
 341                ICVer8192 = (IC_Version&0xf);
 342                ICVer8256 = ((IC_Version&0xf0)>>4);
 343                RT_TRACE(COMP_INIT, "\nICVer8192 = 0x%x\n", ICVer8192);
 344                RT_TRACE(COMP_INIT, "\nICVer8256 = 0x%x\n", ICVer8256);
 345                if (ICVer8192 == 0x2) {
 346                        if (ICVer8256 == 0x5)
 347                                priv->card_8192_version = VERSION_8190_BE;
 348                }
 349                switch (priv->card_8192_version) {
 350                case VERSION_8190_BD:
 351                case VERSION_8190_BE:
 352                        break;
 353                default:
 354                        priv->card_8192_version = VERSION_8190_BD;
 355                        break;
 356                }
 357                RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n",
 358                          priv->card_8192_version);
 359        } else {
 360                priv->card_8192_version = VERSION_8190_BD;
 361                priv->eeprom_vid = 0;
 362                priv->eeprom_did = 0;
 363                priv->eeprom_CustomerID = 0;
 364                priv->eeprom_ChannelPlan = 0;
 365                RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n", 0xff);
 366        }
 367
 368        RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
 369        RT_TRACE(COMP_INIT, "EEPROM DID = 0x%4x\n", priv->eeprom_did);
 370        RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n",
 371                 priv->eeprom_CustomerID);
 372
 373        if (!priv->AutoloadFailFlag) {
 374                for (i = 0; i < 6; i += 2) {
 375                        usValue = eprom_read(dev,
 376                                 (u16)((EEPROM_NODE_ADDRESS_BYTE_0 + i) >> 1));
 377                        *(u16 *)(&dev->dev_addr[i]) = usValue;
 378                }
 379        } else {
 380                memcpy(dev->dev_addr, bMac_Tmp_Addr, 6);
 381        }
 382
 383        RT_TRACE(COMP_INIT, "Permanent Address = %pM\n",
 384                 dev->dev_addr);
 385
 386        if (priv->card_8192_version > VERSION_8190_BD)
 387                priv->bTXPowerDataReadFromEEPORM = true;
 388        else
 389                priv->bTXPowerDataReadFromEEPORM = false;
 390
 391        priv->rf_type = RTL819X_DEFAULT_RF_TYPE;
 392
 393        if (priv->card_8192_version > VERSION_8190_BD) {
 394                if (!priv->AutoloadFailFlag) {
 395                        tempval = (eprom_read(dev, (EEPROM_RFInd_PowerDiff >>
 396                                              1))) & 0xff;
 397                        priv->EEPROMLegacyHTTxPowerDiff = tempval & 0xf;
 398
 399                        if (tempval&0x80)
 400                                priv->rf_type = RF_1T2R;
 401                        else
 402                                priv->rf_type = RF_2T4R;
 403                } else {
 404                        priv->EEPROMLegacyHTTxPowerDiff = 0x04;
 405                }
 406                RT_TRACE(COMP_INIT, "EEPROMLegacyHTTxPowerDiff = %d\n",
 407                        priv->EEPROMLegacyHTTxPowerDiff);
 408
 409                if (!priv->AutoloadFailFlag)
 410                        priv->EEPROMThermalMeter = (u8)(((eprom_read(dev,
 411                                                   (EEPROM_ThermalMeter>>1))) &
 412                                                   0xff00)>>8);
 413                else
 414                        priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
 415                RT_TRACE(COMP_INIT, "ThermalMeter = %d\n",
 416                         priv->EEPROMThermalMeter);
 417                priv->TSSI_13dBm = priv->EEPROMThermalMeter * 100;
 418
 419                if (priv->epromtype == EEPROM_93C46) {
 420                        if (!priv->AutoloadFailFlag) {
 421                                usValue = eprom_read(dev,
 422                                          (EEPROM_TxPwDiff_CrystalCap >> 1));
 423                                priv->EEPROMAntPwDiff = (usValue&0x0fff);
 424                                priv->EEPROMCrystalCap = (u8)((usValue & 0xf000)
 425                                                         >> 12);
 426                        } else {
 427                                priv->EEPROMAntPwDiff =
 428                                         EEPROM_Default_AntTxPowerDiff;
 429                                priv->EEPROMCrystalCap =
 430                                         EEPROM_Default_TxPwDiff_CrystalCap;
 431                        }
 432                        RT_TRACE(COMP_INIT, "EEPROMAntPwDiff = %d\n",
 433                                 priv->EEPROMAntPwDiff);
 434                        RT_TRACE(COMP_INIT, "EEPROMCrystalCap = %d\n",
 435                                 priv->EEPROMCrystalCap);
 436
 437                        for (i = 0; i < 14; i += 2) {
 438                                if (!priv->AutoloadFailFlag)
 439                                        usValue = eprom_read(dev,
 440                                                  (u16)((EEPROM_TxPwIndex_CCK +
 441                                                  i) >> 1));
 442                                else
 443                                        usValue = EEPROM_Default_TxPower;
 444                                *((u16 *)(&priv->EEPROMTxPowerLevelCCK[i])) =
 445                                                                 usValue;
 446                                RT_TRACE(COMP_INIT, "CCK Tx Power Level, Index"
 447                                         " %d = 0x%02x\n", i,
 448                                         priv->EEPROMTxPowerLevelCCK[i]);
 449                                RT_TRACE(COMP_INIT, "CCK Tx Power Level, Index"
 450                                         " %d = 0x%02x\n", i+1,
 451                                         priv->EEPROMTxPowerLevelCCK[i+1]);
 452                        }
 453                        for (i = 0; i < 14; i += 2) {
 454                                if (!priv->AutoloadFailFlag)
 455                                        usValue = eprom_read(dev,
 456                                                (u16)((EEPROM_TxPwIndex_OFDM_24G
 457                                                + i) >> 1));
 458                                else
 459                                        usValue = EEPROM_Default_TxPower;
 460                                *((u16 *)(&priv->EEPROMTxPowerLevelOFDM24G[i]))
 461                                                         = usValue;
 462                                RT_TRACE(COMP_INIT, "OFDM 2.4G Tx Power Level,"
 463                                         " Index %d = 0x%02x\n", i,
 464                                         priv->EEPROMTxPowerLevelOFDM24G[i]);
 465                                RT_TRACE(COMP_INIT, "OFDM 2.4G Tx Power Level,"
 466                                         " Index %d = 0x%02x\n", i + 1,
 467                                         priv->EEPROMTxPowerLevelOFDM24G[i+1]);
 468                        }
 469                }
 470                if (priv->epromtype == EEPROM_93C46) {
 471                        for (i = 0; i < 14; i++) {
 472                                priv->TxPowerLevelCCK[i] =
 473                                         priv->EEPROMTxPowerLevelCCK[i];
 474                                priv->TxPowerLevelOFDM24G[i] =
 475                                         priv->EEPROMTxPowerLevelOFDM24G[i];
 476                        }
 477                        priv->LegacyHTTxPowerDiff =
 478                                         priv->EEPROMLegacyHTTxPowerDiff;
 479                        priv->AntennaTxPwDiff[0] = (priv->EEPROMAntPwDiff &
 480                                                    0xf);
 481                        priv->AntennaTxPwDiff[1] = ((priv->EEPROMAntPwDiff &
 482                                                    0xf0)>>4);
 483                        priv->AntennaTxPwDiff[2] = ((priv->EEPROMAntPwDiff &
 484                                                    0xf00)>>8);
 485                        priv->CrystalCap = priv->EEPROMCrystalCap;
 486                        priv->ThermalMeter[0] = (priv->EEPROMThermalMeter &
 487                                                 0xf);
 488                        priv->ThermalMeter[1] = ((priv->EEPROMThermalMeter &
 489                                                 0xf0)>>4);
 490                } else if (priv->epromtype == EEPROM_93C56) {
 491
 492                        for (i = 0; i < 3; i++) {
 493                                priv->TxPowerLevelCCK_A[i] =
 494                                         priv->EEPROMRfACCKChnl1TxPwLevel[0];
 495                                priv->TxPowerLevelOFDM24G_A[i] =
 496                                         priv->EEPROMRfAOfdmChnlTxPwLevel[0];
 497                                priv->TxPowerLevelCCK_C[i] =
 498                                         priv->EEPROMRfCCCKChnl1TxPwLevel[0];
 499                                priv->TxPowerLevelOFDM24G_C[i] =
 500                                         priv->EEPROMRfCOfdmChnlTxPwLevel[0];
 501                        }
 502                        for (i = 3; i < 9; i++) {
 503                                priv->TxPowerLevelCCK_A[i]  =
 504                                         priv->EEPROMRfACCKChnl1TxPwLevel[1];
 505                                priv->TxPowerLevelOFDM24G_A[i] =
 506                                         priv->EEPROMRfAOfdmChnlTxPwLevel[1];
 507                                priv->TxPowerLevelCCK_C[i] =
 508                                         priv->EEPROMRfCCCKChnl1TxPwLevel[1];
 509                                priv->TxPowerLevelOFDM24G_C[i] =
 510                                         priv->EEPROMRfCOfdmChnlTxPwLevel[1];
 511                        }
 512                        for (i = 9; i < 14; i++) {
 513                                priv->TxPowerLevelCCK_A[i]  =
 514                                         priv->EEPROMRfACCKChnl1TxPwLevel[2];
 515                                priv->TxPowerLevelOFDM24G_A[i] =
 516                                         priv->EEPROMRfAOfdmChnlTxPwLevel[2];
 517                                priv->TxPowerLevelCCK_C[i] =
 518                                         priv->EEPROMRfCCCKChnl1TxPwLevel[2];
 519                                priv->TxPowerLevelOFDM24G_C[i] =
 520                                         priv->EEPROMRfCOfdmChnlTxPwLevel[2];
 521                        }
 522                        for (i = 0; i < 14; i++)
 523                                RT_TRACE(COMP_INIT, "priv->TxPowerLevelCCK_A"
 524                                         "[%d] = 0x%x\n", i,
 525                                         priv->TxPowerLevelCCK_A[i]);
 526                        for (i = 0; i < 14; i++)
 527                                RT_TRACE(COMP_INIT, "priv->TxPowerLevelOFDM"
 528                                         "24G_A[%d] = 0x%x\n", i,
 529                                         priv->TxPowerLevelOFDM24G_A[i]);
 530                        for (i = 0; i < 14; i++)
 531                                RT_TRACE(COMP_INIT, "priv->TxPowerLevelCCK_C"
 532                                         "[%d] = 0x%x\n", i,
 533                                         priv->TxPowerLevelCCK_C[i]);
 534                        for (i = 0; i < 14; i++)
 535                                RT_TRACE(COMP_INIT, "priv->TxPowerLevelOFDM"
 536                                         "24G_C[%d] = 0x%x\n", i,
 537                                         priv->TxPowerLevelOFDM24G_C[i]);
 538                        priv->LegacyHTTxPowerDiff =
 539                                 priv->EEPROMLegacyHTTxPowerDiff;
 540                        priv->AntennaTxPwDiff[0] = 0;
 541                        priv->AntennaTxPwDiff[1] = 0;
 542                        priv->AntennaTxPwDiff[2] = 0;
 543                        priv->CrystalCap = priv->EEPROMCrystalCap;
 544                        priv->ThermalMeter[0] = (priv->EEPROMThermalMeter &
 545                                                 0xf);
 546                        priv->ThermalMeter[1] = ((priv->EEPROMThermalMeter &
 547                                                 0xf0)>>4);
 548                }
 549        }
 550
 551        if (priv->rf_type == RF_1T2R) {
 552                /* no matter what checkpatch says, the braces are needed */
 553                RT_TRACE(COMP_INIT, "\n1T2R config\n");
 554        } else if (priv->rf_type == RF_2T4R) {
 555                RT_TRACE(COMP_INIT, "\n2T4R config\n");
 556        }
 557
 558        init_rate_adaptive(dev);
 559
 560        priv->rf_chip = RF_8256;
 561
 562        if (priv->RegChannelPlan == 0xf)
 563                priv->ChannelPlan = priv->eeprom_ChannelPlan;
 564        else
 565                priv->ChannelPlan = priv->RegChannelPlan;
 566
 567        if (priv->eeprom_vid == 0x1186 &&  priv->eeprom_did == 0x3304)
 568                priv->CustomerID =  RT_CID_DLINK;
 569
 570        switch (priv->eeprom_CustomerID) {
 571        case EEPROM_CID_DEFAULT:
 572                priv->CustomerID = RT_CID_DEFAULT;
 573                break;
 574        case EEPROM_CID_CAMEO:
 575                priv->CustomerID = RT_CID_819x_CAMEO;
 576                break;
 577        case  EEPROM_CID_RUNTOP:
 578                priv->CustomerID = RT_CID_819x_RUNTOP;
 579                break;
 580        case EEPROM_CID_NetCore:
 581                priv->CustomerID = RT_CID_819x_Netcore;
 582                break;
 583        case EEPROM_CID_TOSHIBA:
 584                priv->CustomerID = RT_CID_TOSHIBA;
 585                if (priv->eeprom_ChannelPlan&0x80)
 586                        priv->ChannelPlan = priv->eeprom_ChannelPlan&0x7f;
 587                else
 588                        priv->ChannelPlan = 0x0;
 589                RT_TRACE(COMP_INIT, "Toshiba ChannelPlan = 0x%x\n",
 590                        priv->ChannelPlan);
 591                break;
 592        case EEPROM_CID_Nettronix:
 593                priv->ScanDelay = 100;
 594                priv->CustomerID = RT_CID_Nettronix;
 595                break;
 596        case EEPROM_CID_Pronet:
 597                priv->CustomerID = RT_CID_PRONET;
 598                break;
 599        case EEPROM_CID_DLINK:
 600                priv->CustomerID = RT_CID_DLINK;
 601                break;
 602
 603        case EEPROM_CID_WHQL:
 604                break;
 605        default:
 606                break;
 607        }
 608
 609        if (priv->ChannelPlan > CHANNEL_PLAN_LEN - 1)
 610                priv->ChannelPlan = 0;
 611        priv->ChannelPlan = COUNTRY_CODE_WORLD_WIDE_13;
 612
 613        if (priv->eeprom_vid == 0x1186 &&  priv->eeprom_did == 0x3304)
 614                priv->rtllib->bSupportRemoteWakeUp = true;
 615        else
 616                priv->rtllib->bSupportRemoteWakeUp = false;
 617
 618        RT_TRACE(COMP_INIT, "RegChannelPlan(%d)\n", priv->RegChannelPlan);
 619        RT_TRACE(COMP_INIT, "ChannelPlan = %d\n", priv->ChannelPlan);
 620        RT_TRACE(COMP_TRACE, "<==== ReadAdapterInfo\n");
 621}
 622
 623void rtl8192_get_eeprom_size(struct net_device *dev)
 624{
 625        u16 curCR;
 626        struct r8192_priv *priv = rtllib_priv(dev);
 627
 628        RT_TRACE(COMP_INIT, "===========>%s()\n", __func__);
 629        curCR = read_nic_dword(dev, EPROM_CMD);
 630        RT_TRACE(COMP_INIT, "read from Reg Cmd9346CR(%x):%x\n", EPROM_CMD,
 631                 curCR);
 632        priv->epromtype = (curCR & EPROM_CMD_9356SEL) ? EEPROM_93C56 :
 633                          EEPROM_93C46;
 634        RT_TRACE(COMP_INIT, "<===========%s(), epromtype:%d\n", __func__,
 635                 priv->epromtype);
 636        rtl8192_read_eeprom_info(dev);
 637}
 638
 639static void rtl8192_hwconfig(struct net_device *dev)
 640{
 641        u32 regRATR = 0, regRRSR = 0;
 642        u8 regBwOpMode = 0, regTmp = 0;
 643        struct r8192_priv *priv = rtllib_priv(dev);
 644
 645        switch (priv->rtllib->mode) {
 646        case WIRELESS_MODE_B:
 647                regBwOpMode = BW_OPMODE_20MHZ;
 648                regRATR = RATE_ALL_CCK;
 649                regRRSR = RATE_ALL_CCK;
 650                break;
 651        case WIRELESS_MODE_A:
 652                regBwOpMode = BW_OPMODE_5G | BW_OPMODE_20MHZ;
 653                regRATR = RATE_ALL_OFDM_AG;
 654                regRRSR = RATE_ALL_OFDM_AG;
 655                break;
 656        case WIRELESS_MODE_G:
 657                regBwOpMode = BW_OPMODE_20MHZ;
 658                regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 659                regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 660                break;
 661        case WIRELESS_MODE_AUTO:
 662        case WIRELESS_MODE_N_24G:
 663                regBwOpMode = BW_OPMODE_20MHZ;
 664                        regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
 665                                  RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
 666                        regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 667                break;
 668        case WIRELESS_MODE_N_5G:
 669                regBwOpMode = BW_OPMODE_5G;
 670                regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS |
 671                          RATE_ALL_OFDM_2SS;
 672                regRRSR = RATE_ALL_OFDM_AG;
 673                break;
 674        default:
 675                regBwOpMode = BW_OPMODE_20MHZ;
 676                regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 677                regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 678                break;
 679        }
 680
 681        write_nic_byte(dev, BW_OPMODE, regBwOpMode);
 682        {
 683                u32 ratr_value = 0;
 684                ratr_value = regRATR;
 685                if (priv->rf_type == RF_1T2R)
 686                        ratr_value &= ~(RATE_ALL_OFDM_2SS);
 687                write_nic_dword(dev, RATR0, ratr_value);
 688                write_nic_byte(dev, UFWP, 1);
 689        }
 690        regTmp = read_nic_byte(dev, 0x313);
 691        regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff);
 692        write_nic_dword(dev, RRSR, regRRSR);
 693
 694        write_nic_word(dev, RETRY_LIMIT,
 695                        priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT |
 696                        priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT);
 697}
 698
 699bool rtl8192_adapter_start(struct net_device *dev)
 700{
 701        struct r8192_priv *priv = rtllib_priv(dev);
 702        u32 ulRegRead;
 703        bool rtStatus = true;
 704        u8 tmpvalue;
 705        u8 ICVersion, SwitchingRegulatorOutput;
 706        bool bfirmwareok = true;
 707        u32 tmpRegA, tmpRegC, TempCCk;
 708        int i = 0;
 709        u32 retry_times = 0;
 710
 711        RT_TRACE(COMP_INIT, "====>%s()\n", __func__);
 712        priv->being_init_adapter = true;
 713
 714start:
 715        rtl8192_pci_resetdescring(dev);
 716        priv->Rf_Mode = RF_OP_By_SW_3wire;
 717        if (priv->ResetProgress == RESET_TYPE_NORESET) {
 718                write_nic_byte(dev, ANAPAR, 0x37);
 719                mdelay(500);
 720        }
 721        priv->pFirmware->firmware_status = FW_STATUS_0_INIT;
 722
 723        if (priv->RegRfOff == true)
 724                priv->rtllib->eRFPowerState = eRfOff;
 725
 726        ulRegRead = read_nic_dword(dev, CPU_GEN);
 727        if (priv->pFirmware->firmware_status == FW_STATUS_0_INIT)
 728                ulRegRead |= CPU_GEN_SYSTEM_RESET;
 729        else if (priv->pFirmware->firmware_status == FW_STATUS_5_READY)
 730                ulRegRead |= CPU_GEN_FIRMWARE_RESET;
 731        else
 732                RT_TRACE(COMP_ERR, "ERROR in %s(): undefined firmware state(%d)"
 733                         "\n", __func__,   priv->pFirmware->firmware_status);
 734
 735        write_nic_dword(dev, CPU_GEN, ulRegRead);
 736
 737        ICVersion = read_nic_byte(dev, IC_VERRSION);
 738        if (ICVersion >= 0x4) {
 739                SwitchingRegulatorOutput = read_nic_byte(dev, SWREGULATOR);
 740                if (SwitchingRegulatorOutput  != 0xb8) {
 741                        write_nic_byte(dev, SWREGULATOR, 0xa8);
 742                        mdelay(1);
 743                        write_nic_byte(dev, SWREGULATOR, 0xb8);
 744                }
 745        }
 746        RT_TRACE(COMP_INIT, "BB Config Start!\n");
 747        rtStatus = rtl8192_BBConfig(dev);
 748        if (rtStatus != true) {
 749                RT_TRACE(COMP_ERR, "BB Config failed\n");
 750                return rtStatus;
 751        }
 752        RT_TRACE(COMP_INIT, "BB Config Finished!\n");
 753
 754        priv->LoopbackMode = RTL819X_NO_LOOPBACK;
 755        if (priv->ResetProgress == RESET_TYPE_NORESET) {
 756                ulRegRead = read_nic_dword(dev, CPU_GEN);
 757                if (priv->LoopbackMode == RTL819X_NO_LOOPBACK)
 758                        ulRegRead = ((ulRegRead & CPU_GEN_NO_LOOPBACK_MSK) |
 759                                     CPU_GEN_NO_LOOPBACK_SET);
 760                else if (priv->LoopbackMode == RTL819X_MAC_LOOPBACK)
 761                        ulRegRead |= CPU_CCK_LOOPBACK;
 762                else
 763                        RT_TRACE(COMP_ERR, "Serious error: wrong loopback"
 764                                 " mode setting\n");
 765
 766                write_nic_dword(dev, CPU_GEN, ulRegRead);
 767
 768                udelay(500);
 769        }
 770        rtl8192_hwconfig(dev);
 771        write_nic_byte(dev, CMDR, CR_RE | CR_TE);
 772
 773        write_nic_byte(dev, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
 774                       (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT)));
 775        write_nic_dword(dev, MAC0, ((u32 *)dev->dev_addr)[0]);
 776        write_nic_word(dev, MAC4, ((u16 *)(dev->dev_addr + 4))[0]);
 777        write_nic_dword(dev, RCR, priv->ReceiveConfig);
 778
 779        write_nic_dword(dev, RQPN1,  NUM_OF_PAGE_IN_FW_QUEUE_BK <<
 780                        RSVD_FW_QUEUE_PAGE_BK_SHIFT |
 781                        NUM_OF_PAGE_IN_FW_QUEUE_BE <<
 782                        RSVD_FW_QUEUE_PAGE_BE_SHIFT |
 783                        NUM_OF_PAGE_IN_FW_QUEUE_VI <<
 784                        RSVD_FW_QUEUE_PAGE_VI_SHIFT |
 785                        NUM_OF_PAGE_IN_FW_QUEUE_VO <<
 786                        RSVD_FW_QUEUE_PAGE_VO_SHIFT);
 787        write_nic_dword(dev, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT <<
 788                        RSVD_FW_QUEUE_PAGE_MGNT_SHIFT);
 789        write_nic_dword(dev, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW |
 790                        NUM_OF_PAGE_IN_FW_QUEUE_BCN <<
 791                        RSVD_FW_QUEUE_PAGE_BCN_SHIFT|
 792                        NUM_OF_PAGE_IN_FW_QUEUE_PUB <<
 793                        RSVD_FW_QUEUE_PAGE_PUB_SHIFT);
 794
 795        rtl8192_tx_enable(dev);
 796        rtl8192_rx_enable(dev);
 797        ulRegRead = (0xFFF00000 & read_nic_dword(dev, RRSR))  |
 798                     RATE_ALL_OFDM_AG | RATE_ALL_CCK;
 799        write_nic_dword(dev, RRSR, ulRegRead);
 800        write_nic_dword(dev, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK));
 801
 802        write_nic_byte(dev, ACK_TIMEOUT, 0x30);
 803
 804        if (priv->ResetProgress == RESET_TYPE_NORESET)
 805                rtl8192_SetWirelessMode(dev, priv->rtllib->mode);
 806        CamResetAllEntry(dev);
 807        {
 808                u8 SECR_value = 0x0;
 809                SECR_value |= SCR_TxEncEnable;
 810                SECR_value |= SCR_RxDecEnable;
 811                SECR_value |= SCR_NoSKMC;
 812                write_nic_byte(dev, SECR, SECR_value);
 813        }
 814        write_nic_word(dev, ATIMWND, 2);
 815        write_nic_word(dev, BCN_INTERVAL, 100);
 816        {
 817                int i;
 818                for (i = 0; i < QOS_QUEUE_NUM; i++)
 819                        write_nic_dword(dev, WDCAPARA_ADD[i], 0x005e4332);
 820        }
 821        write_nic_byte(dev, 0xbe, 0xc0);
 822
 823        rtl8192_phy_configmac(dev);
 824
 825        if (priv->card_8192_version > (u8) VERSION_8190_BD) {
 826                rtl8192_phy_getTxPower(dev);
 827                rtl8192_phy_setTxPower(dev, priv->chan);
 828        }
 829
 830        tmpvalue = read_nic_byte(dev, IC_VERRSION);
 831        priv->IC_Cut = tmpvalue;
 832        RT_TRACE(COMP_INIT, "priv->IC_Cut= 0x%x\n", priv->IC_Cut);
 833        if (priv->IC_Cut >= IC_VersionCut_D) {
 834                if (priv->IC_Cut == IC_VersionCut_D) {
 835                        /* no matter what checkpatch says, braces are needed */
 836                        RT_TRACE(COMP_INIT, "D-cut\n");
 837                } else if (priv->IC_Cut == IC_VersionCut_E) {
 838                        RT_TRACE(COMP_INIT, "E-cut\n");
 839                }
 840        } else {
 841                RT_TRACE(COMP_INIT, "Before C-cut\n");
 842        }
 843
 844        RT_TRACE(COMP_INIT, "Load Firmware!\n");
 845        bfirmwareok = init_firmware(dev);
 846        if (!bfirmwareok) {
 847                if (retry_times < 10) {
 848                        retry_times++;
 849                        goto start;
 850                } else {
 851                        rtStatus = false;
 852                        goto end;
 853                }
 854        }
 855        RT_TRACE(COMP_INIT, "Load Firmware finished!\n");
 856        if (priv->ResetProgress == RESET_TYPE_NORESET) {
 857                RT_TRACE(COMP_INIT, "RF Config Started!\n");
 858                rtStatus = rtl8192_phy_RFConfig(dev);
 859                if (rtStatus != true) {
 860                        RT_TRACE(COMP_ERR, "RF Config failed\n");
 861                        return rtStatus;
 862                }
 863                RT_TRACE(COMP_INIT, "RF Config Finished!\n");
 864        }
 865        rtl8192_phy_updateInitGain(dev);
 866
 867        rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
 868        rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
 869
 870        write_nic_byte(dev, 0x87, 0x0);
 871
 872        if (priv->RegRfOff == true) {
 873                RT_TRACE((COMP_INIT | COMP_RF | COMP_POWER),
 874                          "%s(): Turn off RF for RegRfOff ----------\n",
 875                          __func__);
 876                MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_SW, true);
 877        } else if (priv->rtllib->RfOffReason > RF_CHANGE_BY_PS) {
 878                RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): Turn off RF for"
 879                         " RfOffReason(%d) ----------\n", __func__,
 880                         priv->rtllib->RfOffReason);
 881                MgntActSet_RF_State(dev, eRfOff, priv->rtllib->RfOffReason,
 882                                    true);
 883        } else if (priv->rtllib->RfOffReason >= RF_CHANGE_BY_IPS) {
 884                RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): Turn off RF for"
 885                         " RfOffReason(%d) ----------\n", __func__,
 886                         priv->rtllib->RfOffReason);
 887                MgntActSet_RF_State(dev, eRfOff, priv->rtllib->RfOffReason,
 888                                    true);
 889        } else {
 890                RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): RF-ON\n",
 891                          __func__);
 892                priv->rtllib->eRFPowerState = eRfOn;
 893                priv->rtllib->RfOffReason = 0;
 894        }
 895
 896        if (priv->rtllib->FwRWRF)
 897                priv->Rf_Mode = RF_OP_By_FW;
 898        else
 899                priv->Rf_Mode = RF_OP_By_SW_3wire;
 900
 901        if (priv->ResetProgress == RESET_TYPE_NORESET) {
 902                dm_initialize_txpower_tracking(dev);
 903
 904                if (priv->IC_Cut >= IC_VersionCut_D) {
 905                        tmpRegA = rtl8192_QueryBBReg(dev,
 906                                  rOFDM0_XATxIQImbalance, bMaskDWord);
 907                        tmpRegC = rtl8192_QueryBBReg(dev,
 908                                  rOFDM0_XCTxIQImbalance, bMaskDWord);
 909                        for (i = 0; i < TxBBGainTableLength; i++) {
 910                                if (tmpRegA ==
 911                                    priv->txbbgain_table[i].txbbgain_value) {
 912                                        priv->rfa_txpowertrackingindex = (u8)i;
 913                                        priv->rfa_txpowertrackingindex_real =
 914                                                 (u8)i;
 915                                        priv->rfa_txpowertracking_default =
 916                                                 priv->rfa_txpowertrackingindex;
 917                                        break;
 918                                }
 919                        }
 920
 921                        TempCCk = rtl8192_QueryBBReg(dev,
 922                                  rCCK0_TxFilter1, bMaskByte2);
 923
 924                        for (i = 0; i < CCKTxBBGainTableLength; i++) {
 925                                if (TempCCk == priv->cck_txbbgain_table[i].ccktxbb_valuearray[0]) {
 926                                        priv->CCKPresentAttentuation_20Mdefault = (u8)i;
 927                                        break;
 928                                }
 929                        }
 930                        priv->CCKPresentAttentuation_40Mdefault = 0;
 931                        priv->CCKPresentAttentuation_difference = 0;
 932                        priv->CCKPresentAttentuation =
 933                                  priv->CCKPresentAttentuation_20Mdefault;
 934                        RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpower"
 935                                 "trackingindex_initial = %d\n",
 936                                 priv->rfa_txpowertrackingindex);
 937                        RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpower"
 938                                 "trackingindex_real__initial = %d\n",
 939                                 priv->rfa_txpowertrackingindex_real);
 940                        RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresent"
 941                                 "Attentuation_difference_initial = %d\n",
 942                                  priv->CCKPresentAttentuation_difference);
 943                        RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresent"
 944                                 "Attentuation_initial = %d\n",
 945                                 priv->CCKPresentAttentuation);
 946                        priv->btxpower_tracking = false;
 947                }
 948        }
 949        rtl8192_irq_enable(dev);
 950end:
 951        priv->being_init_adapter = false;
 952        return rtStatus;
 953}
 954
 955static void rtl8192_net_update(struct net_device *dev)
 956{
 957
 958        struct r8192_priv *priv = rtllib_priv(dev);
 959        struct rtllib_network *net;
 960        u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf;
 961        u16 rate_config = 0;
 962
 963        net = &priv->rtllib->current_network;
 964        rtl8192_config_rate(dev, &rate_config);
 965        priv->dot11CurrentPreambleMode = PREAMBLE_AUTO;
 966         priv->basic_rate = rate_config &= 0x15f;
 967        write_nic_dword(dev, BSSIDR, ((u32 *)net->bssid)[0]);
 968        write_nic_word(dev, BSSIDR+4, ((u16 *)net->bssid)[2]);
 969
 970        if (priv->rtllib->iw_mode == IW_MODE_ADHOC) {
 971                write_nic_word(dev, ATIMWND, 2);
 972                write_nic_word(dev, BCN_DMATIME, 256);
 973                write_nic_word(dev, BCN_INTERVAL, net->beacon_interval);
 974                write_nic_word(dev, BCN_DRV_EARLY_INT, 10);
 975                write_nic_byte(dev, BCN_ERR_THRESH, 100);
 976
 977                BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT);
 978                BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
 979
 980                write_nic_word(dev, BCN_TCFG, BcnTimeCfg);
 981        }
 982}
 983
 984void rtl8192_link_change(struct net_device *dev)
 985{
 986        struct r8192_priv *priv = rtllib_priv(dev);
 987        struct rtllib_device *ieee = priv->rtllib;
 988
 989        if (!priv->up)
 990                return;
 991
 992        if (ieee->state == RTLLIB_LINKED) {
 993                rtl8192_net_update(dev);
 994                priv->ops->update_ratr_table(dev);
 995                if ((KEY_TYPE_WEP40 == ieee->pairwise_key_type) ||
 996                    (KEY_TYPE_WEP104 == ieee->pairwise_key_type))
 997                        EnableHWSecurityConfig8192(dev);
 998        } else {
 999                write_nic_byte(dev, 0x173, 0);
1000        }
1001        rtl8192e_update_msr(dev);
1002
1003        if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC) {
1004                u32 reg = 0;
1005                reg = read_nic_dword(dev, RCR);
1006                if (priv->rtllib->state == RTLLIB_LINKED) {
1007                        if (ieee->IntelPromiscuousModeInfo.bPromiscuousOn)
1008                                ;
1009                        else
1010                                priv->ReceiveConfig = reg |= RCR_CBSSID;
1011                } else
1012                        priv->ReceiveConfig = reg &= ~RCR_CBSSID;
1013
1014                write_nic_dword(dev, RCR, reg);
1015        }
1016}
1017
1018void rtl8192_AllowAllDestAddr(struct net_device *dev,
1019                              bool bAllowAllDA, bool WriteIntoReg)
1020{
1021        struct r8192_priv *priv = rtllib_priv(dev);
1022
1023        if (bAllowAllDA)
1024                priv->ReceiveConfig |= RCR_AAP;
1025        else
1026                priv->ReceiveConfig &= ~RCR_AAP;
1027
1028        if (WriteIntoReg)
1029                write_nic_dword(dev, RCR, priv->ReceiveConfig);
1030}
1031
1032static u8 MRateToHwRate8190Pci(u8 rate)
1033{
1034        u8  ret = DESC90_RATE1M;
1035
1036        switch (rate) {
1037        case MGN_1M:
1038                ret = DESC90_RATE1M;
1039                break;
1040        case MGN_2M:
1041                ret = DESC90_RATE2M;
1042                break;
1043        case MGN_5_5M:
1044                ret = DESC90_RATE5_5M;
1045                break;
1046        case MGN_11M:
1047                ret = DESC90_RATE11M;
1048                break;
1049        case MGN_6M:
1050                ret = DESC90_RATE6M;
1051                break;
1052        case MGN_9M:
1053                ret = DESC90_RATE9M;
1054                break;
1055        case MGN_12M:
1056                ret = DESC90_RATE12M;
1057                break;
1058        case MGN_18M:
1059                ret = DESC90_RATE18M;
1060                break;
1061        case MGN_24M:
1062                ret = DESC90_RATE24M;
1063                break;
1064        case MGN_36M:
1065                ret = DESC90_RATE36M;
1066                break;
1067        case MGN_48M:
1068                ret = DESC90_RATE48M;
1069                break;
1070        case MGN_54M:
1071                ret = DESC90_RATE54M;
1072                break;
1073        case MGN_MCS0:
1074                ret = DESC90_RATEMCS0;
1075                break;
1076        case MGN_MCS1:
1077                ret = DESC90_RATEMCS1;
1078                break;
1079        case MGN_MCS2:
1080                ret = DESC90_RATEMCS2;
1081                break;
1082        case MGN_MCS3:
1083                ret = DESC90_RATEMCS3;
1084                break;
1085        case MGN_MCS4:
1086                ret = DESC90_RATEMCS4;
1087                break;
1088        case MGN_MCS5:
1089                ret = DESC90_RATEMCS5;
1090                break;
1091        case MGN_MCS6:
1092                ret = DESC90_RATEMCS6;
1093                break;
1094        case MGN_MCS7:
1095                ret = DESC90_RATEMCS7;
1096                break;
1097        case MGN_MCS8:
1098                ret = DESC90_RATEMCS8;
1099                break;
1100        case MGN_MCS9:
1101                ret = DESC90_RATEMCS9;
1102                break;
1103        case MGN_MCS10:
1104                ret = DESC90_RATEMCS10;
1105                break;
1106        case MGN_MCS11:
1107                ret = DESC90_RATEMCS11;
1108                break;
1109        case MGN_MCS12:
1110                ret = DESC90_RATEMCS12;
1111                break;
1112        case MGN_MCS13:
1113                ret = DESC90_RATEMCS13;
1114                break;
1115        case MGN_MCS14:
1116                ret = DESC90_RATEMCS14;
1117                break;
1118        case MGN_MCS15:
1119                ret = DESC90_RATEMCS15;
1120                break;
1121        case (0x80|0x20):
1122                ret = DESC90_RATEMCS32;
1123                break;
1124        default:
1125                break;
1126        }
1127        return ret;
1128}
1129
1130static u8 rtl8192_MapHwQueueToFirmwareQueue(u8 QueueID, u8 priority)
1131{
1132        u8 QueueSelect = 0x0;
1133
1134        switch (QueueID) {
1135        case BE_QUEUE:
1136                QueueSelect = QSLT_BE;
1137                break;
1138
1139        case BK_QUEUE:
1140                QueueSelect = QSLT_BK;
1141                break;
1142
1143        case VO_QUEUE:
1144                QueueSelect = QSLT_VO;
1145                break;
1146
1147        case VI_QUEUE:
1148                QueueSelect = QSLT_VI;
1149                break;
1150        case MGNT_QUEUE:
1151                QueueSelect = QSLT_MGNT;
1152                break;
1153        case BEACON_QUEUE:
1154                QueueSelect = QSLT_BEACON;
1155                break;
1156        case TXCMD_QUEUE:
1157                QueueSelect = QSLT_CMD;
1158                break;
1159        case HIGH_QUEUE:
1160                QueueSelect = QSLT_HIGH;
1161                break;
1162        default:
1163                RT_TRACE(COMP_ERR, "TransmitTCB(): Impossible Queue Selection:"
1164                         " %d\n", QueueID);
1165                break;
1166        }
1167        return QueueSelect;
1168}
1169
1170void  rtl8192_tx_fill_desc(struct net_device *dev, struct tx_desc *pdesc,
1171                           struct cb_desc *cb_desc, struct sk_buff *skb)
1172{
1173        struct r8192_priv *priv = rtllib_priv(dev);
1174        dma_addr_t mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1175                         PCI_DMA_TODEVICE);
1176        struct tx_fwinfo_8190pci *pTxFwInfo = NULL;
1177        pTxFwInfo = (struct tx_fwinfo_8190pci *)skb->data;
1178        memset(pTxFwInfo, 0, sizeof(struct tx_fwinfo_8190pci));
1179        pTxFwInfo->TxHT = (cb_desc->data_rate & 0x80) ? 1 : 0;
1180        pTxFwInfo->TxRate = MRateToHwRate8190Pci((u8)cb_desc->data_rate);
1181        pTxFwInfo->EnableCPUDur = cb_desc->bTxEnableFwCalcDur;
1182        pTxFwInfo->Short = rtl8192_QueryIsShort(pTxFwInfo->TxHT,
1183                                                pTxFwInfo->TxRate,
1184                                                cb_desc);
1185
1186        if (pci_dma_mapping_error(priv->pdev, mapping))
1187                RT_TRACE(COMP_ERR, "DMA Mapping error\n");;
1188        if (cb_desc->bAMPDUEnable) {
1189                pTxFwInfo->AllowAggregation = 1;
1190                pTxFwInfo->RxMF = cb_desc->ampdu_factor;
1191                pTxFwInfo->RxAMD = cb_desc->ampdu_density;
1192        } else {
1193                pTxFwInfo->AllowAggregation = 0;
1194                pTxFwInfo->RxMF = 0;
1195                pTxFwInfo->RxAMD = 0;
1196        }
1197
1198        pTxFwInfo->RtsEnable =  (cb_desc->bRTSEnable) ? 1 : 0;
1199        pTxFwInfo->CtsEnable = (cb_desc->bCTSEnable) ? 1 : 0;
1200        pTxFwInfo->RtsSTBC = (cb_desc->bRTSSTBC) ? 1 : 0;
1201        pTxFwInfo->RtsHT = (cb_desc->rts_rate&0x80) ? 1 : 0;
1202        pTxFwInfo->RtsRate = MRateToHwRate8190Pci((u8)cb_desc->rts_rate);
1203        pTxFwInfo->RtsBandwidth = 0;
1204        pTxFwInfo->RtsSubcarrier = cb_desc->RTSSC;
1205        pTxFwInfo->RtsShort = (pTxFwInfo->RtsHT == 0) ?
1206                          (cb_desc->bRTSUseShortPreamble ? 1 : 0) :
1207                          (cb_desc->bRTSUseShortGI ? 1 : 0);
1208        if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) {
1209                if (cb_desc->bPacketBW) {
1210                        pTxFwInfo->TxBandwidth = 1;
1211                        pTxFwInfo->TxSubCarrier = 0;
1212                } else {
1213                        pTxFwInfo->TxBandwidth = 0;
1214                        pTxFwInfo->TxSubCarrier = priv->nCur40MhzPrimeSC;
1215                }
1216        } else {
1217                pTxFwInfo->TxBandwidth = 0;
1218                pTxFwInfo->TxSubCarrier = 0;
1219        }
1220
1221        memset((u8 *)pdesc, 0, 12);
1222        pdesc->LINIP = 0;
1223        pdesc->CmdInit = 1;
1224        pdesc->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1225        pdesc->PktSize = (u16)skb->len-sizeof(struct tx_fwinfo_8190pci);
1226
1227        pdesc->SecCAMID = 0;
1228        pdesc->RATid = cb_desc->RATRIndex;
1229
1230
1231        pdesc->NoEnc = 1;
1232        pdesc->SecType = 0x0;
1233        if (cb_desc->bHwSec) {
1234                static u8 tmp;
1235                if (!tmp) {
1236                        RT_TRACE(COMP_DBG, "==>================hw sec\n");
1237                        tmp = 1;
1238                }
1239                switch (priv->rtllib->pairwise_key_type) {
1240                case KEY_TYPE_WEP40:
1241                case KEY_TYPE_WEP104:
1242                        pdesc->SecType = 0x1;
1243                        pdesc->NoEnc = 0;
1244                        break;
1245                case KEY_TYPE_TKIP:
1246                        pdesc->SecType = 0x2;
1247                        pdesc->NoEnc = 0;
1248                        break;
1249                case KEY_TYPE_CCMP:
1250                        pdesc->SecType = 0x3;
1251                        pdesc->NoEnc = 0;
1252                        break;
1253                case KEY_TYPE_NA:
1254                        pdesc->SecType = 0x0;
1255                        pdesc->NoEnc = 1;
1256                        break;
1257                }
1258        }
1259
1260        pdesc->PktId = 0x0;
1261
1262        pdesc->QueueSelect = rtl8192_MapHwQueueToFirmwareQueue(
1263                                                cb_desc->queue_index,
1264                                                cb_desc->priority);
1265        pdesc->TxFWInfoSize = sizeof(struct tx_fwinfo_8190pci);
1266
1267        pdesc->DISFB = cb_desc->bTxDisableRateFallBack;
1268        pdesc->USERATE = cb_desc->bTxUseDriverAssingedRate;
1269
1270        pdesc->FirstSeg = 1;
1271        pdesc->LastSeg = 1;
1272        pdesc->TxBufferSize = skb->len;
1273
1274        pdesc->TxBuffAddr = cpu_to_le32(mapping);
1275}
1276
1277void  rtl8192_tx_fill_cmd_desc(struct net_device *dev,
1278                               struct tx_desc_cmd *entry,
1279                               struct cb_desc *cb_desc, struct sk_buff* skb)
1280{
1281        struct r8192_priv *priv = rtllib_priv(dev);
1282        dma_addr_t mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1283                         PCI_DMA_TODEVICE);
1284
1285        if (pci_dma_mapping_error(priv->pdev, mapping))
1286                RT_TRACE(COMP_ERR, "DMA Mapping error\n");;
1287        memset(entry, 0, 12);
1288        entry->LINIP = cb_desc->bLastIniPkt;
1289        entry->FirstSeg = 1;
1290        entry->LastSeg = 1;
1291        if (cb_desc->bCmdOrInit == DESC_PACKET_TYPE_INIT) {
1292                entry->CmdInit = DESC_PACKET_TYPE_INIT;
1293        } else {
1294                struct tx_desc * entry_tmp = (struct tx_desc *)entry;
1295                entry_tmp->CmdInit = DESC_PACKET_TYPE_NORMAL;
1296                entry_tmp->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1297                entry_tmp->PktSize = (u16)(cb_desc->pkt_size +
1298                                      entry_tmp->Offset);
1299                entry_tmp->QueueSelect = QSLT_CMD;
1300                entry_tmp->TxFWInfoSize = 0x08;
1301                entry_tmp->RATid = (u8)DESC_PACKET_TYPE_INIT;
1302        }
1303        entry->TxBufferSize = skb->len;
1304        entry->TxBuffAddr = cpu_to_le32(mapping);
1305        entry->OWN = 1;
1306}
1307
1308static u8 HwRateToMRate90(bool bIsHT, u8 rate)
1309{
1310        u8  ret_rate = 0x02;
1311
1312        if (!bIsHT) {
1313                switch (rate) {
1314                case DESC90_RATE1M:
1315                        ret_rate = MGN_1M;
1316                        break;
1317                case DESC90_RATE2M:
1318                        ret_rate = MGN_2M;
1319                        break;
1320                case DESC90_RATE5_5M:
1321                        ret_rate = MGN_5_5M;
1322                        break;
1323                case DESC90_RATE11M:
1324                        ret_rate = MGN_11M;
1325                        break;
1326                case DESC90_RATE6M:
1327                        ret_rate = MGN_6M;
1328                        break;
1329                case DESC90_RATE9M:
1330                        ret_rate = MGN_9M;
1331                        break;
1332                case DESC90_RATE12M:
1333                        ret_rate = MGN_12M;
1334                        break;
1335                case DESC90_RATE18M:
1336                        ret_rate = MGN_18M;
1337                        break;
1338                case DESC90_RATE24M:
1339                        ret_rate = MGN_24M;
1340                        break;
1341                case DESC90_RATE36M:
1342                        ret_rate = MGN_36M;
1343                        break;
1344                case DESC90_RATE48M:
1345                        ret_rate = MGN_48M;
1346                        break;
1347                case DESC90_RATE54M:
1348                        ret_rate = MGN_54M;
1349                        break;
1350
1351                default:
1352                        RT_TRACE(COMP_RECV, "HwRateToMRate90(): Non supported"
1353                                 "Rate [%x], bIsHT = %d!!!\n", rate, bIsHT);
1354                                                  break;
1355                }
1356
1357        } else {
1358                switch (rate) {
1359                case DESC90_RATEMCS0:
1360                        ret_rate = MGN_MCS0;
1361                        break;
1362                case DESC90_RATEMCS1:
1363                        ret_rate = MGN_MCS1;
1364                        break;
1365                case DESC90_RATEMCS2:
1366                        ret_rate = MGN_MCS2;
1367                        break;
1368                case DESC90_RATEMCS3:
1369                        ret_rate = MGN_MCS3;
1370                        break;
1371                case DESC90_RATEMCS4:
1372                        ret_rate = MGN_MCS4;
1373                        break;
1374                case DESC90_RATEMCS5:
1375                        ret_rate = MGN_MCS5;
1376                        break;
1377                case DESC90_RATEMCS6:
1378                        ret_rate = MGN_MCS6;
1379                        break;
1380                case DESC90_RATEMCS7:
1381                        ret_rate = MGN_MCS7;
1382                        break;
1383                case DESC90_RATEMCS8:
1384                        ret_rate = MGN_MCS8;
1385                        break;
1386                case DESC90_RATEMCS9:
1387                        ret_rate = MGN_MCS9;
1388                        break;
1389                case DESC90_RATEMCS10:
1390                        ret_rate = MGN_MCS10;
1391                        break;
1392                case DESC90_RATEMCS11:
1393                        ret_rate = MGN_MCS11;
1394                        break;
1395                case DESC90_RATEMCS12:
1396                        ret_rate = MGN_MCS12;
1397                        break;
1398                case DESC90_RATEMCS13:
1399                        ret_rate = MGN_MCS13;
1400                        break;
1401                case DESC90_RATEMCS14:
1402                        ret_rate = MGN_MCS14;
1403                        break;
1404                case DESC90_RATEMCS15:
1405                        ret_rate = MGN_MCS15;
1406                        break;
1407                case DESC90_RATEMCS32:
1408                        ret_rate = (0x80|0x20);
1409                        break;
1410
1411                default:
1412                        RT_TRACE(COMP_RECV, "HwRateToMRate90(): Non supported "
1413                                 "Rate [%x], bIsHT = %d!!!\n", rate, bIsHT);
1414                        break;
1415                }
1416        }
1417
1418        return ret_rate;
1419}
1420
1421static long rtl8192_signal_scale_mapping(struct r8192_priv *priv, long currsig)
1422{
1423        long retsig;
1424
1425        if (currsig >= 61 && currsig <= 100)
1426                retsig = 90 + ((currsig - 60) / 4);
1427        else if (currsig >= 41 && currsig <= 60)
1428                retsig = 78 + ((currsig - 40) / 2);
1429        else if (currsig >= 31 && currsig <= 40)
1430                retsig = 66 + (currsig - 30);
1431        else if (currsig >= 21 && currsig <= 30)
1432                retsig = 54 + (currsig - 20);
1433        else if (currsig >= 5 && currsig <= 20)
1434                retsig = 42 + (((currsig - 5) * 2) / 3);
1435        else if (currsig == 4)
1436                retsig = 36;
1437        else if (currsig == 3)
1438                retsig = 27;
1439        else if (currsig == 2)
1440                retsig = 18;
1441        else if (currsig == 1)
1442                retsig = 9;
1443        else
1444                retsig = currsig;
1445
1446        return retsig;
1447}
1448
1449
1450#define  rx_hal_is_cck_rate(_pdrvinfo)\
1451                        ((_pdrvinfo->RxRate == DESC90_RATE1M ||\
1452                        _pdrvinfo->RxRate == DESC90_RATE2M ||\
1453                        _pdrvinfo->RxRate == DESC90_RATE5_5M ||\
1454                        _pdrvinfo->RxRate == DESC90_RATE11M) &&\
1455                        !_pdrvinfo->RxHT)
1456
1457static void rtl8192_query_rxphystatus(
1458        struct r8192_priv *priv,
1459        struct rtllib_rx_stats *pstats,
1460        struct rx_desc  *pdesc,
1461        struct rx_fwinfo   *pdrvinfo,
1462        struct rtllib_rx_stats *precord_stats,
1463        bool bpacket_match_bssid,
1464        bool bpacket_toself,
1465        bool bPacketBeacon,
1466        bool bToSelfBA
1467        )
1468{
1469        struct phy_sts_ofdm_819xpci *pofdm_buf;
1470        struct phy_sts_cck_819xpci *pcck_buf;
1471        struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *prxsc;
1472        u8 *prxpkt;
1473        u8 i, max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg;
1474        char rx_pwr[4], rx_pwr_all = 0;
1475        char rx_snrX, rx_evmX;
1476        u8 evm, pwdb_all;
1477        u32 RSSI, total_rssi = 0;
1478        u8 is_cck_rate = 0;
1479        u8 rf_rx_num = 0;
1480        static  u8 check_reg824;
1481        static  u32 reg824_bit9;
1482
1483        priv->stats.numqry_phystatus++;
1484
1485        is_cck_rate = rx_hal_is_cck_rate(pdrvinfo);
1486        memset(precord_stats, 0, sizeof(struct rtllib_rx_stats));
1487        pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID =
1488                                    bpacket_match_bssid;
1489        pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself;
1490        pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate;
1491        pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon;
1492        pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA;
1493        if (check_reg824 == 0) {
1494                reg824_bit9 = rtl8192_QueryBBReg(priv->rtllib->dev,
1495                              rFPGA0_XA_HSSIParameter2, 0x200);
1496                check_reg824 = 1;
1497        }
1498
1499
1500        prxpkt = (u8 *)pdrvinfo;
1501
1502        prxpkt += sizeof(struct rx_fwinfo);
1503
1504        pcck_buf = (struct phy_sts_cck_819xpci *)prxpkt;
1505        pofdm_buf = (struct phy_sts_ofdm_819xpci *)prxpkt;
1506
1507        pstats->RxMIMOSignalQuality[0] = -1;
1508        pstats->RxMIMOSignalQuality[1] = -1;
1509        precord_stats->RxMIMOSignalQuality[0] = -1;
1510        precord_stats->RxMIMOSignalQuality[1] = -1;
1511
1512        if (is_cck_rate) {
1513                u8 report;
1514
1515                priv->stats.numqry_phystatusCCK++;
1516                if (!reg824_bit9) {
1517                        report = pcck_buf->cck_agc_rpt & 0xc0;
1518                        report = report>>6;
1519                        switch (report) {
1520                        case 0x3:
1521                                rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt &
1522                                             0x3e);
1523                                break;
1524                        case 0x2:
1525                                rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt &
1526                                             0x3e);
1527                                break;
1528                        case 0x1:
1529                                rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt &
1530                                             0x3e);
1531                                break;
1532                        case 0x0:
1533                                rx_pwr_all = 8 - (pcck_buf->cck_agc_rpt & 0x3e);
1534                                break;
1535                        }
1536                } else {
1537                        report = pcck_buf->cck_agc_rpt & 0x60;
1538                        report = report>>5;
1539                        switch (report) {
1540                        case 0x3:
1541                                rx_pwr_all = -35 -
1542                                        ((pcck_buf->cck_agc_rpt &
1543                                        0x1f) << 1);
1544                                break;
1545                        case 0x2:
1546                                rx_pwr_all = -23 -
1547                                        ((pcck_buf->cck_agc_rpt &
1548                                         0x1f) << 1);
1549                                break;
1550                        case 0x1:
1551                                rx_pwr_all = -11 -
1552                                         ((pcck_buf->cck_agc_rpt &
1553                                         0x1f) << 1);
1554                                break;
1555                        case 0x0:
1556                                rx_pwr_all = -8 -
1557                                         ((pcck_buf->cck_agc_rpt &
1558                                         0x1f) << 1);
1559                                break;
1560                        }
1561                }
1562
1563                pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);
1564                pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1565                pstats->RecvSignalPower = rx_pwr_all;
1566
1567                if (bpacket_match_bssid) {
1568                        u8      sq;
1569
1570                        if (pstats->RxPWDBAll > 40) {
1571                                sq = 100;
1572                        } else {
1573                                sq = pcck_buf->sq_rpt;
1574
1575                                if (pcck_buf->sq_rpt > 64)
1576                                        sq = 0;
1577                                else if (pcck_buf->sq_rpt < 20)
1578                                        sq = 100;
1579                                else
1580                                        sq = ((64-sq) * 100) / 44;
1581                        }
1582                        pstats->SignalQuality = sq;
1583                        precord_stats->SignalQuality = sq;
1584                        pstats->RxMIMOSignalQuality[0] = sq;
1585                        precord_stats->RxMIMOSignalQuality[0] = sq;
1586                        pstats->RxMIMOSignalQuality[1] = -1;
1587                        precord_stats->RxMIMOSignalQuality[1] = -1;
1588                }
1589        } else {
1590                priv->stats.numqry_phystatusHT++;
1591                for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
1592                        if (priv->brfpath_rxenable[i])
1593                                rf_rx_num++;
1594
1595                        rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i] & 0x3F) *
1596                                     2) - 110;
1597
1598                        tmp_rxsnr = pofdm_buf->rxsnr_X[i];
1599                        rx_snrX = (char)(tmp_rxsnr);
1600                        rx_snrX /= 2;
1601                        priv->stats.rxSNRdB[i] = (long)rx_snrX;
1602
1603                        RSSI = rtl819x_query_rxpwrpercentage(rx_pwr[i]);
1604                        if (priv->brfpath_rxenable[i])
1605                                total_rssi += RSSI;
1606
1607                        if (bpacket_match_bssid) {
1608                                pstats->RxMIMOSignalStrength[i] = (u8) RSSI;
1609                                precord_stats->RxMIMOSignalStrength[i] =
1610                                                                (u8) RSSI;
1611                        }
1612                }
1613
1614
1615                rx_pwr_all = (((pofdm_buf->pwdb_all) >> 1) & 0x7f) - 106;
1616                pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);
1617
1618                pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1619                pstats->RxPower = precord_stats->RxPower =      rx_pwr_all;
1620                pstats->RecvSignalPower = rx_pwr_all;
1621                if (pdrvinfo->RxHT && pdrvinfo->RxRate >= DESC90_RATEMCS8 &&
1622                    pdrvinfo->RxRate <= DESC90_RATEMCS15)
1623                        max_spatial_stream = 2;
1624                else
1625                        max_spatial_stream = 1;
1626
1627                for (i = 0; i < max_spatial_stream; i++) {
1628                        tmp_rxevm = pofdm_buf->rxevm_X[i];
1629                        rx_evmX = (char)(tmp_rxevm);
1630
1631                        rx_evmX /= 2;
1632
1633                        evm = rtl819x_evm_dbtopercentage(rx_evmX);
1634                        if (bpacket_match_bssid) {
1635                                if (i == 0) {
1636                                        pstats->SignalQuality = (u8)(evm &
1637                                                                 0xff);
1638                                        precord_stats->SignalQuality = (u8)(evm
1639                                                                        & 0xff);
1640                                }
1641                                pstats->RxMIMOSignalQuality[i] = (u8)(evm &
1642                                                                 0xff);
1643                                precord_stats->RxMIMOSignalQuality[i] = (u8)(evm
1644                                                                        & 0xff);
1645                        }
1646                }
1647
1648
1649                rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg;
1650                prxsc = (struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *)
1651                        &rxsc_sgien_exflg;
1652                if (pdrvinfo->BW)
1653                        priv->stats.received_bwtype[1+prxsc->rxsc]++;
1654                else
1655                        priv->stats.received_bwtype[0]++;
1656        }
1657
1658        if (is_cck_rate) {
1659                pstats->SignalStrength = precord_stats->SignalStrength =
1660                                         (u8)(rtl8192_signal_scale_mapping(priv,
1661                                         (long)pwdb_all));
1662
1663        } else {
1664                if (rf_rx_num != 0)
1665                        pstats->SignalStrength = precord_stats->SignalStrength =
1666                                         (u8)(rtl8192_signal_scale_mapping(priv,
1667                                         (long)(total_rssi /= rf_rx_num)));
1668        }
1669}
1670
1671static void rtl8192_process_phyinfo(struct r8192_priv *priv, u8 *buffer,
1672                                    struct rtllib_rx_stats *prev_st,
1673                                    struct rtllib_rx_stats *curr_st)
1674{
1675        bool bcheck = false;
1676        u8      rfpath;
1677        u32 ij, tmp_val;
1678        static u32 slide_rssi_index, slide_rssi_statistics;
1679        static u32 slide_evm_index, slide_evm_statistics;
1680        static u32 last_rssi, last_evm;
1681        static u32 slide_beacon_adc_pwdb_index;
1682        static u32 slide_beacon_adc_pwdb_statistics;
1683        static u32 last_beacon_adc_pwdb;
1684        struct rtllib_hdr_3addr *hdr;
1685        u16 sc;
1686        unsigned int frag, seq;
1687
1688        hdr = (struct rtllib_hdr_3addr *)buffer;
1689        sc = le16_to_cpu(hdr->seq_ctl);
1690        frag = WLAN_GET_SEQ_FRAG(sc);
1691        seq = WLAN_GET_SEQ_SEQ(sc);
1692        curr_st->Seq_Num = seq;
1693        if (!prev_st->bIsAMPDU)
1694                bcheck = true;
1695
1696        if (slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1697                slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX;
1698                last_rssi = priv->stats.slide_signal_strength[slide_rssi_index];
1699                priv->stats.slide_rssi_total -= last_rssi;
1700        }
1701        priv->stats.slide_rssi_total += prev_st->SignalStrength;
1702
1703        priv->stats.slide_signal_strength[slide_rssi_index++] =
1704                                         prev_st->SignalStrength;
1705        if (slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX)
1706                slide_rssi_index = 0;
1707
1708        tmp_val = priv->stats.slide_rssi_total/slide_rssi_statistics;
1709        priv->stats.signal_strength = rtl819x_translate_todbm(priv,
1710                                      (u8)tmp_val);
1711        curr_st->rssi = priv->stats.signal_strength;
1712        if (!prev_st->bPacketMatchBSSID) {
1713                if (!prev_st->bToSelfBA)
1714                        return;
1715        }
1716
1717        if (!bcheck)
1718                return;
1719
1720        rtl819x_process_cck_rxpathsel(priv, prev_st);
1721
1722        priv->stats.num_process_phyinfo++;
1723        if (!prev_st->bIsCCK && prev_st->bPacketToSelf) {
1724                for (rfpath = RF90_PATH_A; rfpath < RF90_PATH_C; rfpath++) {
1725                        if (!rtl8192_phy_CheckIsLegalRFPath(priv->rtllib->dev,
1726                            rfpath))
1727                                continue;
1728                        RT_TRACE(COMP_DBG, "Jacken -> pPreviousstats->RxMIMO"
1729                                 "SignalStrength[rfpath]  = %d\n",
1730                                 prev_st->RxMIMOSignalStrength[rfpath]);
1731                        if (priv->stats.rx_rssi_percentage[rfpath] == 0) {
1732                                priv->stats.rx_rssi_percentage[rfpath] =
1733                                         prev_st->RxMIMOSignalStrength[rfpath];
1734                        }
1735                        if (prev_st->RxMIMOSignalStrength[rfpath]  >
1736                            priv->stats.rx_rssi_percentage[rfpath]) {
1737                                priv->stats.rx_rssi_percentage[rfpath] =
1738                                        ((priv->stats.rx_rssi_percentage[rfpath]
1739                                        * (RX_SMOOTH - 1)) +
1740                                        (prev_st->RxMIMOSignalStrength
1741                                        [rfpath])) / (RX_SMOOTH);
1742                                priv->stats.rx_rssi_percentage[rfpath] =
1743                                         priv->stats.rx_rssi_percentage[rfpath]
1744                                         + 1;
1745                        } else {
1746                                priv->stats.rx_rssi_percentage[rfpath] =
1747                                   ((priv->stats.rx_rssi_percentage[rfpath] *
1748                                   (RX_SMOOTH-1)) +
1749                                   (prev_st->RxMIMOSignalStrength[rfpath])) /
1750                                   (RX_SMOOTH);
1751                        }
1752                        RT_TRACE(COMP_DBG, "Jacken -> priv->RxStats.RxRSSI"
1753                                 "Percentage[rfPath]  = %d\n",
1754                                 priv->stats.rx_rssi_percentage[rfpath]);
1755                }
1756        }
1757
1758
1759        if (prev_st->bPacketBeacon) {
1760                if (slide_beacon_adc_pwdb_statistics++ >=
1761                    PHY_Beacon_RSSI_SLID_WIN_MAX) {
1762                        slide_beacon_adc_pwdb_statistics =
1763                                         PHY_Beacon_RSSI_SLID_WIN_MAX;
1764                        last_beacon_adc_pwdb = priv->stats.Slide_Beacon_pwdb
1765                                               [slide_beacon_adc_pwdb_index];
1766                        priv->stats.Slide_Beacon_Total -= last_beacon_adc_pwdb;
1767                }
1768                priv->stats.Slide_Beacon_Total += prev_st->RxPWDBAll;
1769                priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index] =
1770                                                         prev_st->RxPWDBAll;
1771                slide_beacon_adc_pwdb_index++;
1772                if (slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX)
1773                        slide_beacon_adc_pwdb_index = 0;
1774                prev_st->RxPWDBAll = priv->stats.Slide_Beacon_Total /
1775                                     slide_beacon_adc_pwdb_statistics;
1776                if (prev_st->RxPWDBAll >= 3)
1777                        prev_st->RxPWDBAll -= 3;
1778        }
1779
1780        RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n",
1781                                prev_st->bIsCCK ? "CCK" : "OFDM",
1782                                prev_st->RxPWDBAll);
1783
1784        if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1785            prev_st->bToSelfBA) {
1786                if (priv->undecorated_smoothed_pwdb < 0)
1787                        priv->undecorated_smoothed_pwdb = prev_st->RxPWDBAll;
1788                if (prev_st->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb) {
1789                        priv->undecorated_smoothed_pwdb =
1790                                        (((priv->undecorated_smoothed_pwdb) *
1791                                        (RX_SMOOTH-1)) +
1792                                        (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1793                        priv->undecorated_smoothed_pwdb =
1794                                         priv->undecorated_smoothed_pwdb + 1;
1795                } else {
1796                        priv->undecorated_smoothed_pwdb =
1797                                        (((priv->undecorated_smoothed_pwdb) *
1798                                        (RX_SMOOTH-1)) +
1799                                        (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1800                }
1801                rtl819x_update_rxsignalstatistics8190pci(priv, prev_st);
1802        }
1803
1804        if (prev_st->SignalQuality != 0) {
1805                if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1806                    prev_st->bToSelfBA) {
1807                        if (slide_evm_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1808                                slide_evm_statistics = PHY_RSSI_SLID_WIN_MAX;
1809                                last_evm =
1810                                         priv->stats.slide_evm[slide_evm_index];
1811                                priv->stats.slide_evm_total -= last_evm;
1812                        }
1813
1814                        priv->stats.slide_evm_total += prev_st->SignalQuality;
1815
1816                        priv->stats.slide_evm[slide_evm_index++] =
1817                                                 prev_st->SignalQuality;
1818                        if (slide_evm_index >= PHY_RSSI_SLID_WIN_MAX)
1819                                slide_evm_index = 0;
1820
1821                        tmp_val = priv->stats.slide_evm_total /
1822                                  slide_evm_statistics;
1823                        priv->stats.signal_quality = tmp_val;
1824                        priv->stats.last_signal_strength_inpercent = tmp_val;
1825                }
1826
1827                if (prev_st->bPacketToSelf ||
1828                    prev_st->bPacketBeacon ||
1829                    prev_st->bToSelfBA) {
1830                        for (ij = 0; ij < 2; ij++) {
1831                                if (prev_st->RxMIMOSignalQuality[ij] != -1) {
1832                                        if (priv->stats.rx_evm_percentage[ij] == 0)
1833                                                priv->stats.rx_evm_percentage[ij] =
1834                                                   prev_st->RxMIMOSignalQuality[ij];
1835                                        priv->stats.rx_evm_percentage[ij] =
1836                                          ((priv->stats.rx_evm_percentage[ij] *
1837                                          (RX_SMOOTH - 1)) +
1838                                          (prev_st->RxMIMOSignalQuality[ij])) /
1839                                          (RX_SMOOTH);
1840                                }
1841                        }
1842                }
1843        }
1844}
1845
1846static void rtl8192_TranslateRxSignalStuff(struct net_device *dev,
1847                                           struct sk_buff *skb,
1848                                           struct rtllib_rx_stats *pstats,
1849                                           struct rx_desc *pdesc,
1850                                           struct rx_fwinfo *pdrvinfo)
1851{
1852        struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1853        bool bpacket_match_bssid, bpacket_toself;
1854        bool bPacketBeacon = false;
1855        struct rtllib_hdr_3addr *hdr;
1856        bool bToSelfBA = false;
1857        static struct rtllib_rx_stats  previous_stats;
1858        u16 fc, type;
1859        u8 *tmp_buf;
1860        u8 *praddr;
1861
1862        tmp_buf = skb->data + pstats->RxDrvInfoSize + pstats->RxBufShift;
1863
1864        hdr = (struct rtllib_hdr_3addr *)tmp_buf;
1865        fc = le16_to_cpu(hdr->frame_ctl);
1866        type = WLAN_FC_GET_TYPE(fc);
1867        praddr = hdr->addr1;
1868
1869        bpacket_match_bssid = ((RTLLIB_FTYPE_CTL != type) &&
1870                        (!compare_ether_addr(priv->rtllib->
1871                        current_network.bssid,
1872                           (fc & RTLLIB_FCTL_TODS) ? hdr->addr1 :
1873                           (fc & RTLLIB_FCTL_FROMDS) ? hdr->addr2 : hdr->addr3))
1874                && (!pstats->bHwError) && (!pstats->bCRC) && (!pstats->bICV));
1875        bpacket_toself =  bpacket_match_bssid &&        /* check this */
1876                          (!compare_ether_addr(praddr,
1877                          priv->rtllib->dev->dev_addr));
1878        if (WLAN_FC_GET_FRAMETYPE(fc) == RTLLIB_STYPE_BEACON)
1879                bPacketBeacon = true;
1880        if (bpacket_match_bssid)
1881                priv->stats.numpacket_matchbssid++;
1882        if (bpacket_toself)
1883                priv->stats.numpacket_toself++;
1884        rtl8192_process_phyinfo(priv, tmp_buf, &previous_stats, pstats);
1885        rtl8192_query_rxphystatus(priv, pstats, pdesc, pdrvinfo,
1886                                  &previous_stats, bpacket_match_bssid,
1887                                  bpacket_toself, bPacketBeacon, bToSelfBA);
1888        rtl8192_record_rxdesc_forlateruse(pstats, &previous_stats);
1889}
1890
1891static void rtl8192_UpdateReceivedRateHistogramStatistics(
1892                                           struct net_device *dev,
1893                                           struct rtllib_rx_stats *pstats)
1894{
1895        struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1896        u32 rcvType = 1;
1897        u32 rateIndex;
1898        u32 preamble_guardinterval;
1899
1900        if (pstats->bCRC)
1901                rcvType = 2;
1902        else if (pstats->bICV)
1903                rcvType = 3;
1904
1905        if (pstats->bShortPreamble)
1906                preamble_guardinterval = 1;
1907        else
1908                preamble_guardinterval = 0;
1909
1910        switch (pstats->rate) {
1911        case MGN_1M:
1912                rateIndex = 0;
1913                break;
1914        case MGN_2M:
1915                rateIndex = 1;
1916                 break;
1917        case MGN_5_5M:
1918                rateIndex = 2;
1919                break;
1920        case MGN_11M:
1921                rateIndex = 3;
1922                break;
1923        case MGN_6M:
1924                rateIndex = 4;
1925                break;
1926        case MGN_9M:
1927                rateIndex = 5;
1928                break;
1929        case MGN_12M:
1930                rateIndex = 6;
1931                break;
1932        case MGN_18M:
1933                rateIndex = 7;
1934                 break;
1935        case MGN_24M:
1936                rateIndex = 8;
1937                break;
1938        case MGN_36M:
1939                rateIndex = 9;
1940                break;
1941        case MGN_48M:
1942                rateIndex = 10;
1943                break;
1944        case MGN_54M:
1945                rateIndex = 11;
1946                break;
1947        case MGN_MCS0:
1948                rateIndex = 12;
1949                break;
1950        case MGN_MCS1:
1951                rateIndex = 13;
1952                break;
1953        case MGN_MCS2:
1954                rateIndex = 14;
1955                break;
1956        case MGN_MCS3:
1957                rateIndex = 15;
1958                break;
1959        case MGN_MCS4:
1960                rateIndex = 16;
1961                break;
1962        case MGN_MCS5:
1963                rateIndex = 17;
1964                break;
1965        case MGN_MCS6:
1966                rateIndex = 18;
1967                break;
1968        case MGN_MCS7:
1969                rateIndex = 19;
1970                break;
1971        case MGN_MCS8:
1972                rateIndex = 20;
1973                break;
1974        case MGN_MCS9:
1975                rateIndex = 21;
1976                break;
1977        case MGN_MCS10:
1978                rateIndex = 22;
1979                break;
1980        case MGN_MCS11:
1981                rateIndex = 23;
1982                break;
1983        case MGN_MCS12:
1984                rateIndex = 24;
1985                break;
1986        case MGN_MCS13:
1987                rateIndex = 25;
1988                break;
1989        case MGN_MCS14:
1990                rateIndex = 26;
1991                break;
1992        case MGN_MCS15:
1993                rateIndex = 27;
1994                break;
1995        default:
1996                rateIndex = 28;
1997                break;
1998        }
1999        priv->stats.received_preamble_GI[preamble_guardinterval][rateIndex]++;
2000        priv->stats.received_rate_histogram[0][rateIndex]++;
2001        priv->stats.received_rate_histogram[rcvType][rateIndex]++;
2002}
2003
2004bool rtl8192_rx_query_status_desc(struct net_device *dev,
2005                                  struct rtllib_rx_stats *stats,
2006                                  struct rx_desc *pdesc,
2007                                  struct sk_buff *skb)
2008{
2009        struct r8192_priv *priv = rtllib_priv(dev);
2010
2011        stats->bICV = pdesc->ICV;
2012        stats->bCRC = pdesc->CRC32;
2013        stats->bHwError = pdesc->CRC32 | pdesc->ICV;
2014
2015        stats->Length = pdesc->Length;
2016        if (stats->Length < 24)
2017                stats->bHwError |= 1;
2018
2019        if (stats->bHwError) {
2020                stats->bShift = false;
2021
2022                if (pdesc->CRC32) {
2023                        if (pdesc->Length < 500)
2024                                priv->stats.rxcrcerrmin++;
2025                        else if (pdesc->Length > 1000)
2026                                priv->stats.rxcrcerrmax++;
2027                        else
2028                                priv->stats.rxcrcerrmid++;
2029                }
2030                return false;
2031        } else {
2032                struct rx_fwinfo *pDrvInfo = NULL;
2033                stats->RxDrvInfoSize = pdesc->RxDrvInfoSize;
2034                stats->RxBufShift = ((pdesc->Shift)&0x03);
2035                stats->Decrypted = !pdesc->SWDec;
2036
2037                pDrvInfo = (struct rx_fwinfo *)(skb->data + stats->RxBufShift);
2038
2039                stats->rate = HwRateToMRate90((bool)pDrvInfo->RxHT,
2040                                             (u8)pDrvInfo->RxRate);
2041                stats->bShortPreamble = pDrvInfo->SPLCP;
2042
2043                rtl8192_UpdateReceivedRateHistogramStatistics(dev, stats);
2044
2045                stats->bIsAMPDU = (pDrvInfo->PartAggr == 1);
2046                stats->bFirstMPDU = (pDrvInfo->PartAggr == 1) &&
2047                                    (pDrvInfo->FirstAGGR == 1);
2048
2049                stats->TimeStampLow = pDrvInfo->TSFL;
2050                stats->TimeStampHigh = read_nic_dword(dev, TSFR+4);
2051
2052                rtl819x_UpdateRxPktTimeStamp(dev, stats);
2053
2054                if ((stats->RxBufShift + stats->RxDrvInfoSize) > 0)
2055                        stats->bShift = 1;
2056
2057                stats->RxIs40MHzPacket = pDrvInfo->BW;
2058
2059                rtl8192_TranslateRxSignalStuff(dev, skb, stats, pdesc,
2060                                               pDrvInfo);
2061
2062                if (pDrvInfo->FirstAGGR == 1 || pDrvInfo->PartAggr == 1)
2063                        RT_TRACE(COMP_RXDESC, "pDrvInfo->FirstAGGR = %d,"
2064                                 " pDrvInfo->PartAggr = %d\n",
2065                                 pDrvInfo->FirstAGGR, pDrvInfo->PartAggr);
2066                skb_trim(skb, skb->len - 4/*sCrcLng*/);
2067
2068
2069                stats->packetlength = stats->Length-4;
2070                stats->fraglength = stats->packetlength;
2071                stats->fragoffset = 0;
2072                stats->ntotalfrag = 1;
2073                return true;
2074        }
2075}
2076
2077void rtl8192_halt_adapter(struct net_device *dev, bool reset)
2078{
2079        struct r8192_priv *priv = rtllib_priv(dev);
2080        int i;
2081        u8      OpMode;
2082        u8      u1bTmp;
2083        u32     ulRegRead;
2084
2085        OpMode = RT_OP_MODE_NO_LINK;
2086        priv->rtllib->SetHwRegHandler(dev, HW_VAR_MEDIA_STATUS, &OpMode);
2087
2088        if (!priv->rtllib->bSupportRemoteWakeUp) {
2089                u1bTmp = 0x0;
2090                write_nic_byte(dev, CMDR, u1bTmp);
2091        }
2092
2093        mdelay(20);
2094
2095        if (!reset) {
2096                mdelay(150);
2097
2098                priv->bHwRfOffAction = 2;
2099
2100                if (!priv->rtllib->bSupportRemoteWakeUp) {
2101                        PHY_SetRtl8192eRfOff(dev);
2102                        ulRegRead = read_nic_dword(dev, CPU_GEN);
2103                        ulRegRead |= CPU_GEN_SYSTEM_RESET;
2104                        write_nic_dword(dev, CPU_GEN, ulRegRead);
2105                } else {
2106                        write_nic_dword(dev, WFCRC0, 0xffffffff);
2107                        write_nic_dword(dev, WFCRC1, 0xffffffff);
2108                        write_nic_dword(dev, WFCRC2, 0xffffffff);
2109
2110
2111                        write_nic_byte(dev, PMR, 0x5);
2112                        write_nic_byte(dev, MacBlkCtrl, 0xa);
2113                }
2114        }
2115
2116        for (i = 0; i < MAX_QUEUE_SIZE; i++)
2117                skb_queue_purge(&priv->rtllib->skb_waitQ[i]);
2118        for (i = 0; i < MAX_QUEUE_SIZE; i++)
2119                skb_queue_purge(&priv->rtllib->skb_aggQ[i]);
2120
2121        skb_queue_purge(&priv->skb_queue);
2122        return;
2123}
2124
2125void rtl8192_update_ratr_table(struct net_device *dev)
2126{
2127        struct r8192_priv *priv = rtllib_priv(dev);
2128        struct rtllib_device *ieee = priv->rtllib;
2129        u8 *pMcsRate = ieee->dot11HTOperationalRateSet;
2130        u32 ratr_value = 0;
2131        u8 rate_index = 0;
2132
2133        rtl8192_config_rate(dev, (u16 *)(&ratr_value));
2134        ratr_value |= (*(u16 *)(pMcsRate)) << 12;
2135        switch (ieee->mode) {
2136        case IEEE_A:
2137                ratr_value &= 0x00000FF0;
2138                break;
2139        case IEEE_B:
2140                ratr_value &= 0x0000000F;
2141                break;
2142        case IEEE_G:
2143        case IEEE_G|IEEE_B:
2144                ratr_value &= 0x00000FF7;
2145                break;
2146        case IEEE_N_24G:
2147        case IEEE_N_5G:
2148                if (ieee->pHTInfo->PeerMimoPs == 0) {
2149                        ratr_value &= 0x0007F007;
2150                } else {
2151                        if (priv->rf_type == RF_1T2R)
2152                                ratr_value &= 0x000FF007;
2153                        else
2154                                ratr_value &= 0x0F81F007;
2155                }
2156                break;
2157        default:
2158                break;
2159        }
2160        ratr_value &= 0x0FFFFFFF;
2161        if (ieee->pHTInfo->bCurTxBW40MHz &&
2162            ieee->pHTInfo->bCurShortGI40MHz)
2163                ratr_value |= 0x80000000;
2164        else if (!ieee->pHTInfo->bCurTxBW40MHz &&
2165                  ieee->pHTInfo->bCurShortGI20MHz)
2166                ratr_value |= 0x80000000;
2167        write_nic_dword(dev, RATR0+rate_index*4, ratr_value);
2168        write_nic_byte(dev, UFWP, 1);
2169}
2170
2171void
2172rtl8192_InitializeVariables(struct net_device  *dev)
2173{
2174        struct r8192_priv *priv = rtllib_priv(dev);
2175
2176        strcpy(priv->nick, "rtl8192E");
2177
2178        priv->rtllib->softmac_features  = IEEE_SOFTMAC_SCAN |
2179                IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ |
2180                IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE /* |
2181                IEEE_SOFTMAC_BEACONS*/;
2182
2183        priv->rtllib->tx_headroom = sizeof(struct tx_fwinfo_8190pci);
2184
2185        priv->ShortRetryLimit = 0x30;
2186        priv->LongRetryLimit = 0x30;
2187
2188        priv->EarlyRxThreshold = 7;
2189        priv->pwrGroupCnt = 0;
2190
2191        priv->bIgnoreSilentReset = false;
2192        priv->enable_gpio0 = 0;
2193
2194        priv->TransmitConfig = 0;
2195
2196        priv->ReceiveConfig = RCR_ADD3  |
2197                RCR_AMF | RCR_ADF |
2198                RCR_AICV |
2199                RCR_AB | RCR_AM | RCR_APM |
2200                RCR_AAP | ((u32)7<<RCR_MXDMA_OFFSET) |
2201                ((u32)7 << RCR_FIFO_OFFSET) | RCR_ONLYERLPKT;
2202
2203        priv->irq_mask[0] = (u32)(IMR_ROK | IMR_VODOK | IMR_VIDOK |
2204                            IMR_BEDOK | IMR_BKDOK | IMR_HCCADOK |
2205                            IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK |
2206                            IMR_BDOK | IMR_RXCMDOK | IMR_TIMEOUT0 |
2207                            IMR_RDU | IMR_RXFOVW | IMR_TXFOVW |
2208                            IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
2209
2210
2211        priv->MidHighPwrTHR_L1 = 0x3B;
2212        priv->MidHighPwrTHR_L2 = 0x40;
2213        priv->PwrDomainProtect = false;
2214
2215        priv->bfirst_after_down = 0;
2216}
2217
2218void rtl8192_EnableInterrupt(struct net_device *dev)
2219{
2220        struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2221        priv->irq_enabled = 1;
2222
2223        write_nic_dword(dev, INTA_MASK, priv->irq_mask[0]);
2224
2225}
2226
2227void rtl8192_DisableInterrupt(struct net_device *dev)
2228{
2229        struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2230
2231        write_nic_dword(dev, INTA_MASK, 0);
2232
2233        priv->irq_enabled = 0;
2234}
2235
2236void rtl8192_ClearInterrupt(struct net_device *dev)
2237{
2238        u32 tmp = 0;
2239        tmp = read_nic_dword(dev, ISR);
2240        write_nic_dword(dev, ISR, tmp);
2241}
2242
2243
2244void rtl8192_enable_rx(struct net_device *dev)
2245{
2246        struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2247        write_nic_dword(dev, RDQDA, priv->rx_ring_dma[RX_MPDU_QUEUE]);
2248}
2249
2250static const u32 TX_DESC_BASE[] = {
2251        BKQDA, BEQDA, VIQDA, VOQDA, HCCAQDA, CQDA, MQDA, HQDA, BQDA
2252};
2253
2254void rtl8192_enable_tx(struct net_device *dev)
2255{
2256        struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2257        u32 i;
2258
2259        for (i = 0; i < MAX_TX_QUEUE_COUNT; i++)
2260                write_nic_dword(dev, TX_DESC_BASE[i], priv->tx_ring[i].dma);
2261}
2262
2263
2264void rtl8192_interrupt_recognized(struct net_device *dev, u32 *p_inta,
2265                                  u32 *p_intb)
2266{
2267        *p_inta = read_nic_dword(dev, ISR);
2268        write_nic_dword(dev, ISR, *p_inta);
2269}
2270
2271bool rtl8192_HalRxCheckStuck(struct net_device *dev)
2272{
2273        struct r8192_priv *priv = rtllib_priv(dev);
2274        u16               RegRxCounter = read_nic_word(dev, 0x130);
2275        bool              bStuck = false;
2276        static u8         rx_chk_cnt;
2277        u32             SlotIndex = 0, TotalRxStuckCount = 0;
2278        u8              i;
2279        u8              SilentResetRxSoltNum = 4;
2280
2281        RT_TRACE(COMP_RESET, "%s(): RegRxCounter is %d, RxCounter is %d\n",
2282                 __func__, RegRxCounter, priv->RxCounter);
2283
2284        rx_chk_cnt++;
2285        if (priv->undecorated_smoothed_pwdb >= (RateAdaptiveTH_High+5)) {
2286                rx_chk_cnt = 0;
2287        } else if ((priv->undecorated_smoothed_pwdb < (RateAdaptiveTH_High + 5))
2288          && (((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) &&
2289          (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_40M))
2290          || ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) &&
2291          (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_20M)))) {
2292                if (rx_chk_cnt < 2)
2293                        return bStuck;
2294                else
2295                        rx_chk_cnt = 0;
2296        } else if ((((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) &&
2297                  (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_40M)) ||
2298                ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) &&
2299                 (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_20M))) &&
2300                priv->undecorated_smoothed_pwdb >= VeryLowRSSI) {
2301                if (rx_chk_cnt < 4)
2302                        return bStuck;
2303                else
2304                        rx_chk_cnt = 0;
2305        } else {
2306                if (rx_chk_cnt < 8)
2307                        return bStuck;
2308                else
2309                        rx_chk_cnt = 0;
2310        }
2311
2312
2313        SlotIndex = (priv->SilentResetRxSlotIndex++)%SilentResetRxSoltNum;
2314
2315        if (priv->RxCounter == RegRxCounter) {
2316                priv->SilentResetRxStuckEvent[SlotIndex] = 1;
2317
2318                for (i = 0; i < SilentResetRxSoltNum; i++)
2319                        TotalRxStuckCount += priv->SilentResetRxStuckEvent[i];
2320
2321                if (TotalRxStuckCount == SilentResetRxSoltNum) {
2322                        bStuck = true;
2323                        for (i = 0; i < SilentResetRxSoltNum; i++)
2324                                TotalRxStuckCount +=
2325                                         priv->SilentResetRxStuckEvent[i];
2326                }
2327
2328
2329        } else {
2330                priv->SilentResetRxStuckEvent[SlotIndex] = 0;
2331        }
2332
2333        priv->RxCounter = RegRxCounter;
2334
2335        return bStuck;
2336}
2337
2338bool rtl8192_HalTxCheckStuck(struct net_device *dev)
2339{
2340        struct r8192_priv *priv = rtllib_priv(dev);
2341        bool    bStuck = false;
2342        u16     RegTxCounter = read_nic_word(dev, 0x128);
2343
2344        RT_TRACE(COMP_RESET, "%s():RegTxCounter is %d,TxCounter is %d\n",
2345                 __func__, RegTxCounter, priv->TxCounter);
2346
2347        if (priv->TxCounter == RegTxCounter)
2348                bStuck = true;
2349
2350        priv->TxCounter = RegTxCounter;
2351
2352        return bStuck;
2353}
2354
2355bool rtl8192_GetNmodeSupportBySecCfg(struct net_device *dev)
2356{
2357        struct r8192_priv *priv = rtllib_priv(dev);
2358        struct rtllib_device *ieee = priv->rtllib;
2359        if (ieee->rtllib_ap_sec_type &&
2360           (ieee->rtllib_ap_sec_type(priv->rtllib)&(SEC_ALG_WEP |
2361                                     SEC_ALG_TKIP))) {
2362                return false;
2363        } else {
2364                return true;
2365        }
2366}
2367
2368bool rtl8192_GetHalfNmodeSupportByAPs(struct net_device *dev)
2369{
2370        bool Reval;
2371        struct r8192_priv *priv = rtllib_priv(dev);
2372        struct rtllib_device *ieee = priv->rtllib;
2373
2374        if (ieee->bHalfWirelessN24GMode == true)
2375                Reval = true;
2376        else
2377                Reval =  false;
2378
2379        return Reval;
2380}
2381
2382u8 rtl8192_QueryIsShort(u8 TxHT, u8 TxRate, struct cb_desc *tcb_desc)
2383{
2384        u8   tmp_Short;
2385
2386        tmp_Short = (TxHT == 1) ? ((tcb_desc->bUseShortGI) ? 1 : 0) :
2387                        ((tcb_desc->bUseShortPreamble) ? 1 : 0);
2388        if (TxHT == 1 && TxRate != DESC90_RATEMCS15)
2389                tmp_Short = 0;
2390
2391        return tmp_Short;
2392}
2393
2394void ActUpdateChannelAccessSetting(struct net_device *dev,
2395        enum wireless_mode WirelessMode,
2396        struct channel_access_setting *ChnlAccessSetting)
2397{
2398        return;
2399}
2400