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20#include "rtl_core.h"
21#include "r8192E_hw.h"
22#include "r8192E_phyreg.h"
23#include "r8190P_rtl8256.h"
24#include "r8192E_phy.h"
25#include "rtl_dm.h"
26
27#include "r8192E_hwimg.h"
28
29static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
30 0,
31 0x085c,
32 0x08dc,
33 0x095c,
34 0x09dc,
35 0x0a5c,
36 0x0adc,
37 0x0b5c,
38 0x0bdc,
39 0x0c5c,
40 0x0cdc,
41 0x0d5c,
42 0x0ddc,
43 0x0e5c,
44 0x0f72,
45};
46
47
48
49static u32 phy_FwRFSerialRead(struct net_device *dev,
50 enum rf90_radio_path eRFPath,
51 u32 Offset);
52static void phy_FwRFSerialWrite(struct net_device *dev,
53 enum rf90_radio_path eRFPath,
54 u32 Offset, u32 Data);
55
56static u32 rtl8192_CalculateBitShift(u32 dwBitMask)
57{
58 u32 i;
59 for (i = 0; i <= 31; i++) {
60 if (((dwBitMask >> i) & 0x1) == 1)
61 break;
62 }
63 return i;
64}
65
66u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath)
67{
68 u8 ret = 1;
69 struct r8192_priv *priv = rtllib_priv(dev);
70 if (priv->rf_type == RF_2T4R)
71 ret = 0;
72 else if (priv->rf_type == RF_1T2R) {
73 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
74 ret = 1;
75 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
76 ret = 0;
77 }
78 return ret;
79}
80
81void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask,
82 u32 dwData)
83{
84
85 u32 OriginalValue, BitShift, NewValue;
86
87 if (dwBitMask != bMaskDWord) {
88 OriginalValue = read_nic_dword(dev, dwRegAddr);
89 BitShift = rtl8192_CalculateBitShift(dwBitMask);
90 NewValue = (((OriginalValue) & (~dwBitMask)) |
91 (dwData << BitShift));
92 write_nic_dword(dev, dwRegAddr, NewValue);
93 } else
94 write_nic_dword(dev, dwRegAddr, dwData);
95 return;
96}
97
98u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask)
99{
100 u32 Ret = 0, OriginalValue, BitShift;
101
102 OriginalValue = read_nic_dword(dev, dwRegAddr);
103 BitShift = rtl8192_CalculateBitShift(dwBitMask);
104 Ret = (OriginalValue & dwBitMask) >> BitShift;
105
106 return Ret;
107}
108static u32 rtl8192_phy_RFSerialRead(struct net_device *dev,
109 enum rf90_radio_path eRFPath, u32 Offset)
110{
111 struct r8192_priv *priv = rtllib_priv(dev);
112 u32 ret = 0;
113 u32 NewOffset = 0;
114 struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath];
115 Offset &= 0x3f;
116
117 if (priv->rf_chip == RF_8256) {
118 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
119 if (Offset >= 31) {
120 priv->RfReg0Value[eRFPath] |= 0x140;
121 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
122 bMaskDWord,
123 (priv->RfReg0Value[eRFPath]<<16));
124 NewOffset = Offset - 30;
125 } else if (Offset >= 16) {
126 priv->RfReg0Value[eRFPath] |= 0x100;
127 priv->RfReg0Value[eRFPath] &= (~0x40);
128 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
129 bMaskDWord,
130 (priv->RfReg0Value[eRFPath]<<16));
131
132 NewOffset = Offset - 15;
133 } else
134 NewOffset = Offset;
135 } else {
136 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need"
137 " to be 8256\n");
138 NewOffset = Offset;
139 }
140 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
141 NewOffset);
142 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
143 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
144
145 mdelay(1);
146
147 ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack,
148 bLSSIReadBackData);
149
150 if (priv->rf_chip == RF_8256) {
151 priv->RfReg0Value[eRFPath] &= 0xebf;
152
153 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
154 (priv->RfReg0Value[eRFPath] << 16));
155
156 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
157 }
158
159
160 return ret;
161
162}
163
164static void rtl8192_phy_RFSerialWrite(struct net_device *dev,
165 enum rf90_radio_path eRFPath, u32 Offset,
166 u32 Data)
167{
168 struct r8192_priv *priv = rtllib_priv(dev);
169 u32 DataAndAddr = 0, NewOffset = 0;
170 struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath];
171
172 Offset &= 0x3f;
173 if (priv->rf_chip == RF_8256) {
174 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
175
176 if (Offset >= 31) {
177 priv->RfReg0Value[eRFPath] |= 0x140;
178 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
179 bMaskDWord,
180 (priv->RfReg0Value[eRFPath] << 16));
181 NewOffset = Offset - 30;
182 } else if (Offset >= 16) {
183 priv->RfReg0Value[eRFPath] |= 0x100;
184 priv->RfReg0Value[eRFPath] &= (~0x40);
185 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
186 bMaskDWord,
187 (priv->RfReg0Value[eRFPath] << 16));
188 NewOffset = Offset - 15;
189 } else
190 NewOffset = Offset;
191 } else {
192 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be"
193 " 8256\n");
194 NewOffset = Offset;
195 }
196
197 DataAndAddr = (Data<<16) | (NewOffset&0x3f);
198
199 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
200
201 if (Offset == 0x0)
202 priv->RfReg0Value[eRFPath] = Data;
203
204 if (priv->rf_chip == RF_8256) {
205 if (Offset != 0) {
206 priv->RfReg0Value[eRFPath] &= 0xebf;
207 rtl8192_setBBreg(
208 dev,
209 pPhyReg->rf3wireOffset,
210 bMaskDWord,
211 (priv->RfReg0Value[eRFPath] << 16));
212 }
213 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
214 }
215 return;
216}
217
218void rtl8192_phy_SetRFReg(struct net_device *dev, enum rf90_radio_path eRFPath,
219 u32 RegAddr, u32 BitMask, u32 Data)
220{
221 struct r8192_priv *priv = rtllib_priv(dev);
222 u32 Original_Value, BitShift, New_Value;
223
224 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
225 return;
226 if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter)
227 return;
228
229 RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n");
230 if (priv->Rf_Mode == RF_OP_By_FW) {
231 if (BitMask != bMask12Bits) {
232 Original_Value = phy_FwRFSerialRead(dev, eRFPath,
233 RegAddr);
234 BitShift = rtl8192_CalculateBitShift(BitMask);
235 New_Value = (((Original_Value) & (~BitMask)) |
236 (Data << BitShift));
237
238 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
239 } else
240 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
241 udelay(200);
242
243 } else {
244 if (BitMask != bMask12Bits) {
245 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath,
246 RegAddr);
247 BitShift = rtl8192_CalculateBitShift(BitMask);
248 New_Value = (((Original_Value) & (~BitMask)) |
249 (Data << BitShift));
250
251 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr,
252 New_Value);
253 } else
254 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
255 }
256 return;
257}
258
259u32 rtl8192_phy_QueryRFReg(struct net_device *dev, enum rf90_radio_path eRFPath,
260 u32 RegAddr, u32 BitMask)
261{
262 u32 Original_Value, Readback_Value, BitShift;
263 struct r8192_priv *priv = rtllib_priv(dev);
264 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
265 return 0;
266 if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter)
267 return 0;
268 down(&priv->rf_sem);
269 if (priv->Rf_Mode == RF_OP_By_FW) {
270 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
271 udelay(200);
272 } else {
273 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath,
274 RegAddr);
275 }
276 BitShift = rtl8192_CalculateBitShift(BitMask);
277 Readback_Value = (Original_Value & BitMask) >> BitShift;
278 up(&priv->rf_sem);
279 return Readback_Value;
280}
281
282static u32 phy_FwRFSerialRead(struct net_device *dev,
283 enum rf90_radio_path eRFPath, u32 Offset)
284{
285 u32 retValue = 0;
286 u32 Data = 0;
287 u8 time = 0;
288 Data |= ((Offset & 0xFF) << 12);
289 Data |= ((eRFPath & 0x3) << 20);
290 Data |= 0x80000000;
291 while (read_nic_dword(dev, QPNR)&0x80000000) {
292 if (time++ < 100)
293 udelay(10);
294 else
295 break;
296 }
297 write_nic_dword(dev, QPNR, Data);
298 while (read_nic_dword(dev, QPNR) & 0x80000000) {
299 if (time++ < 100)
300 udelay(10);
301 else
302 return 0;
303 }
304 retValue = read_nic_dword(dev, RF_DATA);
305
306 return retValue;
307
308}
309
310static void phy_FwRFSerialWrite(struct net_device *dev,
311 enum rf90_radio_path eRFPath,
312 u32 Offset, u32 Data)
313{
314 u8 time = 0;
315
316 Data |= ((Offset & 0xFF) << 12);
317 Data |= ((eRFPath & 0x3) << 20);
318 Data |= 0x400000;
319 Data |= 0x80000000;
320
321 while (read_nic_dword(dev, QPNR) & 0x80000000) {
322 if (time++ < 100)
323 udelay(10);
324 else
325 break;
326 }
327 write_nic_dword(dev, QPNR, Data);
328
329}
330
331
332void rtl8192_phy_configmac(struct net_device *dev)
333{
334 u32 dwArrayLen = 0, i = 0;
335 u32 *pdwArray = NULL;
336 struct r8192_priv *priv = rtllib_priv(dev);
337
338 if (priv->bTXPowerDataReadFromEEPORM) {
339 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
340 dwArrayLen = MACPHY_Array_PGLength;
341 pdwArray = Rtl819XMACPHY_Array_PG;
342
343 } else {
344 RT_TRACE(COMP_PHY, "Read rtl819XMACPHY_Array\n");
345 dwArrayLen = MACPHY_ArrayLength;
346 pdwArray = Rtl819XMACPHY_Array;
347 }
348 for (i = 0; i < dwArrayLen; i += 3) {
349 RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MAC"
350 "PHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
351 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
352 if (pdwArray[i] == 0x318)
353 pdwArray[i+2] = 0x00000800;
354 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1],
355 pdwArray[i+2]);
356 }
357 return;
358
359}
360
361void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType)
362{
363 int i;
364 u32 *Rtl819XPHY_REGArray_Table = NULL;
365 u32 *Rtl819XAGCTAB_Array_Table = NULL;
366 u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0;
367 struct r8192_priv *priv = rtllib_priv(dev);
368
369 AGCTAB_ArrayLen = AGCTAB_ArrayLength;
370 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
371 if (priv->rf_type == RF_2T4R) {
372 PHY_REGArrayLen = PHY_REGArrayLength;
373 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray;
374 } else if (priv->rf_type == RF_1T2R) {
375 PHY_REGArrayLen = PHY_REG_1T2RArrayLength;
376 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray;
377 }
378
379 if (ConfigType == BaseBand_Config_PHY_REG) {
380 for (i = 0; i < PHY_REGArrayLen; i += 2) {
381 rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i],
382 bMaskDWord,
383 Rtl819XPHY_REGArray_Table[i+1]);
384 RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray"
385 "[0] is %x Rtl819xUsbPHY_REGArray[1] is %x\n",
386 i, Rtl819XPHY_REGArray_Table[i],
387 Rtl819XPHY_REGArray_Table[i+1]);
388 }
389 } else if (ConfigType == BaseBand_Config_AGC_TAB) {
390 for (i = 0; i < AGCTAB_ArrayLen; i += 2) {
391 rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i],
392 bMaskDWord,
393 Rtl819XAGCTAB_Array_Table[i+1]);
394 RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] "
395 "is %x rtl819XAGCTAB_Array[1] is %x\n", i,
396 Rtl819XAGCTAB_Array_Table[i],
397 Rtl819XAGCTAB_Array_Table[i+1]);
398 }
399 }
400 return;
401}
402
403static void rtl8192_InitBBRFRegDef(struct net_device *dev)
404{
405 struct r8192_priv *priv = rtllib_priv(dev);
406
407 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
408 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
409 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
410 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
411
412 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
413 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
414 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
415 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
416
417 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
418 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
419 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
420 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
421
422 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
423 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
424 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
425 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
426
427 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
428 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
429 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
430 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
431
432 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
433 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
434 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
435 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
436
437 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
438 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
439 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
440 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
441
442 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
443 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
444 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
445 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
446
447 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
448 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
449 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
450 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
451
452 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
453 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
454 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
455 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
456
457 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
458 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
459 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
460 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
461
462 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
463 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
464 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
465 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
466
467 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
468 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
469 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
470 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
471
472 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
473 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
474 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
475 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
476
477 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
478 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
479 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
480 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
481
482 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
483 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
484 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
485 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
486
487 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
488 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
489 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
490 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
491
492}
493
494bool rtl8192_phy_checkBBAndRF(struct net_device *dev,
495 enum hw90_block CheckBlock,
496 enum rf90_radio_path eRFPath)
497{
498 bool ret = true;
499 u32 i, CheckTimes = 4, dwRegRead = 0;
500 u32 WriteAddr[4];
501 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
502
503 WriteAddr[HW90_BLOCK_MAC] = 0x100;
504 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
505 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
506 WriteAddr[HW90_BLOCK_RF] = 0x3;
507 RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __func__,
508 CheckBlock);
509 for (i = 0; i < CheckTimes; i++) {
510 switch (CheckBlock) {
511 case HW90_BLOCK_MAC:
512 RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write "
513 "0x100 here!");
514 break;
515
516 case HW90_BLOCK_PHY0:
517 case HW90_BLOCK_PHY1:
518 write_nic_dword(dev, WriteAddr[CheckBlock],
519 WriteData[i]);
520 dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
521 break;
522
523 case HW90_BLOCK_RF:
524 WriteData[i] &= 0xfff;
525 rtl8192_phy_SetRFReg(dev, eRFPath,
526 WriteAddr[HW90_BLOCK_RF],
527 bMask12Bits, WriteData[i]);
528 mdelay(10);
529 dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath,
530 WriteAddr[HW90_BLOCK_RF],
531 bMaskDWord);
532 mdelay(10);
533 break;
534
535 default:
536 ret = false;
537 break;
538 }
539
540
541 if (dwRegRead != WriteData[i]) {
542 RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, "
543 "WriteData: %x\n", dwRegRead, WriteData[i]);
544 ret = false;
545 break;
546 }
547 }
548
549 return ret;
550}
551
552static bool rtl8192_BB_Config_ParaFile(struct net_device *dev)
553{
554 struct r8192_priv *priv = rtllib_priv(dev);
555 bool rtStatus = true;
556 u8 bRegValue = 0, eCheckItem = 0;
557 u32 dwRegValue = 0;
558
559 bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET);
560 write_nic_byte(dev, BB_GLOBAL_RESET, (bRegValue|BB_GLOBAL_RESET_BIT));
561
562 dwRegValue = read_nic_dword(dev, CPU_GEN);
563 write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
564
565 for (eCheckItem = (enum hw90_block)HW90_BLOCK_PHY0;
566 eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) {
567 rtStatus = rtl8192_phy_checkBBAndRF(dev,
568 (enum hw90_block)eCheckItem,
569 (enum rf90_radio_path)0);
570 if (rtStatus != true) {
571 RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():"
572 "Check PHY%d Fail!!\n", eCheckItem-1);
573 return rtStatus;
574 }
575 }
576 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
577 rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
578
579 dwRegValue = read_nic_dword(dev, CPU_GEN);
580 write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
581
582 rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
583
584 if (priv->IC_Cut > VERSION_8190_BD) {
585 if (priv->rf_type == RF_2T4R)
586 dwRegValue = (priv->AntennaTxPwDiff[2]<<8 |
587 priv->AntennaTxPwDiff[1]<<4 |
588 priv->AntennaTxPwDiff[0]);
589 else
590 dwRegValue = 0x0;
591 rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
592 (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
593
594
595 dwRegValue = priv->CrystalCap;
596 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x,
597 dwRegValue);
598 }
599
600 return rtStatus;
601}
602bool rtl8192_BBConfig(struct net_device *dev)
603{
604 bool rtStatus = true;
605
606 rtl8192_InitBBRFRegDef(dev);
607 rtStatus = rtl8192_BB_Config_ParaFile(dev);
608 return rtStatus;
609}
610
611void rtl8192_phy_getTxPower(struct net_device *dev)
612{
613 struct r8192_priv *priv = rtllib_priv(dev);
614
615 priv->MCSTxPowerLevelOriginalOffset[0] =
616 read_nic_dword(dev, rTxAGC_Rate18_06);
617 priv->MCSTxPowerLevelOriginalOffset[1] =
618 read_nic_dword(dev, rTxAGC_Rate54_24);
619 priv->MCSTxPowerLevelOriginalOffset[2] =
620 read_nic_dword(dev, rTxAGC_Mcs03_Mcs00);
621 priv->MCSTxPowerLevelOriginalOffset[3] =
622 read_nic_dword(dev, rTxAGC_Mcs07_Mcs04);
623 priv->MCSTxPowerLevelOriginalOffset[4] =
624 read_nic_dword(dev, rTxAGC_Mcs11_Mcs08);
625 priv->MCSTxPowerLevelOriginalOffset[5] =
626 read_nic_dword(dev, rTxAGC_Mcs15_Mcs12);
627
628 priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1);
629 priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1);
630 priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1);
631 priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1);
632 RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, "
633 "c60=0x%x, c68=0x%x)\n",
634 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
635 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
636
637 priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3);
638 priv->framesyncC34 = read_nic_dword(dev, rOFDM0_RxDetector2);
639 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n",
640 rOFDM0_RxDetector3, priv->framesync);
641 priv->SifsTime = read_nic_word(dev, SIFS);
642 return;
643}
644
645void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
646{
647 struct r8192_priv *priv = rtllib_priv(dev);
648 u8 powerlevel = 0, powerlevelOFDM24G = 0;
649 char ant_pwr_diff;
650 u32 u4RegValue;
651
652 if (priv->epromtype == EEPROM_93C46) {
653 powerlevel = priv->TxPowerLevelCCK[channel-1];
654 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
655 } else if (priv->epromtype == EEPROM_93C56) {
656 if (priv->rf_type == RF_1T2R) {
657 powerlevel = priv->TxPowerLevelCCK_C[channel-1];
658 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1];
659 } else if (priv->rf_type == RF_2T4R) {
660 powerlevel = priv->TxPowerLevelCCK_A[channel-1];
661 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1];
662
663 ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1]
664 - priv->TxPowerLevelOFDM24G_A[channel-1];
665
666 priv->RF_C_TxPwDiff = ant_pwr_diff;
667
668 ant_pwr_diff &= 0xf;
669
670 priv->AntennaTxPwDiff[2] = 0;
671 priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff);
672 priv->AntennaTxPwDiff[0] = 0;
673
674 u4RegValue = (priv->AntennaTxPwDiff[2]<<8 |
675 priv->AntennaTxPwDiff[1]<<4 |
676 priv->AntennaTxPwDiff[0]);
677
678 rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
679 (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
680 }
681 }
682 switch (priv->rf_chip) {
683 case RF_8225:
684 break;
685 case RF_8256:
686 PHY_SetRF8256CCKTxPower(dev, powerlevel);
687 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
688 break;
689 case RF_8258:
690 break;
691 default:
692 RT_TRACE(COMP_ERR, "unknown rf chip in function %s()\n",
693 __func__);
694 break;
695 }
696 return;
697}
698
699bool rtl8192_phy_RFConfig(struct net_device *dev)
700{
701 struct r8192_priv *priv = rtllib_priv(dev);
702 bool rtStatus = true;
703 switch (priv->rf_chip) {
704 case RF_8225:
705 break;
706 case RF_8256:
707 rtStatus = PHY_RF8256_Config(dev);
708 break;
709
710 case RF_8258:
711 break;
712 case RF_PSEUDO_11N:
713 break;
714
715 default:
716 RT_TRACE(COMP_ERR, "error chip id\n");
717 break;
718 }
719 return rtStatus;
720}
721
722void rtl8192_phy_updateInitGain(struct net_device *dev)
723{
724 return;
725}
726
727u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
728 enum rf90_radio_path eRFPath)
729{
730
731 int i;
732 u8 ret = 0;
733
734 switch (eRFPath) {
735 case RF90_PATH_A:
736 for (i = 0; i < RadioA_ArrayLength; i += 2) {
737 if (Rtl819XRadioA_Array[i] == 0xfe) {
738 msleep(100);
739 continue;
740 }
741 rtl8192_phy_SetRFReg(dev, eRFPath,
742 Rtl819XRadioA_Array[i],
743 bMask12Bits,
744 Rtl819XRadioA_Array[i+1]);
745
746 }
747 break;
748 case RF90_PATH_B:
749 for (i = 0; i < RadioB_ArrayLength; i += 2) {
750 if (Rtl819XRadioB_Array[i] == 0xfe) {
751 msleep(100);
752 continue;
753 }
754 rtl8192_phy_SetRFReg(dev, eRFPath,
755 Rtl819XRadioB_Array[i],
756 bMask12Bits,
757 Rtl819XRadioB_Array[i+1]);
758
759 }
760 break;
761 case RF90_PATH_C:
762 for (i = 0; i < RadioC_ArrayLength; i += 2) {
763 if (Rtl819XRadioC_Array[i] == 0xfe) {
764 msleep(100);
765 continue;
766 }
767 rtl8192_phy_SetRFReg(dev, eRFPath,
768 Rtl819XRadioC_Array[i],
769 bMask12Bits,
770 Rtl819XRadioC_Array[i+1]);
771
772 }
773 break;
774 case RF90_PATH_D:
775 for (i = 0; i < RadioD_ArrayLength; i += 2) {
776 if (Rtl819XRadioD_Array[i] == 0xfe) {
777 msleep(100);
778 continue;
779 }
780 rtl8192_phy_SetRFReg(dev, eRFPath,
781 Rtl819XRadioD_Array[i], bMask12Bits,
782 Rtl819XRadioD_Array[i+1]);
783
784 }
785 break;
786 default:
787 break;
788 }
789
790 return ret;
791
792}
793static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
794{
795 struct r8192_priv *priv = rtllib_priv(dev);
796 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
797 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
798
799 switch (priv->rf_chip) {
800 case RF_8225:
801 break;
802
803 case RF_8256:
804 PHY_SetRF8256CCKTxPower(dev, powerlevel);
805 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
806 break;
807
808 case RF_8258:
809 break;
810 default:
811 RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPower"
812 "Level()\n");
813 break;
814 }
815 return;
816}
817
818static u8 rtl8192_phy_SetSwChnlCmdArray(struct sw_chnl_cmd *CmdTable,
819 u32 CmdTableIdx, u32 CmdTableSz,
820 enum sw_chnl_cmd_id CmdID,
821 u32 Para1, u32 Para2, u32 msDelay)
822{
823 struct sw_chnl_cmd *pCmd;
824
825 if (CmdTable == NULL) {
826 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot "
827 "be NULL.\n");
828 return false;
829 }
830 if (CmdTableIdx >= CmdTableSz) {
831 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid"
832 " index, please check size of the table, CmdTableIdx:"
833 "%d, CmdTableSz:%d\n",
834 CmdTableIdx, CmdTableSz);
835 return false;
836 }
837
838 pCmd = CmdTable + CmdTableIdx;
839 pCmd->CmdID = CmdID;
840 pCmd->Para1 = Para1;
841 pCmd->Para2 = Para2;
842 pCmd->msDelay = msDelay;
843
844 return true;
845}
846
847static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel,
848 u8 *stage, u8 *step, u32 *delay)
849{
850 struct r8192_priv *priv = rtllib_priv(dev);
851 struct rtllib_device *ieee = priv->rtllib;
852 u32 PreCommonCmdCnt;
853 u32 PostCommonCmdCnt;
854 u32 RfDependCmdCnt;
855 struct sw_chnl_cmd *CurrentCmd = NULL;
856 u8 eRFPath;
857
858 RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n",
859 __func__, *stage, *step, channel);
860
861 if (!rtllib_legal_channel(priv->rtllib, channel)) {
862 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n",
863 channel);
864 return true;
865 }
866
867 {
868 PreCommonCmdCnt = 0;
869 rtl8192_phy_SetSwChnlCmdArray(ieee->PreCommonCmd,
870 PreCommonCmdCnt++,
871 MAX_PRECMD_CNT, CmdID_SetTxPowerLevel,
872 0, 0, 0);
873 rtl8192_phy_SetSwChnlCmdArray(ieee->PreCommonCmd,
874 PreCommonCmdCnt++,
875 MAX_PRECMD_CNT, CmdID_End, 0, 0, 0);
876
877 PostCommonCmdCnt = 0;
878
879 rtl8192_phy_SetSwChnlCmdArray(ieee->PostCommonCmd,
880 PostCommonCmdCnt++,
881 MAX_POSTCMD_CNT, CmdID_End, 0, 0, 0);
882
883 RfDependCmdCnt = 0;
884 switch (priv->rf_chip) {
885 case RF_8225:
886 if (!(channel >= 1 && channel <= 14)) {
887 RT_TRACE(COMP_ERR, "illegal channel for Zebra "
888 "8225: %d\n", channel);
889 return false;
890 }
891 rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd,
892 RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
893 CmdID_RF_WriteReg, rZebra1_Channel,
894 RF_CHANNEL_TABLE_ZEBRA[channel], 10);
895 rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd,
896 RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
897 CmdID_End, 0, 0, 0);
898 break;
899
900 case RF_8256:
901 if (!(channel >= 1 && channel <= 14)) {
902 RT_TRACE(COMP_ERR, "illegal channel for Zebra"
903 " 8256: %d\n", channel);
904 return false;
905 }
906 rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd,
907 RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
908 CmdID_RF_WriteReg, rZebra1_Channel, channel,
909 10);
910 rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd,
911
912 RfDependCmdCnt++,
913 MAX_RFDEPENDCMD_CNT,
914 CmdID_End, 0, 0, 0);
915 break;
916
917 case RF_8258:
918 break;
919
920 default:
921 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n",
922 priv->rf_chip);
923 return false;
924 break;
925 }
926
927
928 do {
929 switch (*stage) {
930 case 0:
931 CurrentCmd = &ieee->PreCommonCmd[*step];
932 break;
933 case 1:
934 CurrentCmd = &ieee->RfDependCmd[*step];
935 break;
936 case 2:
937 CurrentCmd = &ieee->PostCommonCmd[*step];
938 break;
939 }
940
941 if (CurrentCmd && CurrentCmd->CmdID == CmdID_End) {
942 if ((*stage) == 2) {
943 return true;
944 } else {
945 (*stage)++;
946 (*step) = 0;
947 continue;
948 }
949 }
950
951 if (!CurrentCmd)
952 continue;
953 switch (CurrentCmd->CmdID) {
954 case CmdID_SetTxPowerLevel:
955 if (priv->IC_Cut > (u8)VERSION_8190_BD)
956 rtl8192_SetTxPowerLevel(dev, channel);
957 break;
958 case CmdID_WritePortUlong:
959 write_nic_dword(dev, CurrentCmd->Para1,
960 CurrentCmd->Para2);
961 break;
962 case CmdID_WritePortUshort:
963 write_nic_word(dev, CurrentCmd->Para1,
964 (u16)CurrentCmd->Para2);
965 break;
966 case CmdID_WritePortUchar:
967 write_nic_byte(dev, CurrentCmd->Para1,
968 (u8)CurrentCmd->Para2);
969 break;
970 case CmdID_RF_WriteReg:
971 for (eRFPath = 0; eRFPath <
972 priv->NumTotalRFPath; eRFPath++)
973 rtl8192_phy_SetRFReg(dev,
974 (enum rf90_radio_path)eRFPath,
975 CurrentCmd->Para1, bMask12Bits,
976 CurrentCmd->Para2<<7);
977 break;
978 default:
979 break;
980 }
981
982 break;
983 } while (true);
984 }
985
986 (*delay) = CurrentCmd->msDelay;
987 (*step)++;
988 return false;
989}
990
991static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
992{
993 struct r8192_priv *priv = rtllib_priv(dev);
994 u32 delay = 0;
995
996 while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage,
997 &priv->SwChnlStep, &delay)) {
998 if (delay > 0)
999 msleep(delay);
1000 if (IS_NIC_DOWN(priv))
1001 break;
1002 }
1003}
1004void rtl8192_SwChnl_WorkItem(struct net_device *dev)
1005{
1006
1007 struct r8192_priv *priv = rtllib_priv(dev);
1008
1009 RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n");
1010
1011 RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __func__,
1012 priv->chan, priv);
1013
1014 rtl8192_phy_FinishSwChnlNow(dev , priv->chan);
1015
1016 RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n");
1017}
1018
1019u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel)
1020{
1021 struct r8192_priv *priv = rtllib_priv(dev);
1022 RT_TRACE(COMP_PHY, "=====>%s()\n", __func__);
1023 if (IS_NIC_DOWN(priv)) {
1024 RT_TRACE(COMP_ERR, "%s(): ERR !! driver is not up\n", __func__);
1025 return false;
1026 }
1027 if (priv->SwChnlInProgress)
1028 return false;
1029
1030
1031 switch (priv->rtllib->mode) {
1032 case WIRELESS_MODE_A:
1033 case WIRELESS_MODE_N_5G:
1034 if (channel <= 14) {
1035 RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
1036 return false;
1037 }
1038 break;
1039 case WIRELESS_MODE_B:
1040 if (channel > 14) {
1041 RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
1042 return false;
1043 }
1044 break;
1045 case WIRELESS_MODE_G:
1046 case WIRELESS_MODE_N_24G:
1047 if (channel > 14) {
1048 RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
1049 return false;
1050 }
1051 break;
1052 }
1053
1054 priv->SwChnlInProgress = true;
1055 if (channel == 0)
1056 channel = 1;
1057
1058 priv->chan = channel;
1059
1060 priv->SwChnlStage = 0;
1061 priv->SwChnlStep = 0;
1062
1063 if (!IS_NIC_DOWN(priv))
1064 rtl8192_SwChnl_WorkItem(dev);
1065 priv->SwChnlInProgress = false;
1066 return true;
1067}
1068
1069static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev)
1070{
1071 struct r8192_priv *priv = rtllib_priv(dev);
1072
1073 switch (priv->CurrentChannelBW) {
1074 case HT_CHANNEL_WIDTH_20:
1075 priv->CCKPresentAttentuation =
1076 priv->CCKPresentAttentuation_20Mdefault +
1077 priv->CCKPresentAttentuation_difference;
1078
1079 if (priv->CCKPresentAttentuation >
1080 (CCKTxBBGainTableLength-1))
1081 priv->CCKPresentAttentuation =
1082 CCKTxBBGainTableLength-1;
1083 if (priv->CCKPresentAttentuation < 0)
1084 priv->CCKPresentAttentuation = 0;
1085
1086 RT_TRACE(COMP_POWER_TRACKING, "20M, priv->CCKPresent"
1087 "Attentuation = %d\n",
1088 priv->CCKPresentAttentuation);
1089
1090 if (priv->rtllib->current_network.channel == 14 &&
1091 !priv->bcck_in_ch14) {
1092 priv->bcck_in_ch14 = true;
1093 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1094 } else if (priv->rtllib->current_network.channel !=
1095 14 && priv->bcck_in_ch14) {
1096 priv->bcck_in_ch14 = false;
1097 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1098 } else {
1099 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1100 }
1101 break;
1102
1103 case HT_CHANNEL_WIDTH_20_40:
1104 priv->CCKPresentAttentuation =
1105 priv->CCKPresentAttentuation_40Mdefault +
1106 priv->CCKPresentAttentuation_difference;
1107
1108 RT_TRACE(COMP_POWER_TRACKING, "40M, priv->CCKPresent"
1109 "Attentuation = %d\n",
1110 priv->CCKPresentAttentuation);
1111 if (priv->CCKPresentAttentuation >
1112 (CCKTxBBGainTableLength - 1))
1113 priv->CCKPresentAttentuation =
1114 CCKTxBBGainTableLength-1;
1115 if (priv->CCKPresentAttentuation < 0)
1116 priv->CCKPresentAttentuation = 0;
1117
1118 if (priv->rtllib->current_network.channel == 14 &&
1119 !priv->bcck_in_ch14) {
1120 priv->bcck_in_ch14 = true;
1121 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1122 } else if (priv->rtllib->current_network.channel != 14
1123 && priv->bcck_in_ch14) {
1124 priv->bcck_in_ch14 = false;
1125 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1126 } else {
1127 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1128 }
1129 break;
1130 }
1131}
1132
1133static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev)
1134{
1135 struct r8192_priv *priv = rtllib_priv(dev);
1136
1137 if (priv->rtllib->current_network.channel == 14 &&
1138 !priv->bcck_in_ch14)
1139 priv->bcck_in_ch14 = true;
1140 else if (priv->rtllib->current_network.channel != 14 &&
1141 priv->bcck_in_ch14)
1142 priv->bcck_in_ch14 = false;
1143
1144 switch (priv->CurrentChannelBW) {
1145 case HT_CHANNEL_WIDTH_20:
1146 if (priv->Record_CCK_20Mindex == 0)
1147 priv->Record_CCK_20Mindex = 6;
1148 priv->CCK_index = priv->Record_CCK_20Mindex;
1149 RT_TRACE(COMP_POWER_TRACKING, "20MHz, CCK_Tx_Power_Track_BW_"
1150 "Switch_ThermalMeter(),CCK_index = %d\n",
1151 priv->CCK_index);
1152 break;
1153
1154 case HT_CHANNEL_WIDTH_20_40:
1155 priv->CCK_index = priv->Record_CCK_40Mindex;
1156 RT_TRACE(COMP_POWER_TRACKING, "40MHz, CCK_Tx_Power_Track_BW_"
1157 "Switch_ThermalMeter(), CCK_index = %d\n",
1158 priv->CCK_index);
1159 break;
1160 }
1161 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1162}
1163
1164static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev)
1165{
1166 struct r8192_priv *priv = rtllib_priv(dev);
1167
1168 if (priv->IC_Cut >= IC_VersionCut_D)
1169 CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
1170 else
1171 CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev);
1172}
1173
1174void rtl8192_SetBWModeWorkItem(struct net_device *dev)
1175{
1176
1177 struct r8192_priv *priv = rtllib_priv(dev);
1178 u8 regBwOpMode;
1179
1180 RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s "
1181 "bandwidth\n", priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ?
1182 "20MHz" : "40MHz")
1183
1184
1185 if (priv->rf_chip == RF_PSEUDO_11N) {
1186 priv->SetBWModeInProgress = false;
1187 return;
1188 }
1189 if (IS_NIC_DOWN(priv)) {
1190 RT_TRACE(COMP_ERR, "%s(): ERR!! driver is not up\n", __func__);
1191 return;
1192 }
1193 regBwOpMode = read_nic_byte(dev, BW_OPMODE);
1194
1195 switch (priv->CurrentChannelBW) {
1196 case HT_CHANNEL_WIDTH_20:
1197 regBwOpMode |= BW_OPMODE_20MHZ;
1198 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1199 break;
1200
1201 case HT_CHANNEL_WIDTH_20_40:
1202 regBwOpMode &= ~BW_OPMODE_20MHZ;
1203 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1204 break;
1205
1206 default:
1207 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown "
1208 "Bandwidth: %#X\n", priv->CurrentChannelBW);
1209 break;
1210 }
1211
1212 switch (priv->CurrentChannelBW) {
1213 case HT_CHANNEL_WIDTH_20:
1214 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1215 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1216
1217 if (!priv->btxpower_tracking) {
1218 write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
1219 write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
1220 write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
1221 } else {
1222 CCK_Tx_Power_Track_BW_Switch(dev);
1223 }
1224
1225 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
1226
1227 break;
1228 case HT_CHANNEL_WIDTH_20_40:
1229 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1230 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1231
1232 if (!priv->btxpower_tracking) {
1233 write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
1234 write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
1235 write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
1236 } else {
1237 CCK_Tx_Power_Track_BW_Switch(dev);
1238 }
1239
1240 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand,
1241 (priv->nCur40MhzPrimeSC>>1));
1242 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00,
1243 priv->nCur40MhzPrimeSC);
1244
1245 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1246 break;
1247 default:
1248 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown "
1249 "Bandwidth: %#X\n", priv->CurrentChannelBW);
1250 break;
1251
1252 }
1253
1254 switch (priv->rf_chip) {
1255 case RF_8225:
1256 break;
1257
1258 case RF_8256:
1259 PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
1260 break;
1261
1262 case RF_8258:
1263 break;
1264
1265 case RF_PSEUDO_11N:
1266 break;
1267
1268 default:
1269 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1270 break;
1271 }
1272
1273 atomic_dec(&(priv->rtllib->atm_swbw));
1274 priv->SetBWModeInProgress = false;
1275
1276 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()");
1277}
1278
1279void rtl8192_SetBWMode(struct net_device *dev, enum ht_channel_width Bandwidth,
1280 enum ht_extchnl_offset Offset)
1281{
1282 struct r8192_priv *priv = rtllib_priv(dev);
1283
1284
1285 if (priv->SetBWModeInProgress)
1286 return;
1287
1288 atomic_inc(&(priv->rtllib->atm_swbw));
1289 priv->SetBWModeInProgress = true;
1290
1291 priv->CurrentChannelBW = Bandwidth;
1292
1293 if (Offset == HT_EXTCHNL_OFFSET_LOWER)
1294 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1295 else if (Offset == HT_EXTCHNL_OFFSET_UPPER)
1296 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1297 else
1298 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1299
1300 rtl8192_SetBWModeWorkItem(dev);
1301
1302}
1303
1304void InitialGain819xPci(struct net_device *dev, u8 Operation)
1305{
1306#define SCAN_RX_INITIAL_GAIN 0x17
1307#define POWER_DETECTION_TH 0x08
1308 struct r8192_priv *priv = rtllib_priv(dev);
1309 u32 BitMask;
1310 u8 initial_gain;
1311
1312 if (!IS_NIC_DOWN(priv)) {
1313 switch (Operation) {
1314 case IG_Backup:
1315 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial"
1316 " gain.\n");
1317 initial_gain = SCAN_RX_INITIAL_GAIN;
1318 BitMask = bMaskByte0;
1319 if (dm_digtable.dig_algorithm ==
1320 DIG_ALGO_BY_FALSE_ALARM)
1321 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1322 priv->initgain_backup.xaagccore1 =
1323 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1,
1324 BitMask);
1325 priv->initgain_backup.xbagccore1 =
1326 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1,
1327 BitMask);
1328 priv->initgain_backup.xcagccore1 =
1329 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1,
1330 BitMask);
1331 priv->initgain_backup.xdagccore1 =
1332 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1,
1333 BitMask);
1334 BitMask = bMaskByte2;
1335 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev,
1336 rCCK0_CCA, BitMask);
1337
1338 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is"
1339 " %x\n", priv->initgain_backup.xaagccore1);
1340 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is"
1341 " %x\n", priv->initgain_backup.xbagccore1);
1342 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is"
1343 " %x\n", priv->initgain_backup.xcagccore1);
1344 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is"
1345 " %x\n", priv->initgain_backup.xdagccore1);
1346 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is"
1347 " %x\n", priv->initgain_backup.cca);
1348
1349 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n",
1350 initial_gain);
1351 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1352 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1353 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1354 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1355 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n",
1356 POWER_DETECTION_TH);
1357 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
1358 break;
1359 case IG_Restore:
1360 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial "
1361 "gain.\n");
1362 BitMask = 0x7f;
1363 if (dm_digtable.dig_algorithm ==
1364 DIG_ALGO_BY_FALSE_ALARM)
1365 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1366
1367 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask,
1368 (u32)priv->initgain_backup.xaagccore1);
1369 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask,
1370 (u32)priv->initgain_backup.xbagccore1);
1371 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask,
1372 (u32)priv->initgain_backup.xcagccore1);
1373 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask,
1374 (u32)priv->initgain_backup.xdagccore1);
1375 BitMask = bMaskByte2;
1376 rtl8192_setBBreg(dev, rCCK0_CCA, BitMask,
1377 (u32)priv->initgain_backup.cca);
1378
1379 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50"
1380 " is %x\n", priv->initgain_backup.xaagccore1);
1381 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58"
1382 " is %x\n", priv->initgain_backup.xbagccore1);
1383 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60"
1384 " is %x\n", priv->initgain_backup.xcagccore1);
1385 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68"
1386 " is %x\n", priv->initgain_backup.xdagccore1);
1387 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a"
1388 " is %x\n", priv->initgain_backup.cca);
1389
1390 rtl8192_phy_setTxPower(dev,
1391 priv->rtllib->current_network.channel);
1392
1393 if (dm_digtable.dig_algorithm ==
1394 DIG_ALGO_BY_FALSE_ALARM)
1395 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);
1396 break;
1397 default:
1398 RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n");
1399 break;
1400 }
1401 }
1402}
1403
1404void PHY_SetRtl8192eRfOff(struct net_device *dev)
1405{
1406
1407 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0);
1408 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0);
1409 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0);
1410 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
1411 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
1412 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0);
1413 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0);
1414 write_nic_byte(dev, ANAPAR_FOR_8192PciE, 0x07);
1415
1416}
1417
1418static bool SetRFPowerState8190(struct net_device *dev,
1419 enum rt_rf_power_state eRFPowerState)
1420{
1421 struct r8192_priv *priv = rtllib_priv(dev);
1422 struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *)
1423 (&(priv->rtllib->PowerSaveControl));
1424 bool bResult = true;
1425 u8 i = 0, QueueID = 0;
1426 struct rtl8192_tx_ring *ring = NULL;
1427
1428 if (priv->SetRFPowerStateInProgress == true)
1429 return false;
1430 RT_TRACE(COMP_PS, "===========> SetRFPowerState8190()!\n");
1431 priv->SetRFPowerStateInProgress = true;
1432
1433 switch (priv->rf_chip) {
1434 case RF_8256:
1435 switch (eRFPowerState) {
1436 case eRfOn:
1437 RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOn!\n");
1438 if ((priv->rtllib->eRFPowerState == eRfOff) &&
1439 RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) {
1440 bool rtstatus = true;
1441 u32 InitilizeCount = 3;
1442 do {
1443 InitilizeCount--;
1444 priv->RegRfOff = false;
1445 rtstatus = NicIFEnableNIC(dev);
1446 } while ((rtstatus != true) &&
1447 (InitilizeCount > 0));
1448
1449 if (rtstatus != true) {
1450 RT_TRACE(COMP_ERR, "%s():Initialize Ada"
1451 "pter fail,return\n",
1452 __func__);
1453 priv->SetRFPowerStateInProgress = false;
1454 return false;
1455 }
1456
1457 RT_CLEAR_PS_LEVEL(pPSC,
1458 RT_RF_OFF_LEVL_HALT_NIC);
1459 } else {
1460 write_nic_byte(dev, ANAPAR, 0x37);
1461 mdelay(1);
1462 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1463 0x4, 0x1);
1464 priv->bHwRfOffAction = 0;
1465
1466 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE,
1467 BIT4, 0x1);
1468 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4,
1469 0x300, 0x3);
1470 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1471 0x18, 0x3);
1472 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3,
1473 0x3);
1474 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3,
1475 0x3);
1476 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1477 0x60, 0x3);
1478
1479 }
1480
1481 break;
1482
1483 case eRfSleep:
1484 if (priv->rtllib->eRFPowerState == eRfOff)
1485 break;
1486
1487
1488 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
1489 ring = &priv->tx_ring[QueueID];
1490
1491 if (skb_queue_len(&ring->queue) == 0) {
1492 QueueID++;
1493 continue;
1494 } else {
1495 RT_TRACE((COMP_POWER|COMP_RF), "eRf Off"
1496 "/Sleep: %d times TcbBusyQueue"
1497 "[%d] !=0 before doze!\n",
1498 (i+1), QueueID);
1499 udelay(10);
1500 i++;
1501 }
1502
1503 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
1504 RT_TRACE(COMP_POWER, "\n\n\n TimeOut!! "
1505 "SetRFPowerState8190(): eRfOff"
1506 ": %d times TcbBusyQueue[%d] "
1507 "!= 0 !!!\n",
1508 MAX_DOZE_WAITING_TIMES_9x,
1509 QueueID);
1510 break;
1511 }
1512 }
1513 PHY_SetRtl8192eRfOff(dev);
1514 break;
1515
1516 case eRfOff:
1517 RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOff/"
1518 "Sleep !\n");
1519
1520 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
1521 ring = &priv->tx_ring[QueueID];
1522
1523 if (skb_queue_len(&ring->queue) == 0) {
1524 QueueID++;
1525 continue;
1526 } else {
1527 RT_TRACE(COMP_POWER, "eRf Off/Sleep: %d"
1528 " times TcbBusyQueue[%d] !=0 b"
1529 "efore doze!\n", (i+1),
1530 QueueID);
1531 udelay(10);
1532 i++;
1533 }
1534
1535 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
1536 RT_TRACE(COMP_POWER, "\n\n\n SetZebra: "
1537 "RFPowerState8185B(): eRfOff:"
1538 " %d times TcbBusyQueue[%d] "
1539 "!= 0 !!!\n",
1540 MAX_DOZE_WAITING_TIMES_9x,
1541 QueueID);
1542 break;
1543 }
1544 }
1545
1546 if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC &&
1547 !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) {
1548 NicIFDisableNIC(dev);
1549 RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
1550 } else if (!(pPSC->RegRfPsLevel &
1551 RT_RF_OFF_LEVL_HALT_NIC)) {
1552 PHY_SetRtl8192eRfOff(dev);
1553 }
1554
1555 break;
1556
1557 default:
1558 bResult = false;
1559 RT_TRACE(COMP_ERR, "SetRFPowerState8190(): unknow state"
1560 " to set: 0x%X!!!\n", eRFPowerState);
1561 break;
1562 }
1563
1564 break;
1565
1566 default:
1567 RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n");
1568 break;
1569 }
1570
1571 if (bResult) {
1572 priv->rtllib->eRFPowerState = eRFPowerState;
1573
1574 switch (priv->rf_chip) {
1575 case RF_8256:
1576 break;
1577
1578 default:
1579 RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown "
1580 "RF type\n");
1581 break;
1582 }
1583 }
1584
1585 priv->SetRFPowerStateInProgress = false;
1586 RT_TRACE(COMP_PS, "<=========== SetRFPowerState8190() bResult = %d!\n",
1587 bResult);
1588 return bResult;
1589}
1590
1591bool SetRFPowerState(struct net_device *dev,
1592 enum rt_rf_power_state eRFPowerState)
1593{
1594 struct r8192_priv *priv = rtllib_priv(dev);
1595
1596 bool bResult = false;
1597
1598 RT_TRACE(COMP_PS, "---------> SetRFPowerState(): eRFPowerState(%d)\n",
1599 eRFPowerState);
1600 if (eRFPowerState == priv->rtllib->eRFPowerState &&
1601 priv->bHwRfOffAction == 0) {
1602 RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): discard the "
1603 "request for eRFPowerState(%d) is the same.\n",
1604 eRFPowerState);
1605 return bResult;
1606 }
1607
1608 bResult = SetRFPowerState8190(dev, eRFPowerState);
1609
1610 RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): bResult(%d)\n",
1611 bResult);
1612
1613 return bResult;
1614}
1615
1616void PHY_ScanOperationBackup8192(struct net_device *dev, u8 Operation)
1617{
1618 struct r8192_priv *priv = rtllib_priv(dev);
1619
1620 if (priv->up) {
1621 switch (Operation) {
1622 case SCAN_OPT_BACKUP:
1623 priv->rtllib->InitialGainHandler(dev, IG_Backup);
1624 break;
1625
1626 case SCAN_OPT_RESTORE:
1627 priv->rtllib->InitialGainHandler(dev, IG_Restore);
1628 break;
1629
1630 default:
1631 RT_TRACE(COMP_SCAN, "Unknown Scan Backup Operation.\n");
1632 break;
1633 }
1634 }
1635
1636}
1637
