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9
10#include <linux/irq.h>
11#include <linux/slab.h>
12
13static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv)
14{
15 int last = urb_priv->length - 1;
16
17 if (last >= 0) {
18 int i;
19 struct td *td;
20
21 for (i = 0; i <= last; i++) {
22 td = urb_priv->td [i];
23 if (td)
24 td_free (hc, td);
25 }
26 }
27
28 list_del (&urb_priv->pending);
29 kfree (urb_priv);
30}
31
32
33
34
35
36
37
38
39static void
40finish_urb(struct ohci_hcd *ohci, struct urb *urb, int status)
41__releases(ohci->lock)
42__acquires(ohci->lock)
43{
44
45
46 urb_free_priv (ohci, urb->hcpriv);
47 urb->hcpriv = NULL;
48 if (likely(status == -EINPROGRESS))
49 status = 0;
50
51 switch (usb_pipetype (urb->pipe)) {
52 case PIPE_ISOCHRONOUS:
53 ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--;
54 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
55 if (quirk_amdiso(ohci))
56 usb_amd_quirk_pll_enable();
57 if (quirk_amdprefetch(ohci))
58 sb800_prefetch(ohci, 0);
59 }
60 break;
61 case PIPE_INTERRUPT:
62 ohci_to_hcd(ohci)->self.bandwidth_int_reqs--;
63 break;
64 }
65
66#ifdef OHCI_VERBOSE_DEBUG
67 urb_print(urb, "RET", usb_pipeout (urb->pipe), status);
68#endif
69
70
71 usb_hcd_unlink_urb_from_ep(ohci_to_hcd(ohci), urb);
72 spin_unlock (&ohci->lock);
73 usb_hcd_giveback_urb(ohci_to_hcd(ohci), urb, status);
74 spin_lock (&ohci->lock);
75
76
77 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0
78 && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0) {
79 ohci->hc_control &= ~(OHCI_CTRL_PLE|OHCI_CTRL_IE);
80 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
81 }
82}
83
84
85
86
87
88
89
90
91
92static int balance (struct ohci_hcd *ohci, int interval, int load)
93{
94 int i, branch = -ENOSPC;
95
96
97 if (interval > NUM_INTS)
98 interval = NUM_INTS;
99
100
101
102
103 for (i = 0; i < interval ; i++) {
104 if (branch < 0 || ohci->load [branch] > ohci->load [i]) {
105 int j;
106
107
108 for (j = i; j < NUM_INTS; j += interval) {
109 if ((ohci->load [j] + load) > 900)
110 break;
111 }
112 if (j < NUM_INTS)
113 continue;
114 branch = i;
115 }
116 }
117 return branch;
118}
119
120
121
122
123
124
125
126static void periodic_link (struct ohci_hcd *ohci, struct ed *ed)
127{
128 unsigned i;
129
130 ohci_vdbg (ohci, "link %sed %p branch %d [%dus.], interval %d\n",
131 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
132 ed, ed->branch, ed->load, ed->interval);
133
134 for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
135 struct ed **prev = &ohci->periodic [i];
136 __hc32 *prev_p = &ohci->hcca->int_table [i];
137 struct ed *here = *prev;
138
139
140
141
142
143 while (here && ed != here) {
144 if (ed->interval > here->interval)
145 break;
146 prev = &here->ed_next;
147 prev_p = &here->hwNextED;
148 here = *prev;
149 }
150 if (ed != here) {
151 ed->ed_next = here;
152 if (here)
153 ed->hwNextED = *prev_p;
154 wmb ();
155 *prev = ed;
156 *prev_p = cpu_to_hc32(ohci, ed->dma);
157 wmb();
158 }
159 ohci->load [i] += ed->load;
160 }
161 ohci_to_hcd(ohci)->self.bandwidth_allocated += ed->load / ed->interval;
162}
163
164
165
166static int ed_schedule (struct ohci_hcd *ohci, struct ed *ed)
167{
168 int branch;
169
170 ed->state = ED_OPER;
171 ed->ed_prev = NULL;
172 ed->ed_next = NULL;
173 ed->hwNextED = 0;
174 if (quirk_zfmicro(ohci)
175 && (ed->type == PIPE_INTERRUPT)
176 && !(ohci->eds_scheduled++))
177 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ));
178 wmb ();
179
180
181
182
183
184
185
186
187
188
189
190 switch (ed->type) {
191 case PIPE_CONTROL:
192 if (ohci->ed_controltail == NULL) {
193 WARN_ON (ohci->hc_control & OHCI_CTRL_CLE);
194 ohci_writel (ohci, ed->dma,
195 &ohci->regs->ed_controlhead);
196 } else {
197 ohci->ed_controltail->ed_next = ed;
198 ohci->ed_controltail->hwNextED = cpu_to_hc32 (ohci,
199 ed->dma);
200 }
201 ed->ed_prev = ohci->ed_controltail;
202 if (!ohci->ed_controltail && !ohci->ed_rm_list) {
203 wmb();
204 ohci->hc_control |= OHCI_CTRL_CLE;
205 ohci_writel (ohci, 0, &ohci->regs->ed_controlcurrent);
206 ohci_writel (ohci, ohci->hc_control,
207 &ohci->regs->control);
208 }
209 ohci->ed_controltail = ed;
210 break;
211
212 case PIPE_BULK:
213 if (ohci->ed_bulktail == NULL) {
214 WARN_ON (ohci->hc_control & OHCI_CTRL_BLE);
215 ohci_writel (ohci, ed->dma, &ohci->regs->ed_bulkhead);
216 } else {
217 ohci->ed_bulktail->ed_next = ed;
218 ohci->ed_bulktail->hwNextED = cpu_to_hc32 (ohci,
219 ed->dma);
220 }
221 ed->ed_prev = ohci->ed_bulktail;
222 if (!ohci->ed_bulktail && !ohci->ed_rm_list) {
223 wmb();
224 ohci->hc_control |= OHCI_CTRL_BLE;
225 ohci_writel (ohci, 0, &ohci->regs->ed_bulkcurrent);
226 ohci_writel (ohci, ohci->hc_control,
227 &ohci->regs->control);
228 }
229 ohci->ed_bulktail = ed;
230 break;
231
232
233
234 default:
235 branch = balance (ohci, ed->interval, ed->load);
236 if (branch < 0) {
237 ohci_dbg (ohci,
238 "ERR %d, interval %d msecs, load %d\n",
239 branch, ed->interval, ed->load);
240
241 return branch;
242 }
243 ed->branch = branch;
244 periodic_link (ohci, ed);
245 }
246
247
248
249
250 return 0;
251}
252
253
254
255
256static void periodic_unlink (struct ohci_hcd *ohci, struct ed *ed)
257{
258 int i;
259
260 for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
261 struct ed *temp;
262 struct ed **prev = &ohci->periodic [i];
263 __hc32 *prev_p = &ohci->hcca->int_table [i];
264
265 while (*prev && (temp = *prev) != ed) {
266 prev_p = &temp->hwNextED;
267 prev = &temp->ed_next;
268 }
269 if (*prev) {
270 *prev_p = ed->hwNextED;
271 *prev = ed->ed_next;
272 }
273 ohci->load [i] -= ed->load;
274 }
275 ohci_to_hcd(ohci)->self.bandwidth_allocated -= ed->load / ed->interval;
276
277 ohci_vdbg (ohci, "unlink %sed %p branch %d [%dus.], interval %d\n",
278 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
279 ed, ed->branch, ed->load, ed->interval);
280}
281
282
283
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285
286
287
288
289
290
291
292
293
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295
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298
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302
303
304static void ed_deschedule (struct ohci_hcd *ohci, struct ed *ed)
305{
306 ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
307 wmb ();
308 ed->state = ED_UNLINK;
309
310
311
312
313
314
315
316
317
318
319
320 switch (ed->type) {
321 case PIPE_CONTROL:
322
323 if (ed->ed_prev == NULL) {
324 if (!ed->hwNextED) {
325 ohci->hc_control &= ~OHCI_CTRL_CLE;
326 ohci_writel (ohci, ohci->hc_control,
327 &ohci->regs->control);
328
329 } else
330 ohci_writel (ohci,
331 hc32_to_cpup (ohci, &ed->hwNextED),
332 &ohci->regs->ed_controlhead);
333 } else {
334 ed->ed_prev->ed_next = ed->ed_next;
335 ed->ed_prev->hwNextED = ed->hwNextED;
336 }
337
338 if (ohci->ed_controltail == ed) {
339 ohci->ed_controltail = ed->ed_prev;
340 if (ohci->ed_controltail)
341 ohci->ed_controltail->ed_next = NULL;
342 } else if (ed->ed_next) {
343 ed->ed_next->ed_prev = ed->ed_prev;
344 }
345 break;
346
347 case PIPE_BULK:
348
349 if (ed->ed_prev == NULL) {
350 if (!ed->hwNextED) {
351 ohci->hc_control &= ~OHCI_CTRL_BLE;
352 ohci_writel (ohci, ohci->hc_control,
353 &ohci->regs->control);
354
355 } else
356 ohci_writel (ohci,
357 hc32_to_cpup (ohci, &ed->hwNextED),
358 &ohci->regs->ed_bulkhead);
359 } else {
360 ed->ed_prev->ed_next = ed->ed_next;
361 ed->ed_prev->hwNextED = ed->hwNextED;
362 }
363
364 if (ohci->ed_bulktail == ed) {
365 ohci->ed_bulktail = ed->ed_prev;
366 if (ohci->ed_bulktail)
367 ohci->ed_bulktail->ed_next = NULL;
368 } else if (ed->ed_next) {
369 ed->ed_next->ed_prev = ed->ed_prev;
370 }
371 break;
372
373
374
375 default:
376 periodic_unlink (ohci, ed);
377 break;
378 }
379}
380
381
382
383
384
385
386
387static struct ed *ed_get (
388 struct ohci_hcd *ohci,
389 struct usb_host_endpoint *ep,
390 struct usb_device *udev,
391 unsigned int pipe,
392 int interval
393) {
394 struct ed *ed;
395 unsigned long flags;
396
397 spin_lock_irqsave (&ohci->lock, flags);
398
399 if (!(ed = ep->hcpriv)) {
400 struct td *td;
401 int is_out;
402 u32 info;
403
404 ed = ed_alloc (ohci, GFP_ATOMIC);
405 if (!ed) {
406
407 goto done;
408 }
409
410
411 td = td_alloc (ohci, GFP_ATOMIC);
412 if (!td) {
413
414 ed_free (ohci, ed);
415 ed = NULL;
416 goto done;
417 }
418 ed->dummy = td;
419 ed->hwTailP = cpu_to_hc32 (ohci, td->td_dma);
420 ed->hwHeadP = ed->hwTailP;
421 ed->state = ED_IDLE;
422
423 is_out = !(ep->desc.bEndpointAddress & USB_DIR_IN);
424
425
426
427
428 info = usb_pipedevice (pipe);
429 ed->type = usb_pipetype(pipe);
430
431 info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << 7;
432 info |= usb_endpoint_maxp(&ep->desc) << 16;
433 if (udev->speed == USB_SPEED_LOW)
434 info |= ED_LOWSPEED;
435
436 if (ed->type != PIPE_CONTROL) {
437 info |= is_out ? ED_OUT : ED_IN;
438 if (ed->type != PIPE_BULK) {
439
440 if (ed->type == PIPE_ISOCHRONOUS)
441 info |= ED_ISO;
442 else if (interval > 32)
443 interval = 32;
444 ed->interval = interval;
445 ed->load = usb_calc_bus_time (
446 udev->speed, !is_out,
447 ed->type == PIPE_ISOCHRONOUS,
448 usb_endpoint_maxp(&ep->desc))
449 / 1000;
450 }
451 }
452 ed->hwINFO = cpu_to_hc32(ohci, info);
453
454 ep->hcpriv = ed;
455 }
456
457done:
458 spin_unlock_irqrestore (&ohci->lock, flags);
459 return ed;
460}
461
462
463
464
465
466
467
468
469
470static void start_ed_unlink (struct ohci_hcd *ohci, struct ed *ed)
471{
472 ed->hwINFO |= cpu_to_hc32 (ohci, ED_DEQUEUE);
473 ed_deschedule (ohci, ed);
474
475
476 ed->ed_next = ohci->ed_rm_list;
477 ed->ed_prev = NULL;
478 ohci->ed_rm_list = ed;
479
480
481 ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrstatus);
482 ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrenable);
483
484 (void) ohci_readl (ohci, &ohci->regs->control);
485
486
487
488
489
490
491 ed->tick = ohci_frame_no(ohci) + 1;
492
493}
494
495
496
497
498
499
500
501static void
502td_fill (struct ohci_hcd *ohci, u32 info,
503 dma_addr_t data, int len,
504 struct urb *urb, int index)
505{
506 struct td *td, *td_pt;
507 struct urb_priv *urb_priv = urb->hcpriv;
508 int is_iso = info & TD_ISO;
509 int hash;
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524 if (index != (urb_priv->length - 1)
525 || (urb->transfer_flags & URB_NO_INTERRUPT))
526 info |= TD_DI_SET (6);
527
528
529 td_pt = urb_priv->td [index];
530
531
532 td = urb_priv->td [index] = urb_priv->ed->dummy;
533 urb_priv->ed->dummy = td_pt;
534
535 td->ed = urb_priv->ed;
536 td->next_dl_td = NULL;
537 td->index = index;
538 td->urb = urb;
539 td->data_dma = data;
540 if (!len)
541 data = 0;
542
543 td->hwINFO = cpu_to_hc32 (ohci, info);
544 if (is_iso) {
545 td->hwCBP = cpu_to_hc32 (ohci, data & 0xFFFFF000);
546 *ohci_hwPSWp(ohci, td, 0) = cpu_to_hc16 (ohci,
547 (data & 0x0FFF) | 0xE000);
548 td->ed->last_iso = info & 0xffff;
549 } else {
550 td->hwCBP = cpu_to_hc32 (ohci, data);
551 }
552 if (data)
553 td->hwBE = cpu_to_hc32 (ohci, data + len - 1);
554 else
555 td->hwBE = 0;
556 td->hwNextTD = cpu_to_hc32 (ohci, td_pt->td_dma);
557
558
559 list_add_tail (&td->td_list, &td->ed->td_list);
560
561
562 hash = TD_HASH_FUNC (td->td_dma);
563 td->td_hash = ohci->td_hash [hash];
564 ohci->td_hash [hash] = td;
565
566
567 wmb ();
568 td->ed->hwTailP = td->hwNextTD;
569}
570
571
572
573
574
575
576
577
578static void td_submit_urb (
579 struct ohci_hcd *ohci,
580 struct urb *urb
581) {
582 struct urb_priv *urb_priv = urb->hcpriv;
583 dma_addr_t data;
584 int data_len = urb->transfer_buffer_length;
585 int cnt = 0;
586 u32 info = 0;
587 int is_out = usb_pipeout (urb->pipe);
588 int periodic = 0;
589
590
591
592
593
594 if (!usb_gettoggle (urb->dev, usb_pipeendpoint (urb->pipe), is_out)) {
595 usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe),
596 is_out, 1);
597 urb_priv->ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_C);
598 }
599
600 list_add (&urb_priv->pending, &ohci->pending);
601
602 if (data_len)
603 data = urb->transfer_dma;
604 else
605 data = 0;
606
607
608
609
610
611 switch (urb_priv->ed->type) {
612
613
614
615
616 case PIPE_INTERRUPT:
617
618 periodic = ohci_to_hcd(ohci)->self.bandwidth_int_reqs++ == 0
619 && ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0;
620
621 case PIPE_BULK:
622 info = is_out
623 ? TD_T_TOGGLE | TD_CC | TD_DP_OUT
624 : TD_T_TOGGLE | TD_CC | TD_DP_IN;
625
626 while (data_len > 4096) {
627 td_fill (ohci, info, data, 4096, urb, cnt);
628 data += 4096;
629 data_len -= 4096;
630 cnt++;
631 }
632
633 if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
634 info |= TD_R;
635 td_fill (ohci, info, data, data_len, urb, cnt);
636 cnt++;
637 if ((urb->transfer_flags & URB_ZERO_PACKET)
638 && cnt < urb_priv->length) {
639 td_fill (ohci, info, 0, 0, urb, cnt);
640 cnt++;
641 }
642
643 if (urb_priv->ed->type == PIPE_BULK) {
644 wmb ();
645 ohci_writel (ohci, OHCI_BLF, &ohci->regs->cmdstatus);
646 }
647 break;
648
649
650
651
652 case PIPE_CONTROL:
653 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
654 td_fill (ohci, info, urb->setup_dma, 8, urb, cnt++);
655 if (data_len > 0) {
656 info = TD_CC | TD_R | TD_T_DATA1;
657 info |= is_out ? TD_DP_OUT : TD_DP_IN;
658
659 td_fill (ohci, info, data, data_len, urb, cnt++);
660 }
661 info = (is_out || data_len == 0)
662 ? TD_CC | TD_DP_IN | TD_T_DATA1
663 : TD_CC | TD_DP_OUT | TD_T_DATA1;
664 td_fill (ohci, info, data, 0, urb, cnt++);
665
666 wmb ();
667 ohci_writel (ohci, OHCI_CLF, &ohci->regs->cmdstatus);
668 break;
669
670
671
672
673
674 case PIPE_ISOCHRONOUS:
675 for (cnt = urb_priv->td_cnt; cnt < urb->number_of_packets;
676 cnt++) {
677 int frame = urb->start_frame;
678
679
680
681
682 frame += cnt * urb->interval;
683 frame &= 0xffff;
684 td_fill (ohci, TD_CC | TD_ISO | frame,
685 data + urb->iso_frame_desc [cnt].offset,
686 urb->iso_frame_desc [cnt].length, urb, cnt);
687 }
688 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
689 if (quirk_amdiso(ohci))
690 usb_amd_quirk_pll_disable();
691 if (quirk_amdprefetch(ohci))
692 sb800_prefetch(ohci, 1);
693 }
694 periodic = ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs++ == 0
695 && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0;
696 break;
697 }
698
699
700 if (periodic) {
701 wmb ();
702 ohci->hc_control |= OHCI_CTRL_PLE|OHCI_CTRL_IE;
703 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
704 }
705
706
707}
708
709
710
711
712
713
714static int td_done(struct ohci_hcd *ohci, struct urb *urb, struct td *td)
715{
716 u32 tdINFO = hc32_to_cpup (ohci, &td->hwINFO);
717 int cc = 0;
718 int status = -EINPROGRESS;
719
720 list_del (&td->td_list);
721
722
723 if (tdINFO & TD_ISO) {
724 u16 tdPSW = ohci_hwPSW(ohci, td, 0);
725 int dlen = 0;
726
727
728
729
730
731 cc = (tdPSW >> 12) & 0xF;
732 if (tdINFO & TD_CC)
733 return status;
734
735 if (usb_pipeout (urb->pipe))
736 dlen = urb->iso_frame_desc [td->index].length;
737 else {
738
739 if (cc == TD_DATAUNDERRUN)
740 cc = TD_CC_NOERROR;
741 dlen = tdPSW & 0x3ff;
742 }
743 urb->actual_length += dlen;
744 urb->iso_frame_desc [td->index].actual_length = dlen;
745 urb->iso_frame_desc [td->index].status = cc_to_error [cc];
746
747 if (cc != TD_CC_NOERROR)
748 ohci_vdbg (ohci,
749 "urb %p iso td %p (%d) len %d cc %d\n",
750 urb, td, 1 + td->index, dlen, cc);
751
752
753
754
755
756 } else {
757 int type = usb_pipetype (urb->pipe);
758 u32 tdBE = hc32_to_cpup (ohci, &td->hwBE);
759
760 cc = TD_CC_GET (tdINFO);
761
762
763 if (cc == TD_DATAUNDERRUN
764 && !(urb->transfer_flags & URB_SHORT_NOT_OK))
765 cc = TD_CC_NOERROR;
766 if (cc != TD_CC_NOERROR && cc < 0x0E)
767 status = cc_to_error[cc];
768
769
770 if ((type != PIPE_CONTROL || td->index != 0) && tdBE != 0) {
771 if (td->hwCBP == 0)
772 urb->actual_length += tdBE - td->data_dma + 1;
773 else
774 urb->actual_length +=
775 hc32_to_cpup (ohci, &td->hwCBP)
776 - td->data_dma;
777 }
778
779 if (cc != TD_CC_NOERROR && cc < 0x0E)
780 ohci_vdbg (ohci,
781 "urb %p td %p (%d) cc %d, len=%d/%d\n",
782 urb, td, 1 + td->index, cc,
783 urb->actual_length,
784 urb->transfer_buffer_length);
785 }
786 return status;
787}
788
789
790
791static void ed_halted(struct ohci_hcd *ohci, struct td *td, int cc)
792{
793 struct urb *urb = td->urb;
794 urb_priv_t *urb_priv = urb->hcpriv;
795 struct ed *ed = td->ed;
796 struct list_head *tmp = td->td_list.next;
797 __hc32 toggle = ed->hwHeadP & cpu_to_hc32 (ohci, ED_C);
798
799
800
801
802 ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
803 wmb ();
804 ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_H);
805
806
807
808
809
810 while (tmp != &ed->td_list) {
811 struct td *next;
812
813 next = list_entry (tmp, struct td, td_list);
814 tmp = next->td_list.next;
815
816 if (next->urb != urb)
817 break;
818
819
820
821
822
823
824
825
826
827 list_del(&next->td_list);
828 urb_priv->td_cnt++;
829 ed->hwHeadP = next->hwNextTD | toggle;
830 }
831
832
833
834
835
836 switch (cc) {
837 case TD_DATAUNDERRUN:
838 if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
839 break;
840
841 case TD_CC_STALL:
842 if (usb_pipecontrol (urb->pipe))
843 break;
844
845 default:
846 ohci_dbg (ohci,
847 "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
848 urb, urb->dev->devpath,
849 usb_pipeendpoint (urb->pipe),
850 usb_pipein (urb->pipe) ? "in" : "out",
851 hc32_to_cpu (ohci, td->hwINFO),
852 cc, cc_to_error [cc]);
853 }
854}
855
856
857
858
859static struct td *dl_reverse_done_list (struct ohci_hcd *ohci)
860{
861 u32 td_dma;
862 struct td *td_rev = NULL;
863 struct td *td = NULL;
864
865 td_dma = hc32_to_cpup (ohci, &ohci->hcca->done_head);
866 ohci->hcca->done_head = 0;
867 wmb();
868
869
870
871
872 while (td_dma) {
873 int cc;
874
875 td = dma_to_td (ohci, td_dma);
876 if (!td) {
877 ohci_err (ohci, "bad entry %8x\n", td_dma);
878 break;
879 }
880
881 td->hwINFO |= cpu_to_hc32 (ohci, TD_DONE);
882 cc = TD_CC_GET (hc32_to_cpup (ohci, &td->hwINFO));
883
884
885
886
887
888 if (cc != TD_CC_NOERROR
889 && (td->ed->hwHeadP & cpu_to_hc32 (ohci, ED_H)))
890 ed_halted(ohci, td, cc);
891
892 td->next_dl_td = td_rev;
893 td_rev = td;
894 td_dma = hc32_to_cpup (ohci, &td->hwNextTD);
895 }
896 return td_rev;
897}
898
899
900
901
902static void
903finish_unlinks (struct ohci_hcd *ohci, u16 tick)
904{
905 struct ed *ed, **last;
906
907rescan_all:
908 for (last = &ohci->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
909 struct list_head *entry, *tmp;
910 int completed, modified;
911 __hc32 *prev;
912
913
914
915
916 if (likely(ohci->rh_state == OHCI_RH_RUNNING)) {
917 if (tick_before (tick, ed->tick)) {
918skip_ed:
919 last = &ed->ed_next;
920 continue;
921 }
922
923 if (!list_empty (&ed->td_list)) {
924 struct td *td;
925 u32 head;
926
927 td = list_entry (ed->td_list.next, struct td,
928 td_list);
929 head = hc32_to_cpu (ohci, ed->hwHeadP) &
930 TD_MASK;
931
932
933 if (td->td_dma != head) {
934 if (ed == ohci->ed_to_check)
935 ohci->ed_to_check = NULL;
936 else
937 goto skip_ed;
938 }
939 }
940 }
941
942
943
944
945
946 *last = ed->ed_next;
947 ed->ed_next = NULL;
948 modified = 0;
949
950
951
952
953
954
955
956
957
958rescan_this:
959 completed = 0;
960 prev = &ed->hwHeadP;
961 list_for_each_safe (entry, tmp, &ed->td_list) {
962 struct td *td;
963 struct urb *urb;
964 urb_priv_t *urb_priv;
965 __hc32 savebits;
966 u32 tdINFO;
967
968 td = list_entry (entry, struct td, td_list);
969 urb = td->urb;
970 urb_priv = td->urb->hcpriv;
971
972 if (!urb->unlinked) {
973 prev = &td->hwNextTD;
974 continue;
975 }
976
977
978 savebits = *prev & ~cpu_to_hc32 (ohci, TD_MASK);
979 *prev = td->hwNextTD | savebits;
980
981
982
983
984
985
986 tdINFO = hc32_to_cpup(ohci, &td->hwINFO);
987 if ((tdINFO & TD_T) == TD_T_DATA0)
988 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_C);
989 else if ((tdINFO & TD_T) == TD_T_DATA1)
990 ed->hwHeadP |= cpu_to_hc32(ohci, ED_C);
991
992
993 td_done (ohci, urb, td);
994 urb_priv->td_cnt++;
995
996
997 if (urb_priv->td_cnt == urb_priv->length) {
998 modified = completed = 1;
999 finish_urb(ohci, urb, 0);
1000 }
1001 }
1002 if (completed && !list_empty (&ed->td_list))
1003 goto rescan_this;
1004
1005
1006 ed->state = ED_IDLE;
1007 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
1008 ohci->eds_scheduled--;
1009 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_H);
1010 ed->hwNextED = 0;
1011 wmb ();
1012 ed->hwINFO &= ~cpu_to_hc32 (ohci, ED_SKIP | ED_DEQUEUE);
1013
1014
1015 if (!list_empty (&ed->td_list)) {
1016 if (ohci->rh_state == OHCI_RH_RUNNING)
1017 ed_schedule (ohci, ed);
1018 }
1019
1020 if (modified)
1021 goto rescan_all;
1022 }
1023
1024
1025 if (ohci->rh_state == OHCI_RH_RUNNING && !ohci->ed_rm_list) {
1026 u32 command = 0, control = 0;
1027
1028 if (ohci->ed_controltail) {
1029 command |= OHCI_CLF;
1030 if (quirk_zfmicro(ohci))
1031 mdelay(1);
1032 if (!(ohci->hc_control & OHCI_CTRL_CLE)) {
1033 control |= OHCI_CTRL_CLE;
1034 ohci_writel (ohci, 0,
1035 &ohci->regs->ed_controlcurrent);
1036 }
1037 }
1038 if (ohci->ed_bulktail) {
1039 command |= OHCI_BLF;
1040 if (quirk_zfmicro(ohci))
1041 mdelay(1);
1042 if (!(ohci->hc_control & OHCI_CTRL_BLE)) {
1043 control |= OHCI_CTRL_BLE;
1044 ohci_writel (ohci, 0,
1045 &ohci->regs->ed_bulkcurrent);
1046 }
1047 }
1048
1049
1050 if (control) {
1051 ohci->hc_control |= control;
1052 if (quirk_zfmicro(ohci))
1053 mdelay(1);
1054 ohci_writel (ohci, ohci->hc_control,
1055 &ohci->regs->control);
1056 }
1057 if (command) {
1058 if (quirk_zfmicro(ohci))
1059 mdelay(1);
1060 ohci_writel (ohci, command, &ohci->regs->cmdstatus);
1061 }
1062 }
1063}
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075static void takeback_td(struct ohci_hcd *ohci, struct td *td)
1076{
1077 struct urb *urb = td->urb;
1078 urb_priv_t *urb_priv = urb->hcpriv;
1079 struct ed *ed = td->ed;
1080 int status;
1081
1082
1083 status = td_done(ohci, urb, td);
1084 urb_priv->td_cnt++;
1085
1086
1087 if (urb_priv->td_cnt == urb_priv->length)
1088 finish_urb(ohci, urb, status);
1089
1090
1091 if (list_empty(&ed->td_list)) {
1092 if (ed->state == ED_OPER)
1093 start_ed_unlink(ohci, ed);
1094
1095
1096 } else if ((ed->hwINFO & cpu_to_hc32(ohci, ED_SKIP | ED_DEQUEUE))
1097 == cpu_to_hc32(ohci, ED_SKIP)) {
1098 td = list_entry(ed->td_list.next, struct td, td_list);
1099 if (!(td->hwINFO & cpu_to_hc32(ohci, TD_DONE))) {
1100 ed->hwINFO &= ~cpu_to_hc32(ohci, ED_SKIP);
1101
1102 switch (ed->type) {
1103 case PIPE_CONTROL:
1104 ohci_writel(ohci, OHCI_CLF,
1105 &ohci->regs->cmdstatus);
1106 break;
1107 case PIPE_BULK:
1108 ohci_writel(ohci, OHCI_BLF,
1109 &ohci->regs->cmdstatus);
1110 break;
1111 }
1112 }
1113 }
1114}
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125static void
1126dl_done_list (struct ohci_hcd *ohci)
1127{
1128 struct td *td = dl_reverse_done_list (ohci);
1129
1130 while (td) {
1131 struct td *td_next = td->next_dl_td;
1132 struct ed *ed = td->ed;
1133
1134
1135
1136
1137
1138
1139
1140
1141 for (;;) {
1142 struct td *td2;
1143
1144 td2 = list_first_entry(&ed->td_list, struct td,
1145 td_list);
1146 if (td2 == td)
1147 break;
1148 takeback_td(ohci, td2);
1149 }
1150
1151 takeback_td(ohci, td);
1152 td = td_next;
1153 }
1154}
1155