1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92#include <linux/module.h>
93#include <linux/kernel.h>
94#include <linux/sched.h>
95#include <linux/slab.h>
96#include <linux/init.h>
97#include <linux/list.h>
98#include <linux/kobject.h>
99#include <linux/prefetch.h>
100#include <linux/platform_device.h>
101#include <linux/io.h>
102#include <linux/idr.h>
103#include <linux/dma-mapping.h>
104
105#include "musb_core.h"
106
107#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
108
109
110#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
111#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
112
113#define MUSB_VERSION "6.0"
114
115#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
116
117#define MUSB_DRIVER_NAME "musb-hdrc"
118const char musb_driver_name[] = MUSB_DRIVER_NAME;
119
120MODULE_DESCRIPTION(DRIVER_INFO);
121MODULE_AUTHOR(DRIVER_AUTHOR);
122MODULE_LICENSE("GPL");
123MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
124
125
126
127
128static inline struct musb *dev_to_musb(struct device *dev)
129{
130 return dev_get_drvdata(dev);
131}
132
133
134
135#ifndef CONFIG_BLACKFIN
136static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
137{
138 void __iomem *addr = phy->io_priv;
139 int i = 0;
140 u8 r;
141 u8 power;
142 int ret;
143
144 pm_runtime_get_sync(phy->io_dev);
145
146
147 power = musb_readb(addr, MUSB_POWER);
148 power &= ~MUSB_POWER_SUSPENDM;
149 musb_writeb(addr, MUSB_POWER, power);
150
151
152
153
154
155 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
156 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
157 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
158
159 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
160 & MUSB_ULPI_REG_CMPLT)) {
161 i++;
162 if (i == 10000) {
163 ret = -ETIMEDOUT;
164 goto out;
165 }
166
167 }
168 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
169 r &= ~MUSB_ULPI_REG_CMPLT;
170 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
171
172 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
173
174out:
175 pm_runtime_put(phy->io_dev);
176
177 return ret;
178}
179
180static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)
181{
182 void __iomem *addr = phy->io_priv;
183 int i = 0;
184 u8 r = 0;
185 u8 power;
186 int ret = 0;
187
188 pm_runtime_get_sync(phy->io_dev);
189
190
191 power = musb_readb(addr, MUSB_POWER);
192 power &= ~MUSB_POWER_SUSPENDM;
193 musb_writeb(addr, MUSB_POWER, power);
194
195 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
196 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
197 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
198
199 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
200 & MUSB_ULPI_REG_CMPLT)) {
201 i++;
202 if (i == 10000) {
203 ret = -ETIMEDOUT;
204 goto out;
205 }
206 }
207
208 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
209 r &= ~MUSB_ULPI_REG_CMPLT;
210 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
211
212out:
213 pm_runtime_put(phy->io_dev);
214
215 return ret;
216}
217#else
218#define musb_ulpi_read NULL
219#define musb_ulpi_write NULL
220#endif
221
222static struct usb_phy_io_ops musb_ulpi_access = {
223 .read = musb_ulpi_read,
224 .write = musb_ulpi_write,
225};
226
227
228
229#if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
230
231
232
233
234void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
235{
236 struct musb *musb = hw_ep->musb;
237 void __iomem *fifo = hw_ep->fifo;
238
239 if (unlikely(len == 0))
240 return;
241
242 prefetch((u8 *)src);
243
244 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
245 'T', hw_ep->epnum, fifo, len, src);
246
247
248 if (likely((0x01 & (unsigned long) src) == 0)) {
249 u16 index = 0;
250
251
252 if ((0x02 & (unsigned long) src) == 0) {
253 if (len >= 4) {
254 iowrite32_rep(fifo, src + index, len >> 2);
255 index += len & ~0x03;
256 }
257 if (len & 0x02) {
258 musb_writew(fifo, 0, *(u16 *)&src[index]);
259 index += 2;
260 }
261 } else {
262 if (len >= 2) {
263 iowrite16_rep(fifo, src + index, len >> 1);
264 index += len & ~0x01;
265 }
266 }
267 if (len & 0x01)
268 musb_writeb(fifo, 0, src[index]);
269 } else {
270
271 iowrite8_rep(fifo, src, len);
272 }
273}
274
275#if !defined(CONFIG_USB_MUSB_AM35X)
276
277
278
279void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
280{
281 struct musb *musb = hw_ep->musb;
282 void __iomem *fifo = hw_ep->fifo;
283
284 if (unlikely(len == 0))
285 return;
286
287 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
288 'R', hw_ep->epnum, fifo, len, dst);
289
290
291 if (likely((0x01 & (unsigned long) dst) == 0)) {
292 u16 index = 0;
293
294
295 if ((0x02 & (unsigned long) dst) == 0) {
296 if (len >= 4) {
297 ioread32_rep(fifo, dst, len >> 2);
298 index = len & ~0x03;
299 }
300 if (len & 0x02) {
301 *(u16 *)&dst[index] = musb_readw(fifo, 0);
302 index += 2;
303 }
304 } else {
305 if (len >= 2) {
306 ioread16_rep(fifo, dst, len >> 1);
307 index = len & ~0x01;
308 }
309 }
310 if (len & 0x01)
311 dst[index] = musb_readb(fifo, 0);
312 } else {
313
314 ioread8_rep(fifo, dst, len);
315 }
316}
317#endif
318
319#endif
320
321
322
323
324
325static const u8 musb_test_packet[53] = {
326
327
328
329 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
330
331 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
332
333 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
334
335 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
336
337 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
338
339 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
340
341
342};
343
344void musb_load_testpacket(struct musb *musb)
345{
346 void __iomem *regs = musb->endpoints[0].regs;
347
348 musb_ep_select(musb->mregs, 0);
349 musb_write_fifo(musb->control_ep,
350 sizeof(musb_test_packet), musb_test_packet);
351 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
352}
353
354
355
356
357
358
359static void musb_otg_timer_func(unsigned long data)
360{
361 struct musb *musb = (struct musb *)data;
362 unsigned long flags;
363
364 spin_lock_irqsave(&musb->lock, flags);
365 switch (musb->xceiv->state) {
366 case OTG_STATE_B_WAIT_ACON:
367 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
368 musb_g_disconnect(musb);
369 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
370 musb->is_active = 0;
371 break;
372 case OTG_STATE_A_SUSPEND:
373 case OTG_STATE_A_WAIT_BCON:
374 dev_dbg(musb->controller, "HNP: %s timeout\n",
375 usb_otg_state_string(musb->xceiv->state));
376 musb_platform_set_vbus(musb, 0);
377 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
378 break;
379 default:
380 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
381 usb_otg_state_string(musb->xceiv->state));
382 }
383 musb->ignore_disconnect = 0;
384 spin_unlock_irqrestore(&musb->lock, flags);
385}
386
387
388
389
390void musb_hnp_stop(struct musb *musb)
391{
392 struct usb_hcd *hcd = musb_to_hcd(musb);
393 void __iomem *mbase = musb->mregs;
394 u8 reg;
395
396 dev_dbg(musb->controller, "HNP: stop from %s\n",
397 usb_otg_state_string(musb->xceiv->state));
398
399 switch (musb->xceiv->state) {
400 case OTG_STATE_A_PERIPHERAL:
401 musb_g_disconnect(musb);
402 dev_dbg(musb->controller, "HNP: back to %s\n",
403 usb_otg_state_string(musb->xceiv->state));
404 break;
405 case OTG_STATE_B_HOST:
406 dev_dbg(musb->controller, "HNP: Disabling HR\n");
407 hcd->self.is_b_host = 0;
408 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
409 MUSB_DEV_MODE(musb);
410 reg = musb_readb(mbase, MUSB_POWER);
411 reg |= MUSB_POWER_SUSPENDM;
412 musb_writeb(mbase, MUSB_POWER, reg);
413
414 break;
415 default:
416 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
417 usb_otg_state_string(musb->xceiv->state));
418 }
419
420
421
422
423
424
425 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
426}
427
428
429
430
431
432
433
434
435
436
437
438
439
440static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
441 u8 devctl)
442{
443 struct usb_otg *otg = musb->xceiv->otg;
444 irqreturn_t handled = IRQ_NONE;
445
446 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
447 int_usb);
448
449
450
451
452
453 if (int_usb & MUSB_INTR_RESUME) {
454 handled = IRQ_HANDLED;
455 dev_dbg(musb->controller, "RESUME (%s)\n", usb_otg_state_string(musb->xceiv->state));
456
457 if (devctl & MUSB_DEVCTL_HM) {
458 void __iomem *mbase = musb->mregs;
459 u8 power;
460
461 switch (musb->xceiv->state) {
462 case OTG_STATE_A_SUSPEND:
463
464
465
466
467 power = musb_readb(musb->mregs, MUSB_POWER);
468 if (power & MUSB_POWER_SUSPENDM) {
469
470 musb->int_usb &= ~MUSB_INTR_SUSPEND;
471 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
472 break;
473 }
474
475 power &= ~MUSB_POWER_SUSPENDM;
476 musb_writeb(mbase, MUSB_POWER,
477 power | MUSB_POWER_RESUME);
478
479 musb->port1_status |=
480 (USB_PORT_STAT_C_SUSPEND << 16)
481 | MUSB_PORT_STAT_RESUME;
482 musb->rh_timer = jiffies
483 + msecs_to_jiffies(20);
484
485 musb->xceiv->state = OTG_STATE_A_HOST;
486 musb->is_active = 1;
487 usb_hcd_resume_root_hub(musb_to_hcd(musb));
488 break;
489 case OTG_STATE_B_WAIT_ACON:
490 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
491 musb->is_active = 1;
492 MUSB_DEV_MODE(musb);
493 break;
494 default:
495 WARNING("bogus %s RESUME (%s)\n",
496 "host",
497 usb_otg_state_string(musb->xceiv->state));
498 }
499 } else {
500 switch (musb->xceiv->state) {
501 case OTG_STATE_A_SUSPEND:
502
503 musb->xceiv->state = OTG_STATE_A_HOST;
504 usb_hcd_resume_root_hub(musb_to_hcd(musb));
505 break;
506 case OTG_STATE_B_WAIT_ACON:
507 case OTG_STATE_B_PERIPHERAL:
508
509
510
511 if ((devctl & MUSB_DEVCTL_VBUS)
512 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
513 ) {
514 musb->int_usb |= MUSB_INTR_DISCONNECT;
515 musb->int_usb &= ~MUSB_INTR_SUSPEND;
516 break;
517 }
518 musb_g_resume(musb);
519 break;
520 case OTG_STATE_B_IDLE:
521 musb->int_usb &= ~MUSB_INTR_SUSPEND;
522 break;
523 default:
524 WARNING("bogus %s RESUME (%s)\n",
525 "peripheral",
526 usb_otg_state_string(musb->xceiv->state));
527 }
528 }
529 }
530
531
532 if (int_usb & MUSB_INTR_SESSREQ) {
533 void __iomem *mbase = musb->mregs;
534
535 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
536 && (devctl & MUSB_DEVCTL_BDEVICE)) {
537 dev_dbg(musb->controller, "SessReq while on B state\n");
538 return IRQ_HANDLED;
539 }
540
541 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
542 usb_otg_state_string(musb->xceiv->state));
543
544
545
546
547
548
549
550
551 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
552 musb->ep0_stage = MUSB_EP0_START;
553 musb->xceiv->state = OTG_STATE_A_IDLE;
554 MUSB_HST_MODE(musb);
555 musb_platform_set_vbus(musb, 1);
556
557 handled = IRQ_HANDLED;
558 }
559
560 if (int_usb & MUSB_INTR_VBUSERROR) {
561 int ignore = 0;
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579 switch (musb->xceiv->state) {
580 case OTG_STATE_A_HOST:
581
582
583
584
585
586
587 case OTG_STATE_A_WAIT_BCON:
588 case OTG_STATE_A_WAIT_VRISE:
589 if (musb->vbuserr_retry) {
590 void __iomem *mbase = musb->mregs;
591
592 musb->vbuserr_retry--;
593 ignore = 1;
594 devctl |= MUSB_DEVCTL_SESSION;
595 musb_writeb(mbase, MUSB_DEVCTL, devctl);
596 } else {
597 musb->port1_status |=
598 USB_PORT_STAT_OVERCURRENT
599 | (USB_PORT_STAT_C_OVERCURRENT << 16);
600 }
601 break;
602 default:
603 break;
604 }
605
606 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
607 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
608 usb_otg_state_string(musb->xceiv->state),
609 devctl,
610 ({ char *s;
611 switch (devctl & MUSB_DEVCTL_VBUS) {
612 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
613 s = "<SessEnd"; break;
614 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
615 s = "<AValid"; break;
616 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
617 s = "<VBusValid"; break;
618
619 default:
620 s = "VALID"; break;
621 }; s; }),
622 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
623 musb->port1_status);
624
625
626 if (!ignore)
627 musb_platform_set_vbus(musb, 0);
628 handled = IRQ_HANDLED;
629 }
630
631 if (int_usb & MUSB_INTR_SUSPEND) {
632 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
633 usb_otg_state_string(musb->xceiv->state), devctl);
634 handled = IRQ_HANDLED;
635
636 switch (musb->xceiv->state) {
637 case OTG_STATE_A_PERIPHERAL:
638
639
640
641
642
643
644
645 musb_hnp_stop(musb);
646 usb_hcd_resume_root_hub(musb_to_hcd(musb));
647 musb_root_disconnect(musb);
648 musb_platform_try_idle(musb, jiffies
649 + msecs_to_jiffies(musb->a_wait_bcon
650 ? : OTG_TIME_A_WAIT_BCON));
651
652 break;
653 case OTG_STATE_B_IDLE:
654 if (!musb->is_active)
655 break;
656 case OTG_STATE_B_PERIPHERAL:
657 musb_g_suspend(musb);
658 musb->is_active = otg->gadget->b_hnp_enable;
659 if (musb->is_active) {
660 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
661 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
662 mod_timer(&musb->otg_timer, jiffies
663 + msecs_to_jiffies(
664 OTG_TIME_B_ASE0_BRST));
665 }
666 break;
667 case OTG_STATE_A_WAIT_BCON:
668 if (musb->a_wait_bcon != 0)
669 musb_platform_try_idle(musb, jiffies
670 + msecs_to_jiffies(musb->a_wait_bcon));
671 break;
672 case OTG_STATE_A_HOST:
673 musb->xceiv->state = OTG_STATE_A_SUSPEND;
674 musb->is_active = otg->host->b_hnp_enable;
675 break;
676 case OTG_STATE_B_HOST:
677
678 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
679 break;
680 default:
681
682 musb->is_active = 0;
683 break;
684 }
685 }
686
687 if (int_usb & MUSB_INTR_CONNECT) {
688 struct usb_hcd *hcd = musb_to_hcd(musb);
689
690 handled = IRQ_HANDLED;
691 musb->is_active = 1;
692
693 musb->ep0_stage = MUSB_EP0_START;
694
695
696 if (is_peripheral_active(musb)) {
697
698 }
699 musb->intrtxe = musb->epmask;
700 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
701 musb->intrrxe = musb->epmask & 0xfffe;
702 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
703 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
704 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
705 |USB_PORT_STAT_HIGH_SPEED
706 |USB_PORT_STAT_ENABLE
707 );
708 musb->port1_status |= USB_PORT_STAT_CONNECTION
709 |(USB_PORT_STAT_C_CONNECTION << 16);
710
711
712 if (devctl & MUSB_DEVCTL_LSDEV)
713 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
714
715
716 switch (musb->xceiv->state) {
717 case OTG_STATE_B_PERIPHERAL:
718 if (int_usb & MUSB_INTR_SUSPEND) {
719 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
720 int_usb &= ~MUSB_INTR_SUSPEND;
721 goto b_host;
722 } else
723 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
724 break;
725 case OTG_STATE_B_WAIT_ACON:
726 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
727b_host:
728 musb->xceiv->state = OTG_STATE_B_HOST;
729 hcd->self.is_b_host = 1;
730 musb->ignore_disconnect = 0;
731 del_timer(&musb->otg_timer);
732 break;
733 default:
734 if ((devctl & MUSB_DEVCTL_VBUS)
735 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
736 musb->xceiv->state = OTG_STATE_A_HOST;
737 hcd->self.is_b_host = 0;
738 }
739 break;
740 }
741
742
743 MUSB_HST_MODE(musb);
744 if (hcd->status_urb)
745 usb_hcd_poll_rh_status(hcd);
746 else
747 usb_hcd_resume_root_hub(hcd);
748
749 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
750 usb_otg_state_string(musb->xceiv->state), devctl);
751 }
752
753 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
754 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
755 usb_otg_state_string(musb->xceiv->state),
756 MUSB_MODE(musb), devctl);
757 handled = IRQ_HANDLED;
758
759 switch (musb->xceiv->state) {
760 case OTG_STATE_A_HOST:
761 case OTG_STATE_A_SUSPEND:
762 usb_hcd_resume_root_hub(musb_to_hcd(musb));
763 musb_root_disconnect(musb);
764 if (musb->a_wait_bcon != 0)
765 musb_platform_try_idle(musb, jiffies
766 + msecs_to_jiffies(musb->a_wait_bcon));
767 break;
768 case OTG_STATE_B_HOST:
769
770
771
772
773
774 musb_root_disconnect(musb);
775 musb_to_hcd(musb)->self.is_b_host = 0;
776 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
777 MUSB_DEV_MODE(musb);
778 musb_g_disconnect(musb);
779 break;
780 case OTG_STATE_A_PERIPHERAL:
781 musb_hnp_stop(musb);
782 musb_root_disconnect(musb);
783
784 case OTG_STATE_B_WAIT_ACON:
785
786 case OTG_STATE_B_PERIPHERAL:
787 case OTG_STATE_B_IDLE:
788 musb_g_disconnect(musb);
789 break;
790 default:
791 WARNING("unhandled DISCONNECT transition (%s)\n",
792 usb_otg_state_string(musb->xceiv->state));
793 break;
794 }
795 }
796
797
798
799
800 if (int_usb & MUSB_INTR_RESET) {
801 handled = IRQ_HANDLED;
802 if ((devctl & MUSB_DEVCTL_HM) != 0) {
803
804
805
806
807
808
809
810 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
811 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
812 else {
813 ERR("Stopping host session -- babble\n");
814 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
815 }
816 } else {
817 dev_dbg(musb->controller, "BUS RESET as %s\n",
818 usb_otg_state_string(musb->xceiv->state));
819 switch (musb->xceiv->state) {
820 case OTG_STATE_A_SUSPEND:
821
822
823
824
825 musb->ignore_disconnect = 1;
826 musb_g_reset(musb);
827
828 case OTG_STATE_A_WAIT_BCON:
829
830 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
831 usb_otg_state_string(musb->xceiv->state),
832 TA_WAIT_BCON(musb));
833 mod_timer(&musb->otg_timer, jiffies
834 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
835 break;
836 case OTG_STATE_A_PERIPHERAL:
837 musb->ignore_disconnect = 0;
838 del_timer(&musb->otg_timer);
839 musb_g_reset(musb);
840 break;
841 case OTG_STATE_B_WAIT_ACON:
842 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
843 usb_otg_state_string(musb->xceiv->state));
844 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
845 musb_g_reset(musb);
846 break;
847 case OTG_STATE_B_IDLE:
848 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
849
850 case OTG_STATE_B_PERIPHERAL:
851 musb_g_reset(musb);
852 break;
853 default:
854 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
855 usb_otg_state_string(musb->xceiv->state));
856 }
857 }
858 }
859
860#if 0
861
862
863
864
865
866
867
868
869
870
871
872 if (int_usb & MUSB_INTR_SOF) {
873 void __iomem *mbase = musb->mregs;
874 struct musb_hw_ep *ep;
875 u8 epnum;
876 u16 frame;
877
878 dev_dbg(musb->controller, "START_OF_FRAME\n");
879 handled = IRQ_HANDLED;
880
881
882 frame = musb_readw(mbase, MUSB_FRAME);
883 ep = musb->endpoints;
884 for (epnum = 1; (epnum < musb->nr_endpoints)
885 && (musb->epmask >= (1 << epnum));
886 epnum++, ep++) {
887
888
889
890
891 if (ep->dwWaitFrame >= frame) {
892 ep->dwWaitFrame = 0;
893 pr_debug("SOF --> periodic TX%s on %d\n",
894 ep->tx_channel ? " DMA" : "",
895 epnum);
896 if (!ep->tx_channel)
897 musb_h_tx_start(musb, epnum);
898 else
899 cppi_hostdma_start(musb, epnum);
900 }
901 }
902 }
903#endif
904
905 schedule_work(&musb->irq_work);
906
907 return handled;
908}
909
910
911
912
913
914
915void musb_start(struct musb *musb)
916{
917 void __iomem *regs = musb->mregs;
918 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
919
920 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
921
922
923 musb->intrtxe = musb->epmask;
924 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
925 musb->intrrxe = musb->epmask & 0xfffe;
926 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
927 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
928
929 musb_writeb(regs, MUSB_TESTMODE, 0);
930
931
932 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
933 | MUSB_POWER_HSENAB
934
935
936 );
937
938 musb->is_active = 0;
939 devctl = musb_readb(regs, MUSB_DEVCTL);
940 devctl &= ~MUSB_DEVCTL_SESSION;
941
942
943
944
945
946
947 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
948 musb->is_active = 1;
949 else
950 devctl |= MUSB_DEVCTL_SESSION;
951
952 musb_platform_enable(musb);
953 musb_writeb(regs, MUSB_DEVCTL, devctl);
954}
955
956
957static void musb_generic_disable(struct musb *musb)
958{
959 void __iomem *mbase = musb->mregs;
960 u16 temp;
961
962
963 musb_writeb(mbase, MUSB_INTRUSBE, 0);
964 musb->intrtxe = 0;
965 musb_writew(mbase, MUSB_INTRTXE, 0);
966 musb->intrrxe = 0;
967 musb_writew(mbase, MUSB_INTRRXE, 0);
968
969
970 musb_writeb(mbase, MUSB_DEVCTL, 0);
971
972
973 temp = musb_readb(mbase, MUSB_INTRUSB);
974 temp = musb_readw(mbase, MUSB_INTRTX);
975 temp = musb_readw(mbase, MUSB_INTRRX);
976
977}
978
979
980
981
982
983
984
985
986void musb_stop(struct musb *musb)
987{
988
989 musb_platform_disable(musb);
990 musb_generic_disable(musb);
991 dev_dbg(musb->controller, "HDRC disabled\n");
992
993
994
995
996
997
998
999
1000 musb_platform_try_idle(musb, 0);
1001}
1002
1003static void musb_shutdown(struct platform_device *pdev)
1004{
1005 struct musb *musb = dev_to_musb(&pdev->dev);
1006 unsigned long flags;
1007
1008 pm_runtime_get_sync(musb->controller);
1009
1010 musb_gadget_cleanup(musb);
1011
1012 spin_lock_irqsave(&musb->lock, flags);
1013 musb_platform_disable(musb);
1014 musb_generic_disable(musb);
1015 spin_unlock_irqrestore(&musb->lock, flags);
1016
1017 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1018 musb_platform_exit(musb);
1019
1020 pm_runtime_put(musb->controller);
1021
1022}
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037#if defined(CONFIG_USB_MUSB_TUSB6010) \
1038 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \
1039 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1040 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \
1041 || defined(CONFIG_USB_MUSB_AM35X) \
1042 || defined(CONFIG_USB_MUSB_AM35X_MODULE) \
1043 || defined(CONFIG_USB_MUSB_DSPS) \
1044 || defined(CONFIG_USB_MUSB_DSPS_MODULE)
1045static ushort fifo_mode = 4;
1046#elif defined(CONFIG_USB_MUSB_UX500) \
1047 || defined(CONFIG_USB_MUSB_UX500_MODULE)
1048static ushort fifo_mode = 5;
1049#else
1050static ushort fifo_mode = 2;
1051#endif
1052
1053
1054module_param(fifo_mode, ushort, 0);
1055MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1056
1057
1058
1059
1060
1061
1062
1063static struct musb_fifo_cfg mode_0_cfg[] = {
1064{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1065{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1066{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1067{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1068{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1069};
1070
1071
1072static struct musb_fifo_cfg mode_1_cfg[] = {
1073{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1074{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1075{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1076{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1077{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1078};
1079
1080
1081static struct musb_fifo_cfg mode_2_cfg[] = {
1082{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1083{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1084{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1085{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1086{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1087{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1088};
1089
1090
1091static struct musb_fifo_cfg mode_3_cfg[] = {
1092{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1093{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1094{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1095{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1096{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1097{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1098};
1099
1100
1101static struct musb_fifo_cfg mode_4_cfg[] = {
1102{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1103{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1104{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1105{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1106{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1107{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1108{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1109{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1110{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1111{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1112{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1113{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1114{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1115{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1116{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1117{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1118{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1119{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1120{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1121{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1122{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1123{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1124{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1125{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1126{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1127{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1128{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1129};
1130
1131
1132static struct musb_fifo_cfg mode_5_cfg[] = {
1133{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1134{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1135{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1136{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1137{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1138{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1139{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1140{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1141{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1142{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1143{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1144{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1145{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1146{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1147{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1148{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1149{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1150{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1151{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1152{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1153{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1154{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1155{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1156{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1157{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1158{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1159{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1160};
1161
1162
1163
1164
1165
1166
1167
1168static int
1169fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1170 const struct musb_fifo_cfg *cfg, u16 offset)
1171{
1172 void __iomem *mbase = musb->mregs;
1173 int size = 0;
1174 u16 maxpacket = cfg->maxpacket;
1175 u16 c_off = offset >> 3;
1176 u8 c_size;
1177
1178
1179
1180 size = ffs(max(maxpacket, (u16) 8)) - 1;
1181 maxpacket = 1 << size;
1182
1183 c_size = size - 3;
1184 if (cfg->mode == BUF_DOUBLE) {
1185 if ((offset + (maxpacket << 1)) >
1186 (1 << (musb->config->ram_bits + 2)))
1187 return -EMSGSIZE;
1188 c_size |= MUSB_FIFOSZ_DPB;
1189 } else {
1190 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1191 return -EMSGSIZE;
1192 }
1193
1194
1195 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1196
1197
1198
1199
1200 if (hw_ep->epnum == 1)
1201 musb->bulk_ep = hw_ep;
1202
1203 switch (cfg->style) {
1204 case FIFO_TX:
1205 musb_write_txfifosz(mbase, c_size);
1206 musb_write_txfifoadd(mbase, c_off);
1207 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1208 hw_ep->max_packet_sz_tx = maxpacket;
1209 break;
1210 case FIFO_RX:
1211 musb_write_rxfifosz(mbase, c_size);
1212 musb_write_rxfifoadd(mbase, c_off);
1213 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1214 hw_ep->max_packet_sz_rx = maxpacket;
1215 break;
1216 case FIFO_RXTX:
1217 musb_write_txfifosz(mbase, c_size);
1218 musb_write_txfifoadd(mbase, c_off);
1219 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1220 hw_ep->max_packet_sz_rx = maxpacket;
1221
1222 musb_write_rxfifosz(mbase, c_size);
1223 musb_write_rxfifoadd(mbase, c_off);
1224 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1225 hw_ep->max_packet_sz_tx = maxpacket;
1226
1227 hw_ep->is_shared_fifo = true;
1228 break;
1229 }
1230
1231
1232
1233
1234 musb->epmask |= (1 << hw_ep->epnum);
1235
1236 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1237}
1238
1239static struct musb_fifo_cfg ep0_cfg = {
1240 .style = FIFO_RXTX, .maxpacket = 64,
1241};
1242
1243static int ep_config_from_table(struct musb *musb)
1244{
1245 const struct musb_fifo_cfg *cfg;
1246 unsigned i, n;
1247 int offset;
1248 struct musb_hw_ep *hw_ep = musb->endpoints;
1249
1250 if (musb->config->fifo_cfg) {
1251 cfg = musb->config->fifo_cfg;
1252 n = musb->config->fifo_cfg_size;
1253 goto done;
1254 }
1255
1256 switch (fifo_mode) {
1257 default:
1258 fifo_mode = 0;
1259
1260 case 0:
1261 cfg = mode_0_cfg;
1262 n = ARRAY_SIZE(mode_0_cfg);
1263 break;
1264 case 1:
1265 cfg = mode_1_cfg;
1266 n = ARRAY_SIZE(mode_1_cfg);
1267 break;
1268 case 2:
1269 cfg = mode_2_cfg;
1270 n = ARRAY_SIZE(mode_2_cfg);
1271 break;
1272 case 3:
1273 cfg = mode_3_cfg;
1274 n = ARRAY_SIZE(mode_3_cfg);
1275 break;
1276 case 4:
1277 cfg = mode_4_cfg;
1278 n = ARRAY_SIZE(mode_4_cfg);
1279 break;
1280 case 5:
1281 cfg = mode_5_cfg;
1282 n = ARRAY_SIZE(mode_5_cfg);
1283 break;
1284 }
1285
1286 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1287 musb_driver_name, fifo_mode);
1288
1289
1290done:
1291 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1292
1293
1294
1295
1296
1297
1298 for (i = 0; i < n; i++) {
1299 u8 epn = cfg->hw_ep_num;
1300
1301 if (epn >= musb->config->num_eps) {
1302 pr_debug("%s: invalid ep %d\n",
1303 musb_driver_name, epn);
1304 return -EINVAL;
1305 }
1306 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1307 if (offset < 0) {
1308 pr_debug("%s: mem overrun, ep %d\n",
1309 musb_driver_name, epn);
1310 return offset;
1311 }
1312 epn++;
1313 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1314 }
1315
1316 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1317 musb_driver_name,
1318 n + 1, musb->config->num_eps * 2 - 1,
1319 offset, (1 << (musb->config->ram_bits + 2)));
1320
1321 if (!musb->bulk_ep) {
1322 pr_debug("%s: missing bulk\n", musb_driver_name);
1323 return -EINVAL;
1324 }
1325
1326 return 0;
1327}
1328
1329
1330
1331
1332
1333
1334static int ep_config_from_hw(struct musb *musb)
1335{
1336 u8 epnum = 0;
1337 struct musb_hw_ep *hw_ep;
1338 void __iomem *mbase = musb->mregs;
1339 int ret = 0;
1340
1341 dev_dbg(musb->controller, "<== static silicon ep config\n");
1342
1343
1344
1345 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1346 musb_ep_select(mbase, epnum);
1347 hw_ep = musb->endpoints + epnum;
1348
1349 ret = musb_read_fifosize(musb, hw_ep, epnum);
1350 if (ret < 0)
1351 break;
1352
1353
1354
1355
1356 if (hw_ep->max_packet_sz_tx < 512
1357 || hw_ep->max_packet_sz_rx < 512)
1358 continue;
1359
1360
1361
1362
1363 if (musb->bulk_ep)
1364 continue;
1365 musb->bulk_ep = hw_ep;
1366 }
1367
1368 if (!musb->bulk_ep) {
1369 pr_debug("%s: missing bulk\n", musb_driver_name);
1370 return -EINVAL;
1371 }
1372
1373 return 0;
1374}
1375
1376enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1377
1378
1379
1380
1381static int musb_core_init(u16 musb_type, struct musb *musb)
1382{
1383 u8 reg;
1384 char *type;
1385 char aInfo[90], aRevision[32], aDate[12];
1386 void __iomem *mbase = musb->mregs;
1387 int status = 0;
1388 int i;
1389
1390
1391 reg = musb_read_configdata(mbase);
1392
1393 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1394 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1395 strcat(aInfo, ", dyn FIFOs");
1396 musb->dyn_fifo = true;
1397 }
1398 if (reg & MUSB_CONFIGDATA_MPRXE) {
1399 strcat(aInfo, ", bulk combine");
1400 musb->bulk_combine = true;
1401 }
1402 if (reg & MUSB_CONFIGDATA_MPTXE) {
1403 strcat(aInfo, ", bulk split");
1404 musb->bulk_split = true;
1405 }
1406 if (reg & MUSB_CONFIGDATA_HBRXE) {
1407 strcat(aInfo, ", HB-ISO Rx");
1408 musb->hb_iso_rx = true;
1409 }
1410 if (reg & MUSB_CONFIGDATA_HBTXE) {
1411 strcat(aInfo, ", HB-ISO Tx");
1412 musb->hb_iso_tx = true;
1413 }
1414 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1415 strcat(aInfo, ", SoftConn");
1416
1417 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1418 musb_driver_name, reg, aInfo);
1419
1420 aDate[0] = 0;
1421 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1422 musb->is_multipoint = 1;
1423 type = "M";
1424 } else {
1425 musb->is_multipoint = 0;
1426 type = "";
1427#ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1428 printk(KERN_ERR
1429 "%s: kernel must blacklist external hubs\n",
1430 musb_driver_name);
1431#endif
1432 }
1433
1434
1435 musb->hwvers = musb_read_hwvers(mbase);
1436 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1437 MUSB_HWVERS_MINOR(musb->hwvers),
1438 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1439 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1440 musb_driver_name, type, aRevision, aDate);
1441
1442
1443 musb_configure_ep0(musb);
1444
1445
1446 musb->nr_endpoints = 1;
1447 musb->epmask = 1;
1448
1449 if (musb->dyn_fifo)
1450 status = ep_config_from_table(musb);
1451 else
1452 status = ep_config_from_hw(musb);
1453
1454 if (status < 0)
1455 return status;
1456
1457
1458 for (i = 0; i < musb->nr_endpoints; i++) {
1459 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1460
1461 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1462#if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE)
1463 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1464 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1465 hw_ep->fifo_sync_va =
1466 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1467
1468 if (i == 0)
1469 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1470 else
1471 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1472#endif
1473
1474 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1475 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1476 hw_ep->rx_reinit = 1;
1477 hw_ep->tx_reinit = 1;
1478
1479 if (hw_ep->max_packet_sz_tx) {
1480 dev_dbg(musb->controller,
1481 "%s: hw_ep %d%s, %smax %d\n",
1482 musb_driver_name, i,
1483 hw_ep->is_shared_fifo ? "shared" : "tx",
1484 hw_ep->tx_double_buffered
1485 ? "doublebuffer, " : "",
1486 hw_ep->max_packet_sz_tx);
1487 }
1488 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1489 dev_dbg(musb->controller,
1490 "%s: hw_ep %d%s, %smax %d\n",
1491 musb_driver_name, i,
1492 "rx",
1493 hw_ep->rx_double_buffered
1494 ? "doublebuffer, " : "",
1495 hw_ep->max_packet_sz_rx);
1496 }
1497 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1498 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1499 }
1500
1501 return 0;
1502}
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513irqreturn_t musb_interrupt(struct musb *musb)
1514{
1515 irqreturn_t retval = IRQ_NONE;
1516 u8 devctl;
1517 int ep_num;
1518 u32 reg;
1519
1520 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1521
1522 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1523 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1524 musb->int_usb, musb->int_tx, musb->int_rx);
1525
1526
1527
1528
1529 if (musb->int_usb)
1530 retval |= musb_stage0_irq(musb, musb->int_usb,
1531 devctl);
1532
1533
1534
1535
1536 if (musb->int_tx & 1) {
1537 if (devctl & MUSB_DEVCTL_HM)
1538 retval |= musb_h_ep0_irq(musb);
1539 else
1540 retval |= musb_g_ep0_irq(musb);
1541 }
1542
1543
1544 reg = musb->int_rx >> 1;
1545 ep_num = 1;
1546 while (reg) {
1547 if (reg & 1) {
1548
1549
1550 retval = IRQ_HANDLED;
1551 if (devctl & MUSB_DEVCTL_HM)
1552 musb_host_rx(musb, ep_num);
1553 else
1554 musb_g_rx(musb, ep_num);
1555 }
1556
1557 reg >>= 1;
1558 ep_num++;
1559 }
1560
1561
1562 reg = musb->int_tx >> 1;
1563 ep_num = 1;
1564 while (reg) {
1565 if (reg & 1) {
1566
1567
1568 retval = IRQ_HANDLED;
1569 if (devctl & MUSB_DEVCTL_HM)
1570 musb_host_tx(musb, ep_num);
1571 else
1572 musb_g_tx(musb, ep_num);
1573 }
1574 reg >>= 1;
1575 ep_num++;
1576 }
1577
1578 return retval;
1579}
1580EXPORT_SYMBOL_GPL(musb_interrupt);
1581
1582#ifndef CONFIG_MUSB_PIO_ONLY
1583static bool use_dma = 1;
1584
1585
1586module_param(use_dma, bool, 0);
1587MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1588
1589void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1590{
1591 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1592
1593
1594
1595 if (!epnum) {
1596#ifndef CONFIG_USB_TUSB_OMAP_DMA
1597 if (!is_cppi_enabled()) {
1598
1599 if (devctl & MUSB_DEVCTL_HM)
1600 musb_h_ep0_irq(musb);
1601 else
1602 musb_g_ep0_irq(musb);
1603 }
1604#endif
1605 } else {
1606
1607 if (transmit) {
1608 if (devctl & MUSB_DEVCTL_HM)
1609 musb_host_tx(musb, epnum);
1610 else
1611 musb_g_tx(musb, epnum);
1612 } else {
1613
1614 if (devctl & MUSB_DEVCTL_HM)
1615 musb_host_rx(musb, epnum);
1616 else
1617 musb_g_rx(musb, epnum);
1618 }
1619 }
1620}
1621EXPORT_SYMBOL_GPL(musb_dma_completion);
1622
1623#else
1624#define use_dma 0
1625#endif
1626
1627
1628
1629static ssize_t
1630musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1631{
1632 struct musb *musb = dev_to_musb(dev);
1633 unsigned long flags;
1634 int ret = -EINVAL;
1635
1636 spin_lock_irqsave(&musb->lock, flags);
1637 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->state));
1638 spin_unlock_irqrestore(&musb->lock, flags);
1639
1640 return ret;
1641}
1642
1643static ssize_t
1644musb_mode_store(struct device *dev, struct device_attribute *attr,
1645 const char *buf, size_t n)
1646{
1647 struct musb *musb = dev_to_musb(dev);
1648 unsigned long flags;
1649 int status;
1650
1651 spin_lock_irqsave(&musb->lock, flags);
1652 if (sysfs_streq(buf, "host"))
1653 status = musb_platform_set_mode(musb, MUSB_HOST);
1654 else if (sysfs_streq(buf, "peripheral"))
1655 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1656 else if (sysfs_streq(buf, "otg"))
1657 status = musb_platform_set_mode(musb, MUSB_OTG);
1658 else
1659 status = -EINVAL;
1660 spin_unlock_irqrestore(&musb->lock, flags);
1661
1662 return (status == 0) ? n : status;
1663}
1664static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1665
1666static ssize_t
1667musb_vbus_store(struct device *dev, struct device_attribute *attr,
1668 const char *buf, size_t n)
1669{
1670 struct musb *musb = dev_to_musb(dev);
1671 unsigned long flags;
1672 unsigned long val;
1673
1674 if (sscanf(buf, "%lu", &val) < 1) {
1675 dev_err(dev, "Invalid VBUS timeout ms value\n");
1676 return -EINVAL;
1677 }
1678
1679 spin_lock_irqsave(&musb->lock, flags);
1680
1681 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1682 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1683 musb->is_active = 0;
1684 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1685 spin_unlock_irqrestore(&musb->lock, flags);
1686
1687 return n;
1688}
1689
1690static ssize_t
1691musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1692{
1693 struct musb *musb = dev_to_musb(dev);
1694 unsigned long flags;
1695 unsigned long val;
1696 int vbus;
1697
1698 spin_lock_irqsave(&musb->lock, flags);
1699 val = musb->a_wait_bcon;
1700
1701
1702
1703 vbus = musb_platform_get_vbus_status(musb);
1704 spin_unlock_irqrestore(&musb->lock, flags);
1705
1706 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1707 vbus ? "on" : "off", val);
1708}
1709static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1710
1711
1712
1713
1714static ssize_t
1715musb_srp_store(struct device *dev, struct device_attribute *attr,
1716 const char *buf, size_t n)
1717{
1718 struct musb *musb = dev_to_musb(dev);
1719 unsigned short srp;
1720
1721 if (sscanf(buf, "%hu", &srp) != 1
1722 || (srp != 1)) {
1723 dev_err(dev, "SRP: Value must be 1\n");
1724 return -EINVAL;
1725 }
1726
1727 if (srp == 1)
1728 musb_g_wakeup(musb);
1729
1730 return n;
1731}
1732static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1733
1734static struct attribute *musb_attributes[] = {
1735 &dev_attr_mode.attr,
1736 &dev_attr_vbus.attr,
1737 &dev_attr_srp.attr,
1738 NULL
1739};
1740
1741static const struct attribute_group musb_attr_group = {
1742 .attrs = musb_attributes,
1743};
1744
1745
1746static void musb_irq_work(struct work_struct *data)
1747{
1748 struct musb *musb = container_of(data, struct musb, irq_work);
1749
1750 if (musb->xceiv->state != musb->xceiv_old_state) {
1751 musb->xceiv_old_state = musb->xceiv->state;
1752 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1753 }
1754}
1755
1756
1757
1758
1759
1760static struct musb *allocate_instance(struct device *dev,
1761 struct musb_hdrc_config *config, void __iomem *mbase)
1762{
1763 struct musb *musb;
1764 struct musb_hw_ep *ep;
1765 int epnum;
1766 struct usb_hcd *hcd;
1767
1768 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1769 if (!hcd)
1770 return NULL;
1771
1772
1773 musb = hcd_to_musb(hcd);
1774 INIT_LIST_HEAD(&musb->control);
1775 INIT_LIST_HEAD(&musb->in_bulk);
1776 INIT_LIST_HEAD(&musb->out_bulk);
1777
1778 hcd->uses_new_polling = 1;
1779 hcd->has_tt = 1;
1780
1781 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1782 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1783 dev_set_drvdata(dev, musb);
1784 musb->mregs = mbase;
1785 musb->ctrl_base = mbase;
1786 musb->nIrq = -ENODEV;
1787 musb->config = config;
1788 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1789 for (epnum = 0, ep = musb->endpoints;
1790 epnum < musb->config->num_eps;
1791 epnum++, ep++) {
1792 ep->musb = musb;
1793 ep->epnum = epnum;
1794 }
1795
1796 musb->controller = dev;
1797
1798 return musb;
1799}
1800
1801static void musb_free(struct musb *musb)
1802{
1803
1804
1805
1806
1807
1808#ifdef CONFIG_SYSFS
1809 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1810#endif
1811
1812 if (musb->nIrq >= 0) {
1813 if (musb->irq_wake)
1814 disable_irq_wake(musb->nIrq);
1815 free_irq(musb->nIrq, musb);
1816 }
1817 if (is_dma_capable() && musb->dma_controller) {
1818 struct dma_controller *c = musb->dma_controller;
1819
1820 (void) c->stop(c);
1821 dma_controller_destroy(c);
1822 }
1823
1824 usb_put_hcd(musb_to_hcd(musb));
1825}
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835static int
1836musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1837{
1838 int status;
1839 struct musb *musb;
1840 struct musb_hdrc_platform_data *plat = dev->platform_data;
1841 struct usb_hcd *hcd;
1842
1843
1844
1845
1846 if (!plat) {
1847 dev_dbg(dev, "no platform_data?\n");
1848 status = -ENODEV;
1849 goto fail0;
1850 }
1851
1852
1853 musb = allocate_instance(dev, plat->config, ctrl);
1854 if (!musb) {
1855 status = -ENOMEM;
1856 goto fail0;
1857 }
1858
1859 pm_runtime_use_autosuspend(musb->controller);
1860 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1861 pm_runtime_enable(musb->controller);
1862
1863 spin_lock_init(&musb->lock);
1864 musb->board_set_power = plat->set_power;
1865 musb->min_power = plat->min_power;
1866 musb->ops = plat->platform_ops;
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880 status = musb_platform_init(musb);
1881 if (status < 0)
1882 goto fail1;
1883
1884 if (!musb->isr) {
1885 status = -ENODEV;
1886 goto fail2;
1887 }
1888
1889 if (!musb->xceiv->io_ops) {
1890 musb->xceiv->io_dev = musb->controller;
1891 musb->xceiv->io_priv = musb->mregs;
1892 musb->xceiv->io_ops = &musb_ulpi_access;
1893 }
1894
1895 pm_runtime_get_sync(musb->controller);
1896
1897#ifndef CONFIG_MUSB_PIO_ONLY
1898 if (use_dma && dev->dma_mask) {
1899 struct dma_controller *c;
1900
1901 c = dma_controller_create(musb, musb->mregs);
1902 musb->dma_controller = c;
1903 if (c)
1904 (void) c->start(c);
1905 }
1906#endif
1907
1908 if (!is_dma_capable() || !musb->dma_controller)
1909 dev->dma_mask = NULL;
1910
1911
1912 musb_platform_disable(musb);
1913 musb_generic_disable(musb);
1914
1915
1916 status = musb_core_init(plat->config->multipoint
1917 ? MUSB_CONTROLLER_MHDRC
1918 : MUSB_CONTROLLER_HDRC, musb);
1919 if (status < 0)
1920 goto fail3;
1921
1922 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
1923
1924
1925 INIT_WORK(&musb->irq_work, musb_irq_work);
1926
1927
1928 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
1929 dev_err(dev, "request_irq %d failed!\n", nIrq);
1930 status = -ENODEV;
1931 goto fail3;
1932 }
1933 musb->nIrq = nIrq;
1934
1935 if (enable_irq_wake(nIrq) == 0) {
1936 musb->irq_wake = 1;
1937 device_init_wakeup(dev, 1);
1938 } else {
1939 musb->irq_wake = 0;
1940 }
1941
1942
1943 hcd = musb_to_hcd(musb);
1944 otg_set_host(musb->xceiv->otg, &hcd->self);
1945 hcd->self.otg_port = 1;
1946 musb->xceiv->otg->host = &hcd->self;
1947 hcd->power_budget = 2 * (plat->power ? : 250);
1948
1949
1950 if (plat->extvbus) {
1951 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
1952 busctl |= MUSB_ULPI_USE_EXTVBUS;
1953 musb_write_ulpi_buscontrol(musb->mregs, busctl);
1954 }
1955
1956 if (musb->xceiv->otg->default_a) {
1957 MUSB_HST_MODE(musb);
1958 musb->xceiv->state = OTG_STATE_A_IDLE;
1959 } else {
1960 MUSB_DEV_MODE(musb);
1961 musb->xceiv->state = OTG_STATE_B_IDLE;
1962 }
1963
1964 status = musb_gadget_setup(musb);
1965
1966 if (status < 0)
1967 goto fail3;
1968
1969 status = musb_init_debugfs(musb);
1970 if (status < 0)
1971 goto fail4;
1972
1973 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
1974 if (status)
1975 goto fail5;
1976
1977 pm_runtime_put(musb->controller);
1978
1979 return 0;
1980
1981fail5:
1982 musb_exit_debugfs(musb);
1983
1984fail4:
1985 musb_gadget_cleanup(musb);
1986
1987fail3:
1988 pm_runtime_put_sync(musb->controller);
1989
1990fail2:
1991 if (musb->irq_wake)
1992 device_init_wakeup(dev, 0);
1993 musb_platform_exit(musb);
1994
1995fail1:
1996 pm_runtime_disable(musb->controller);
1997 dev_err(musb->controller,
1998 "musb_init_controller failed with status %d\n", status);
1999
2000 musb_free(musb);
2001
2002fail0:
2003
2004 return status;
2005
2006}
2007
2008
2009
2010
2011
2012
2013static int musb_probe(struct platform_device *pdev)
2014{
2015 struct device *dev = &pdev->dev;
2016 int irq = platform_get_irq_byname(pdev, "mc");
2017 struct resource *iomem;
2018 void __iomem *base;
2019
2020 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2021 if (!iomem || irq <= 0)
2022 return -ENODEV;
2023
2024 base = devm_ioremap_resource(dev, iomem);
2025 if (IS_ERR(base))
2026 return PTR_ERR(base);
2027
2028 return musb_init_controller(dev, irq, base);
2029}
2030
2031static int musb_remove(struct platform_device *pdev)
2032{
2033 struct device *dev = &pdev->dev;
2034 struct musb *musb = dev_to_musb(dev);
2035
2036
2037
2038
2039
2040
2041 musb_exit_debugfs(musb);
2042 musb_shutdown(pdev);
2043
2044 musb_free(musb);
2045 device_init_wakeup(dev, 0);
2046#ifndef CONFIG_MUSB_PIO_ONLY
2047 dma_set_mask(dev, *dev->parent->dma_mask);
2048#endif
2049 return 0;
2050}
2051
2052#ifdef CONFIG_PM
2053
2054static void musb_save_context(struct musb *musb)
2055{
2056 int i;
2057 void __iomem *musb_base = musb->mregs;
2058 void __iomem *epio;
2059
2060 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2061 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2062 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2063 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2064 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2065 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2066 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2067
2068 for (i = 0; i < musb->config->num_eps; ++i) {
2069 struct musb_hw_ep *hw_ep;
2070
2071 hw_ep = &musb->endpoints[i];
2072 if (!hw_ep)
2073 continue;
2074
2075 epio = hw_ep->regs;
2076 if (!epio)
2077 continue;
2078
2079 musb_writeb(musb_base, MUSB_INDEX, i);
2080 musb->context.index_regs[i].txmaxp =
2081 musb_readw(epio, MUSB_TXMAXP);
2082 musb->context.index_regs[i].txcsr =
2083 musb_readw(epio, MUSB_TXCSR);
2084 musb->context.index_regs[i].rxmaxp =
2085 musb_readw(epio, MUSB_RXMAXP);
2086 musb->context.index_regs[i].rxcsr =
2087 musb_readw(epio, MUSB_RXCSR);
2088
2089 if (musb->dyn_fifo) {
2090 musb->context.index_regs[i].txfifoadd =
2091 musb_read_txfifoadd(musb_base);
2092 musb->context.index_regs[i].rxfifoadd =
2093 musb_read_rxfifoadd(musb_base);
2094 musb->context.index_regs[i].txfifosz =
2095 musb_read_txfifosz(musb_base);
2096 musb->context.index_regs[i].rxfifosz =
2097 musb_read_rxfifosz(musb_base);
2098 }
2099
2100 musb->context.index_regs[i].txtype =
2101 musb_readb(epio, MUSB_TXTYPE);
2102 musb->context.index_regs[i].txinterval =
2103 musb_readb(epio, MUSB_TXINTERVAL);
2104 musb->context.index_regs[i].rxtype =
2105 musb_readb(epio, MUSB_RXTYPE);
2106 musb->context.index_regs[i].rxinterval =
2107 musb_readb(epio, MUSB_RXINTERVAL);
2108
2109 musb->context.index_regs[i].txfunaddr =
2110 musb_read_txfunaddr(musb_base, i);
2111 musb->context.index_regs[i].txhubaddr =
2112 musb_read_txhubaddr(musb_base, i);
2113 musb->context.index_regs[i].txhubport =
2114 musb_read_txhubport(musb_base, i);
2115
2116 musb->context.index_regs[i].rxfunaddr =
2117 musb_read_rxfunaddr(musb_base, i);
2118 musb->context.index_regs[i].rxhubaddr =
2119 musb_read_rxhubaddr(musb_base, i);
2120 musb->context.index_regs[i].rxhubport =
2121 musb_read_rxhubport(musb_base, i);
2122 }
2123}
2124
2125static void musb_restore_context(struct musb *musb)
2126{
2127 int i;
2128 void __iomem *musb_base = musb->mregs;
2129 void __iomem *ep_target_regs;
2130 void __iomem *epio;
2131
2132 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2133 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2134 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2135 musb_writeb(musb_base, MUSB_POWER, musb->context.power);
2136 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2137 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2138 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2139 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2140
2141 for (i = 0; i < musb->config->num_eps; ++i) {
2142 struct musb_hw_ep *hw_ep;
2143
2144 hw_ep = &musb->endpoints[i];
2145 if (!hw_ep)
2146 continue;
2147
2148 epio = hw_ep->regs;
2149 if (!epio)
2150 continue;
2151
2152 musb_writeb(musb_base, MUSB_INDEX, i);
2153 musb_writew(epio, MUSB_TXMAXP,
2154 musb->context.index_regs[i].txmaxp);
2155 musb_writew(epio, MUSB_TXCSR,
2156 musb->context.index_regs[i].txcsr);
2157 musb_writew(epio, MUSB_RXMAXP,
2158 musb->context.index_regs[i].rxmaxp);
2159 musb_writew(epio, MUSB_RXCSR,
2160 musb->context.index_regs[i].rxcsr);
2161
2162 if (musb->dyn_fifo) {
2163 musb_write_txfifosz(musb_base,
2164 musb->context.index_regs[i].txfifosz);
2165 musb_write_rxfifosz(musb_base,
2166 musb->context.index_regs[i].rxfifosz);
2167 musb_write_txfifoadd(musb_base,
2168 musb->context.index_regs[i].txfifoadd);
2169 musb_write_rxfifoadd(musb_base,
2170 musb->context.index_regs[i].rxfifoadd);
2171 }
2172
2173 musb_writeb(epio, MUSB_TXTYPE,
2174 musb->context.index_regs[i].txtype);
2175 musb_writeb(epio, MUSB_TXINTERVAL,
2176 musb->context.index_regs[i].txinterval);
2177 musb_writeb(epio, MUSB_RXTYPE,
2178 musb->context.index_regs[i].rxtype);
2179 musb_writeb(epio, MUSB_RXINTERVAL,
2180
2181 musb->context.index_regs[i].rxinterval);
2182 musb_write_txfunaddr(musb_base, i,
2183 musb->context.index_regs[i].txfunaddr);
2184 musb_write_txhubaddr(musb_base, i,
2185 musb->context.index_regs[i].txhubaddr);
2186 musb_write_txhubport(musb_base, i,
2187 musb->context.index_regs[i].txhubport);
2188
2189 ep_target_regs =
2190 musb_read_target_reg_base(i, musb_base);
2191
2192 musb_write_rxfunaddr(ep_target_regs,
2193 musb->context.index_regs[i].rxfunaddr);
2194 musb_write_rxhubaddr(ep_target_regs,
2195 musb->context.index_regs[i].rxhubaddr);
2196 musb_write_rxhubport(ep_target_regs,
2197 musb->context.index_regs[i].rxhubport);
2198 }
2199 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2200}
2201
2202static int musb_suspend(struct device *dev)
2203{
2204 struct musb *musb = dev_to_musb(dev);
2205 unsigned long flags;
2206
2207 spin_lock_irqsave(&musb->lock, flags);
2208
2209 if (is_peripheral_active(musb)) {
2210
2211
2212
2213 } else if (is_host_active(musb)) {
2214
2215
2216
2217 }
2218
2219 spin_unlock_irqrestore(&musb->lock, flags);
2220 return 0;
2221}
2222
2223static int musb_resume_noirq(struct device *dev)
2224{
2225
2226
2227
2228
2229 return 0;
2230}
2231
2232static int musb_runtime_suspend(struct device *dev)
2233{
2234 struct musb *musb = dev_to_musb(dev);
2235
2236 musb_save_context(musb);
2237
2238 return 0;
2239}
2240
2241static int musb_runtime_resume(struct device *dev)
2242{
2243 struct musb *musb = dev_to_musb(dev);
2244 static int first = 1;
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255 if (!first)
2256 musb_restore_context(musb);
2257 first = 0;
2258
2259 return 0;
2260}
2261
2262static const struct dev_pm_ops musb_dev_pm_ops = {
2263 .suspend = musb_suspend,
2264 .resume_noirq = musb_resume_noirq,
2265 .runtime_suspend = musb_runtime_suspend,
2266 .runtime_resume = musb_runtime_resume,
2267};
2268
2269#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2270#else
2271#define MUSB_DEV_PM_OPS NULL
2272#endif
2273
2274static struct platform_driver musb_driver = {
2275 .driver = {
2276 .name = (char *)musb_driver_name,
2277 .bus = &platform_bus_type,
2278 .owner = THIS_MODULE,
2279 .pm = MUSB_DEV_PM_OPS,
2280 },
2281 .probe = musb_probe,
2282 .remove = musb_remove,
2283 .shutdown = musb_shutdown,
2284};
2285
2286
2287
2288static int __init musb_init(void)
2289{
2290 if (usb_disabled())
2291 return 0;
2292
2293 return platform_driver_register(&musb_driver);
2294}
2295module_init(musb_init);
2296
2297static void __exit musb_cleanup(void)
2298{
2299 platform_driver_unregister(&musb_driver);
2300}
2301module_exit(musb_cleanup);
2302