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34#ifndef CONFIG_BLACKFIN
35
36#define MUSB_HSDMA_BASE 0x200
37#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
38#define MUSB_HSDMA_CONTROL 0x4
39#define MUSB_HSDMA_ADDRESS 0x8
40#define MUSB_HSDMA_COUNT 0xc
41
42#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
43 (MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
44
45#define musb_read_hsdma_addr(mbase, bchannel) \
46 musb_readl(mbase, \
47 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS))
48
49#define musb_write_hsdma_addr(mbase, bchannel, addr) \
50 musb_writel(mbase, \
51 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \
52 addr)
53
54#define musb_read_hsdma_count(mbase, bchannel) \
55 musb_readl(mbase, \
56 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT))
57
58#define musb_write_hsdma_count(mbase, bchannel, len) \
59 musb_writel(mbase, \
60 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
61 len)
62#else
63
64#define MUSB_HSDMA_BASE 0x400
65#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
66#define MUSB_HSDMA_CONTROL 0x04
67#define MUSB_HSDMA_ADDR_LOW 0x08
68#define MUSB_HSDMA_ADDR_HIGH 0x0C
69#define MUSB_HSDMA_COUNT_LOW 0x10
70#define MUSB_HSDMA_COUNT_HIGH 0x14
71
72#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
73 (MUSB_HSDMA_BASE + (_bchannel * 0x20) + _offset)
74
75static inline u32 musb_read_hsdma_addr(void __iomem *mbase, u8 bchannel)
76{
77 u32 addr = musb_readw(mbase,
78 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH));
79
80 addr = addr << 16;
81
82 addr |= musb_readw(mbase,
83 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW));
84
85 return addr;
86}
87
88static inline void musb_write_hsdma_addr(void __iomem *mbase,
89 u8 bchannel, dma_addr_t dma_addr)
90{
91 musb_writew(mbase,
92 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW),
93 dma_addr);
94 musb_writew(mbase,
95 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH),
96 (dma_addr >> 16));
97}
98
99static inline u32 musb_read_hsdma_count(void __iomem *mbase, u8 bchannel)
100{
101 u32 count = musb_readw(mbase,
102 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH));
103
104 count = count << 16;
105
106 count |= musb_readw(mbase,
107 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_LOW));
108
109 return count;
110}
111
112static inline void musb_write_hsdma_count(void __iomem *mbase,
113 u8 bchannel, u32 len)
114{
115 musb_writew(mbase,
116 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_LOW),len);
117 musb_writew(mbase,
118 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH),
119 (len >> 16));
120}
121
122#endif
123
124
125#define MUSB_HSDMA_ENABLE_SHIFT 0
126#define MUSB_HSDMA_TRANSMIT_SHIFT 1
127#define MUSB_HSDMA_MODE1_SHIFT 2
128#define MUSB_HSDMA_IRQENABLE_SHIFT 3
129#define MUSB_HSDMA_ENDPOINT_SHIFT 4
130#define MUSB_HSDMA_BUSERROR_SHIFT 8
131#define MUSB_HSDMA_BURSTMODE_SHIFT 9
132#define MUSB_HSDMA_BURSTMODE (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
133#define MUSB_HSDMA_BURSTMODE_UNSPEC 0
134#define MUSB_HSDMA_BURSTMODE_INCR4 1
135#define MUSB_HSDMA_BURSTMODE_INCR8 2
136#define MUSB_HSDMA_BURSTMODE_INCR16 3
137
138#define MUSB_HSDMA_CHANNELS 8
139
140struct musb_dma_controller;
141
142struct musb_dma_channel {
143 struct dma_channel channel;
144 struct musb_dma_controller *controller;
145 u32 start_addr;
146 u32 len;
147 u16 max_packet_sz;
148 u8 idx;
149 u8 epnum;
150 u8 transmit;
151};
152
153struct musb_dma_controller {
154 struct dma_controller controller;
155 struct musb_dma_channel channel[MUSB_HSDMA_CHANNELS];
156 void *private_data;
157 void __iomem *base;
158 u8 channel_count;
159 u8 used_channels;
160 u8 irq;
161};
162