1/* linux/driver/video/exynos/exynos_mipi_dsi_regs.h 2 * 3 * Register definition file for Samsung MIPI-DSIM driver 4 * 5 * Copyright (c) 2012 Samsung Electronics Co., Ltd 6 * 7 * InKi Dae <inki.dae@samsung.com> 8 * Donghwa Lee <dh09.lee@samsung.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13*/ 14 15#ifndef _EXYNOS_MIPI_DSI_REGS_H 16#define _EXYNOS_MIPI_DSI_REGS_H 17 18#define EXYNOS_DSIM_STATUS 0x0 /* Status register */ 19#define EXYNOS_DSIM_SWRST 0x4 /* Software reset register */ 20#define EXYNOS_DSIM_CLKCTRL 0x8 /* Clock control register */ 21#define EXYNOS_DSIM_TIMEOUT 0xc /* Time out register */ 22#define EXYNOS_DSIM_CONFIG 0x10 /* Configuration register */ 23#define EXYNOS_DSIM_ESCMODE 0x14 /* Escape mode register */ 24 25/* Main display image resolution register */ 26#define EXYNOS_DSIM_MDRESOL 0x18 27#define EXYNOS_DSIM_MVPORCH 0x1c /* Main display Vporch register */ 28#define EXYNOS_DSIM_MHPORCH 0x20 /* Main display Hporch register */ 29#define EXYNOS_DSIM_MSYNC 0x24 /* Main display sync area register */ 30 31/* Sub display image resolution register */ 32#define EXYNOS_DSIM_SDRESOL 0x28 33#define EXYNOS_DSIM_INTSRC 0x2c /* Interrupt source register */ 34#define EXYNOS_DSIM_INTMSK 0x30 /* Interrupt mask register */ 35#define EXYNOS_DSIM_PKTHDR 0x34 /* Packet Header FIFO register */ 36#define EXYNOS_DSIM_PAYLOAD 0x38 /* Payload FIFO register */ 37#define EXYNOS_DSIM_RXFIFO 0x3c /* Read FIFO register */ 38#define EXYNOS_DSIM_FIFOTHLD 0x40 /* FIFO threshold level register */ 39#define EXYNOS_DSIM_FIFOCTRL 0x44 /* FIFO status and control register */ 40 41/* FIFO memory AC characteristic register */ 42#define EXYNOS_DSIM_PLLCTRL 0x4c /* PLL control register */ 43#define EXYNOS_DSIM_PLLTMR 0x50 /* PLL timer register */ 44#define EXYNOS_DSIM_PHYACCHR 0x54 /* D-PHY AC characteristic register */ 45#define EXYNOS_DSIM_PHYACCHR1 0x58 /* D-PHY AC characteristic register1 */ 46 47/* DSIM_STATUS */ 48#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) 49#define DSIM_STOP_STATE_CLK (1 << 8) 50#define DSIM_TX_READY_HS_CLK (1 << 10) 51 52/* DSIM_SWRST */ 53#define DSIM_FUNCRST (1 << 16) 54#define DSIM_SWRST (1 << 0) 55 56/* EXYNOS_DSIM_TIMEOUT */ 57#define DSIM_LPDR_TOUT_SHIFT(x) ((x) << 0) 58#define DSIM_BTA_TOUT_SHIFT(x) ((x) << 16) 59 60/* EXYNOS_DSIM_CLKCTRL */ 61#define DSIM_LANE_ESC_CLKEN(x) (((x) & 0x1f) << 19) 62#define DSIM_BYTE_CLKEN_SHIFT(x) ((x) << 24) 63#define DSIM_BYTE_CLK_SRC_SHIFT(x) ((x) << 25) 64#define DSIM_PLL_BYPASS_SHIFT(x) ((x) << 27) 65#define DSIM_ESC_CLKEN_SHIFT(x) ((x) << 28) 66#define DSIM_TX_REQUEST_HSCLK_SHIFT(x) ((x) << 31) 67 68/* EXYNOS_DSIM_CONFIG */ 69#define DSIM_LANE_ENx(x) (((x) & 0x1f) << 0) 70#define DSIM_NUM_OF_DATALANE_SHIFT(x) ((x) << 5) 71#define DSIM_HSA_MODE_SHIFT(x) ((x) << 20) 72#define DSIM_HBP_MODE_SHIFT(x) ((x) << 21) 73#define DSIM_HFP_MODE_SHIFT(x) ((x) << 22) 74#define DSIM_HSE_MODE_SHIFT(x) ((x) << 23) 75#define DSIM_AUTO_MODE_SHIFT(x) ((x) << 24) 76#define DSIM_EOT_DISABLE(x) ((x) << 28) 77#define DSIM_AUTO_FLUSH(x) ((x) << 29) 78 79#define DSIM_NUM_OF_DATA_LANE(x) ((x) << DSIM_NUM_OF_DATALANE_SHIFT) 80 81/* EXYNOS_DSIM_ESCMODE */ 82#define DSIM_TX_LPDT_LP (1 << 6) 83#define DSIM_CMD_LPDT_LP (1 << 7) 84#define DSIM_FORCE_STOP_STATE_SHIFT(x) ((x) << 20) 85#define DSIM_STOP_STATE_CNT_SHIFT(x) ((x) << 21) 86 87/* EXYNOS_DSIM_MDRESOL */ 88#define DSIM_MAIN_STAND_BY (1 << 31) 89#define DSIM_MAIN_VRESOL(x) (((x) & 0x7ff) << 16) 90#define DSIM_MAIN_HRESOL(x) (((x) & 0X7ff) << 0) 91 92/* EXYNOS_DSIM_MVPORCH */ 93#define DSIM_CMD_ALLOW_SHIFT(x) ((x) << 28) 94#define DSIM_STABLE_VFP_SHIFT(x) ((x) << 16) 95#define DSIM_MAIN_VBP_SHIFT(x) ((x) << 0) 96#define DSIM_CMD_ALLOW_MASK (0xf << 28) 97#define DSIM_STABLE_VFP_MASK (0x7ff << 16) 98#define DSIM_MAIN_VBP_MASK (0x7ff << 0) 99 100/* EXYNOS_DSIM_MHPORCH */ 101#define DSIM_MAIN_HFP_SHIFT(x) ((x) << 16) 102#define DSIM_MAIN_HBP_SHIFT(x) ((x) << 0) 103#define DSIM_MAIN_HFP_MASK ((0xffff) << 16) 104#define DSIM_MAIN_HBP_MASK ((0xffff) << 0) 105 106/* EXYNOS_DSIM_MSYNC */ 107#define DSIM_MAIN_VSA_SHIFT(x) ((x) << 22) 108#define DSIM_MAIN_HSA_SHIFT(x) ((x) << 0) 109#define DSIM_MAIN_VSA_MASK ((0x3ff) << 22) 110#define DSIM_MAIN_HSA_MASK ((0xffff) << 0) 111 112/* EXYNOS_DSIM_SDRESOL */ 113#define DSIM_SUB_STANDY_SHIFT(x) ((x) << 31) 114#define DSIM_SUB_VRESOL_SHIFT(x) ((x) << 16) 115#define DSIM_SUB_HRESOL_SHIFT(x) ((x) << 0) 116#define DSIM_SUB_STANDY_MASK ((0x1) << 31) 117#define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16) 118#define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0) 119 120/* EXYNOS_DSIM_INTSRC */ 121#define INTSRC_PLL_STABLE (1 << 31) 122#define INTSRC_SW_RST_RELEASE (1 << 30) 123#define INTSRC_SFR_FIFO_EMPTY (1 << 29) 124#define INTSRC_FRAME_DONE (1 << 24) 125#define INTSRC_RX_DATA_DONE (1 << 18) 126 127/* EXYNOS_DSIM_INTMSK */ 128#define INTMSK_FIFO_EMPTY (1 << 29) 129#define INTMSK_BTA (1 << 25) 130#define INTMSK_FRAME_DONE (1 << 24) 131#define INTMSK_RX_TIMEOUT (1 << 21) 132#define INTMSK_BTA_TIMEOUT (1 << 20) 133#define INTMSK_RX_DONE (1 << 18) 134#define INTMSK_RX_TE (1 << 17) 135#define INTMSK_RX_ACK (1 << 16) 136#define INTMSK_RX_ECC_ERR (1 << 15) 137#define INTMSK_RX_CRC_ERR (1 << 14) 138 139/* EXYNOS_DSIM_FIFOCTRL */ 140#define SFR_HEADER_EMPTY (1 << 22) 141 142/* EXYNOS_DSIM_PHYACCHR */ 143#define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) 144 145/* EXYNOS_DSIM_PLLCTRL */ 146#define DSIM_PLL_EN_SHIFT(x) ((x) << 23) 147#define DSIM_FREQ_BAND_SHIFT(x) ((x) << 24) 148 149#endif /* _EXYNOS_MIPI_DSI_REGS_H */ 150