1/* 2 * Generic EDAC defs 3 * 4 * Author: Dave Jiang <djiang@mvista.com> 5 * 6 * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under 7 * the terms of the GNU General Public License version 2. This program 8 * is licensed "as is" without any warranty of any kind, whether express 9 * or implied. 10 * 11 */ 12#ifndef _LINUX_EDAC_H_ 13#define _LINUX_EDAC_H_ 14 15#include <linux/atomic.h> 16#include <linux/device.h> 17#include <linux/completion.h> 18#include <linux/workqueue.h> 19#include <linux/debugfs.h> 20 21struct device; 22 23#define EDAC_OPSTATE_INVAL -1 24#define EDAC_OPSTATE_POLL 0 25#define EDAC_OPSTATE_NMI 1 26#define EDAC_OPSTATE_INT 2 27 28extern int edac_op_state; 29extern int edac_err_assert; 30extern atomic_t edac_handlers; 31extern struct bus_type edac_subsys; 32 33extern int edac_handler_set(void); 34extern void edac_atomic_assert_error(void); 35extern struct bus_type *edac_get_sysfs_subsys(void); 36extern void edac_put_sysfs_subsys(void); 37 38static inline void opstate_init(void) 39{ 40 switch (edac_op_state) { 41 case EDAC_OPSTATE_POLL: 42 case EDAC_OPSTATE_NMI: 43 break; 44 default: 45 edac_op_state = EDAC_OPSTATE_POLL; 46 } 47 return; 48} 49 50/* Max length of a DIMM label*/ 51#define EDAC_MC_LABEL_LEN 31 52 53/* Maximum size of the location string */ 54#define LOCATION_SIZE 80 55 56/* Defines the maximum number of labels that can be reported */ 57#define EDAC_MAX_LABELS 8 58 59/* String used to join two or more labels */ 60#define OTHER_LABEL " or " 61 62/** 63 * enum dev_type - describe the type of memory DRAM chips used at the stick 64 * @DEV_UNKNOWN: Can't be determined, or MC doesn't support detect it 65 * @DEV_X1: 1 bit for data 66 * @DEV_X2: 2 bits for data 67 * @DEV_X4: 4 bits for data 68 * @DEV_X8: 8 bits for data 69 * @DEV_X16: 16 bits for data 70 * @DEV_X32: 32 bits for data 71 * @DEV_X64: 64 bits for data 72 * 73 * Typical values are x4 and x8. 74 */ 75enum dev_type { 76 DEV_UNKNOWN = 0, 77 DEV_X1, 78 DEV_X2, 79 DEV_X4, 80 DEV_X8, 81 DEV_X16, 82 DEV_X32, /* Do these parts exist? */ 83 DEV_X64 /* Do these parts exist? */ 84}; 85 86#define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN) 87#define DEV_FLAG_X1 BIT(DEV_X1) 88#define DEV_FLAG_X2 BIT(DEV_X2) 89#define DEV_FLAG_X4 BIT(DEV_X4) 90#define DEV_FLAG_X8 BIT(DEV_X8) 91#define DEV_FLAG_X16 BIT(DEV_X16) 92#define DEV_FLAG_X32 BIT(DEV_X32) 93#define DEV_FLAG_X64 BIT(DEV_X64) 94 95/** 96 * enum hw_event_mc_err_type - type of the detected error 97 * 98 * @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC 99 * corrected error was detected 100 * @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that 101 * can't be corrected by ECC, but it is not 102 * fatal (maybe it is on an unused memory area, 103 * or the memory controller could recover from 104 * it for example, by re-trying the operation). 105 * @HW_EVENT_ERR_FATAL: Fatal Error - Uncorrected error that could not 106 * be recovered. 107 */ 108enum hw_event_mc_err_type { 109 HW_EVENT_ERR_CORRECTED, 110 HW_EVENT_ERR_UNCORRECTED, 111 HW_EVENT_ERR_FATAL, 112 HW_EVENT_ERR_INFO, 113}; 114 115static inline char *mc_event_error_type(const unsigned int err_type) 116{ 117 switch (err_type) { 118 case HW_EVENT_ERR_CORRECTED: 119 return "Corrected"; 120 case HW_EVENT_ERR_UNCORRECTED: 121 return "Uncorrected"; 122 case HW_EVENT_ERR_FATAL: 123 return "Fatal"; 124 default: 125 case HW_EVENT_ERR_INFO: 126 return "Info"; 127 } 128} 129 130/** 131 * enum mem_type - memory types. For a more detailed reference, please see 132 * http://en.wikipedia.org/wiki/DRAM 133 * 134 * @MEM_EMPTY Empty csrow 135 * @MEM_RESERVED: Reserved csrow type 136 * @MEM_UNKNOWN: Unknown csrow type 137 * @MEM_FPM: FPM - Fast Page Mode, used on systems up to 1995. 138 * @MEM_EDO: EDO - Extended data out, used on systems up to 1998. 139 * @MEM_BEDO: BEDO - Burst Extended data out, an EDO variant. 140 * @MEM_SDR: SDR - Single data rate SDRAM 141 * http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory 142 * They use 3 pins for chip select: Pins 0 and 2 are 143 * for rank 0; pins 1 and 3 are for rank 1, if the memory 144 * is dual-rank. 145 * @MEM_RDR: Registered SDR SDRAM 146 * @MEM_DDR: Double data rate SDRAM 147 * http://en.wikipedia.org/wiki/DDR_SDRAM 148 * @MEM_RDDR: Registered Double data rate SDRAM 149 * This is a variant of the DDR memories. 150 * A registered memory has a buffer inside it, hiding 151 * part of the memory details to the memory controller. 152 * @MEM_RMBS: Rambus DRAM, used on a few Pentium III/IV controllers. 153 * @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F. 154 * Those memories are labed as "PC2-" instead of "PC" to 155 * differenciate from DDR. 156 * @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205 157 * and JESD206. 158 * Those memories are accessed per DIMM slot, and not by 159 * a chip select signal. 160 * @MEM_RDDR2: Registered DDR2 RAM 161 * This is a variant of the DDR2 memories. 162 * @MEM_XDR: Rambus XDR 163 * It is an evolution of the original RAMBUS memories, 164 * created to compete with DDR2. Weren't used on any 165 * x86 arch, but cell_edac PPC memory controller uses it. 166 * @MEM_DDR3: DDR3 RAM 167 * @MEM_RDDR3: Registered DDR3 RAM 168 * This is a variant of the DDR3 memories. 169 */ 170enum mem_type { 171 MEM_EMPTY = 0, 172 MEM_RESERVED, 173 MEM_UNKNOWN, 174 MEM_FPM, 175 MEM_EDO, 176 MEM_BEDO, 177 MEM_SDR, 178 MEM_RDR, 179 MEM_DDR, 180 MEM_RDDR, 181 MEM_RMBS, 182 MEM_DDR2, 183 MEM_FB_DDR2, 184 MEM_RDDR2, 185 MEM_XDR, 186 MEM_DDR3, 187 MEM_RDDR3, 188}; 189 190#define MEM_FLAG_EMPTY BIT(MEM_EMPTY) 191#define MEM_FLAG_RESERVED BIT(MEM_RESERVED) 192#define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN) 193#define MEM_FLAG_FPM BIT(MEM_FPM) 194#define MEM_FLAG_EDO BIT(MEM_EDO) 195#define MEM_FLAG_BEDO BIT(MEM_BEDO) 196#define MEM_FLAG_SDR BIT(MEM_SDR) 197#define MEM_FLAG_RDR BIT(MEM_RDR) 198#define MEM_FLAG_DDR BIT(MEM_DDR) 199#define MEM_FLAG_RDDR BIT(MEM_RDDR) 200#define MEM_FLAG_RMBS BIT(MEM_RMBS) 201#define MEM_FLAG_DDR2 BIT(MEM_DDR2) 202#define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2) 203#define MEM_FLAG_RDDR2 BIT(MEM_RDDR2) 204#define MEM_FLAG_XDR BIT(MEM_XDR) 205#define MEM_FLAG_DDR3 BIT(MEM_DDR3) 206#define MEM_FLAG_RDDR3 BIT(MEM_RDDR3) 207 208/** 209 * enum edac-type - Error Detection and Correction capabilities and mode 210 * @EDAC_UNKNOWN: Unknown if ECC is available 211 * @EDAC_NONE: Doesn't support ECC 212 * @EDAC_RESERVED: Reserved ECC type 213 * @EDAC_PARITY: Detects parity errors 214 * @EDAC_EC: Error Checking - no correction 215 * @EDAC_SECDED: Single bit error correction, Double detection 216 * @EDAC_S2ECD2ED: Chipkill x2 devices - do these exist? 217 * @EDAC_S4ECD4ED: Chipkill x4 devices 218 * @EDAC_S8ECD8ED: Chipkill x8 devices 219 * @EDAC_S16ECD16ED: Chipkill x16 devices 220 */ 221enum edac_type { 222 EDAC_UNKNOWN = 0, 223 EDAC_NONE, 224 EDAC_RESERVED, 225 EDAC_PARITY, 226 EDAC_EC, 227 EDAC_SECDED, 228 EDAC_S2ECD2ED, 229 EDAC_S4ECD4ED, 230 EDAC_S8ECD8ED, 231 EDAC_S16ECD16ED, 232}; 233 234#define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN) 235#define EDAC_FLAG_NONE BIT(EDAC_NONE) 236#define EDAC_FLAG_PARITY BIT(EDAC_PARITY) 237#define EDAC_FLAG_EC BIT(EDAC_EC) 238#define EDAC_FLAG_SECDED BIT(EDAC_SECDED) 239#define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED) 240#define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED) 241#define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED) 242#define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED) 243 244/** 245 * enum scrub_type - scrubbing capabilities 246 * @SCRUB_UNKNOWN Unknown if scrubber is available 247 * @SCRUB_NONE: No scrubber 248 * @SCRUB_SW_PROG: SW progressive (sequential) scrubbing 249 * @SCRUB_SW_SRC: Software scrub only errors 250 * @SCRUB_SW_PROG_SRC: Progressive software scrub from an error 251 * @SCRUB_SW_TUNABLE: Software scrub frequency is tunable 252 * @SCRUB_HW_PROG: HW progressive (sequential) scrubbing 253 * @SCRUB_HW_SRC: Hardware scrub only errors 254 * @SCRUB_HW_PROG_SRC: Progressive hardware scrub from an error 255 * SCRUB_HW_TUNABLE: Hardware scrub frequency is tunable 256 */ 257enum scrub_type { 258 SCRUB_UNKNOWN = 0, 259 SCRUB_NONE, 260 SCRUB_SW_PROG, 261 SCRUB_SW_SRC, 262 SCRUB_SW_PROG_SRC, 263 SCRUB_SW_TUNABLE, 264 SCRUB_HW_PROG, 265 SCRUB_HW_SRC, 266 SCRUB_HW_PROG_SRC, 267 SCRUB_HW_TUNABLE 268}; 269 270#define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG) 271#define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC) 272#define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC) 273#define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE) 274#define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG) 275#define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC) 276#define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC) 277#define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE) 278 279/* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */ 280 281/* EDAC internal operation states */ 282#define OP_ALLOC 0x100 283#define OP_RUNNING_POLL 0x201 284#define OP_RUNNING_INTERRUPT 0x202 285#define OP_RUNNING_POLL_INTR 0x203 286#define OP_OFFLINE 0x300 287 288/* 289 * Concepts used at the EDAC subsystem 290 * 291 * There are several things to be aware of that aren't at all obvious: 292 * 293 * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc.. 294 * 295 * These are some of the many terms that are thrown about that don't always 296 * mean what people think they mean (Inconceivable!). In the interest of 297 * creating a common ground for discussion, terms and their definitions 298 * will be established. 299 * 300 * Memory devices: The individual DRAM chips on a memory stick. These 301 * devices commonly output 4 and 8 bits each (x4, x8). 302 * Grouping several of these in parallel provides the 303 * number of bits that the memory controller expects: 304 * typically 72 bits, in order to provide 64 bits + 305 * 8 bits of ECC data. 306 * 307 * Memory Stick: A printed circuit board that aggregates multiple 308 * memory devices in parallel. In general, this is the 309 * Field Replaceable Unit (FRU) which gets replaced, in 310 * the case of excessive errors. Most often it is also 311 * called DIMM (Dual Inline Memory Module). 312 * 313 * Memory Socket: A physical connector on the motherboard that accepts 314 * a single memory stick. Also called as "slot" on several 315 * datasheets. 316 * 317 * Channel: A memory controller channel, responsible to communicate 318 * with a group of DIMMs. Each channel has its own 319 * independent control (command) and data bus, and can 320 * be used independently or grouped with other channels. 321 * 322 * Branch: It is typically the highest hierarchy on a 323 * Fully-Buffered DIMM memory controller. 324 * Typically, it contains two channels. 325 * Two channels at the same branch can be used in single 326 * mode or in lockstep mode. 327 * When lockstep is enabled, the cacheline is doubled, 328 * but it generally brings some performance penalty. 329 * Also, it is generally not possible to point to just one 330 * memory stick when an error occurs, as the error 331 * correction code is calculated using two DIMMs instead 332 * of one. Due to that, it is capable of correcting more 333 * errors than on single mode. 334 * 335 * Single-channel: The data accessed by the memory controller is contained 336 * into one dimm only. E. g. if the data is 64 bits-wide, 337 * the data flows to the CPU using one 64 bits parallel 338 * access. 339 * Typically used with SDR, DDR, DDR2 and DDR3 memories. 340 * FB-DIMM and RAMBUS use a different concept for channel, 341 * so this concept doesn't apply there. 342 * 343 * Double-channel: The data size accessed by the memory controller is 344 * interlaced into two dimms, accessed at the same time. 345 * E. g. if the DIMM is 64 bits-wide (72 bits with ECC), 346 * the data flows to the CPU using a 128 bits parallel 347 * access. 348 * 349 * Chip-select row: This is the name of the DRAM signal used to select the 350 * DRAM ranks to be accessed. Common chip-select rows for 351 * single channel are 64 bits, for dual channel 128 bits. 352 * It may not be visible by the memory controller, as some 353 * DIMM types have a memory buffer that can hide direct 354 * access to it from the Memory Controller. 355 * 356 * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory. 357 * Motherboards commonly drive two chip-select pins to 358 * a memory stick. A single-ranked stick, will occupy 359 * only one of those rows. The other will be unused. 360 * 361 * Double-Ranked stick: A double-ranked stick has two chip-select rows which 362 * access different sets of memory devices. The two 363 * rows cannot be accessed concurrently. 364 * 365 * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick. 366 * A double-sided stick has two chip-select rows which 367 * access different sets of memory devices. The two 368 * rows cannot be accessed concurrently. "Double-sided" 369 * is irrespective of the memory devices being mounted 370 * on both sides of the memory stick. 371 * 372 * Socket set: All of the memory sticks that are required for 373 * a single memory access or all of the memory sticks 374 * spanned by a chip-select row. A single socket set 375 * has two chip-select rows and if double-sided sticks 376 * are used these will occupy those chip-select rows. 377 * 378 * Bank: This term is avoided because it is unclear when 379 * needing to distinguish between chip-select rows and 380 * socket sets. 381 * 382 * Controller pages: 383 * 384 * Physical pages: 385 * 386 * Virtual pages: 387 * 388 * 389 * STRUCTURE ORGANIZATION AND CHOICES 390 * 391 * 392 * 393 * PS - I enjoyed writing all that about as much as you enjoyed reading it. 394 */ 395 396/** 397 * enum edac_mc_layer - memory controller hierarchy layer 398 * 399 * @EDAC_MC_LAYER_BRANCH: memory layer is named "branch" 400 * @EDAC_MC_LAYER_CHANNEL: memory layer is named "channel" 401 * @EDAC_MC_LAYER_SLOT: memory layer is named "slot" 402 * @EDAC_MC_LAYER_CHIP_SELECT: memory layer is named "chip select" 403 * @EDAC_MC_LAYER_ALL_MEM: memory layout is unknown. All memory is mapped 404 * as a single memory area. This is used when 405 * retrieving errors from a firmware driven driver. 406 * 407 * This enum is used by the drivers to tell edac_mc_sysfs what name should 408 * be used when describing a memory stick location. 409 */ 410enum edac_mc_layer_type { 411 EDAC_MC_LAYER_BRANCH, 412 EDAC_MC_LAYER_CHANNEL, 413 EDAC_MC_LAYER_SLOT, 414 EDAC_MC_LAYER_CHIP_SELECT, 415 EDAC_MC_LAYER_ALL_MEM, 416}; 417 418/** 419 * struct edac_mc_layer - describes the memory controller hierarchy 420 * @layer: layer type 421 * @size: number of components per layer. For example, 422 * if the channel layer has two channels, size = 2 423 * @is_virt_csrow: This layer is part of the "csrow" when old API 424 * compatibility mode is enabled. Otherwise, it is 425 * a channel 426 */ 427struct edac_mc_layer { 428 enum edac_mc_layer_type type; 429 unsigned size; 430 bool is_virt_csrow; 431}; 432 433/* 434 * Maximum number of layers used by the memory controller to uniquely 435 * identify a single memory stick. 436 * NOTE: Changing this constant requires not only to change the constant 437 * below, but also to change the existing code at the core, as there are 438 * some code there that are optimized for 3 layers. 439 */ 440#define EDAC_MAX_LAYERS 3 441 442/** 443 * EDAC_DIMM_OFF - Macro responsible to get a pointer offset inside a pointer array 444 * for the element given by [layer0,layer1,layer2] position 445 * 446 * @layers: a struct edac_mc_layer array, describing how many elements 447 * were allocated for each layer 448 * @n_layers: Number of layers at the @layers array 449 * @layer0: layer0 position 450 * @layer1: layer1 position. Unused if n_layers < 2 451 * @layer2: layer2 position. Unused if n_layers < 3 452 * 453 * For 1 layer, this macro returns &var[layer0] - &var 454 * For 2 layers, this macro is similar to allocate a bi-dimensional array 455 * and to return "&var[layer0][layer1] - &var" 456 * For 3 layers, this macro is similar to allocate a tri-dimensional array 457 * and to return "&var[layer0][layer1][layer2] - &var" 458 * 459 * A loop could be used here to make it more generic, but, as we only have 460 * 3 layers, this is a little faster. 461 * By design, layers can never be 0 or more than 3. If that ever happens, 462 * a NULL is returned, causing an OOPS during the memory allocation routine, 463 * with would point to the developer that he's doing something wrong. 464 */ 465#define EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2) ({ \ 466 int __i; \ 467 if ((nlayers) == 1) \ 468 __i = layer0; \ 469 else if ((nlayers) == 2) \ 470 __i = (layer1) + ((layers[1]).size * (layer0)); \ 471 else if ((nlayers) == 3) \ 472 __i = (layer2) + ((layers[2]).size * ((layer1) + \ 473 ((layers[1]).size * (layer0)))); \ 474 else \ 475 __i = -EINVAL; \ 476 __i; \ 477}) 478 479/** 480 * EDAC_DIMM_PTR - Macro responsible to get a pointer inside a pointer array 481 * for the element given by [layer0,layer1,layer2] position 482 * 483 * @layers: a struct edac_mc_layer array, describing how many elements 484 * were allocated for each layer 485 * @var: name of the var where we want to get the pointer 486 * (like mci->dimms) 487 * @n_layers: Number of layers at the @layers array 488 * @layer0: layer0 position 489 * @layer1: layer1 position. Unused if n_layers < 2 490 * @layer2: layer2 position. Unused if n_layers < 3 491 * 492 * For 1 layer, this macro returns &var[layer0] 493 * For 2 layers, this macro is similar to allocate a bi-dimensional array 494 * and to return "&var[layer0][layer1]" 495 * For 3 layers, this macro is similar to allocate a tri-dimensional array 496 * and to return "&var[layer0][layer1][layer2]" 497 */ 498#define EDAC_DIMM_PTR(layers, var, nlayers, layer0, layer1, layer2) ({ \ 499 typeof(*var) __p; \ 500 int ___i = EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2); \ 501 if (___i < 0) \ 502 __p = NULL; \ 503 else \ 504 __p = (var)[___i]; \ 505 __p; \ 506}) 507 508struct dimm_info { 509 struct device dev; 510 511 char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */ 512 513 /* Memory location data */ 514 unsigned location[EDAC_MAX_LAYERS]; 515 516 struct mem_ctl_info *mci; /* the parent */ 517 518 u32 grain; /* granularity of reported error in bytes */ 519 enum dev_type dtype; /* memory device type */ 520 enum mem_type mtype; /* memory dimm type */ 521 enum edac_type edac_mode; /* EDAC mode for this dimm */ 522 523 u32 nr_pages; /* number of pages on this dimm */ 524 525 unsigned csrow, cschannel; /* Points to the old API data */ 526}; 527 528/** 529 * struct rank_info - contains the information for one DIMM rank 530 * 531 * @chan_idx: channel number where the rank is (typically, 0 or 1) 532 * @ce_count: number of correctable errors for this rank 533 * @csrow: A pointer to the chip select row structure (the parent 534 * structure). The location of the rank is given by 535 * the (csrow->csrow_idx, chan_idx) vector. 536 * @dimm: A pointer to the DIMM structure, where the DIMM label 537 * information is stored. 538 * 539 * FIXME: Currently, the EDAC core model will assume one DIMM per rank. 540 * This is a bad assumption, but it makes this patch easier. Later 541 * patches in this series will fix this issue. 542 */ 543struct rank_info { 544 int chan_idx; 545 struct csrow_info *csrow; 546 struct dimm_info *dimm; 547 548 u32 ce_count; /* Correctable Errors for this csrow */ 549}; 550 551struct csrow_info { 552 struct device dev; 553 554 /* Used only by edac_mc_find_csrow_by_page() */ 555 unsigned long first_page; /* first page number in csrow */ 556 unsigned long last_page; /* last page number in csrow */ 557 unsigned long page_mask; /* used for interleaving - 558 * 0UL for non intlv */ 559 560 int csrow_idx; /* the chip-select row */ 561 562 u32 ue_count; /* Uncorrectable Errors for this csrow */ 563 u32 ce_count; /* Correctable Errors for this csrow */ 564 565 struct mem_ctl_info *mci; /* the parent */ 566 567 /* channel information for this csrow */ 568 u32 nr_channels; 569 struct rank_info **channels; 570}; 571 572/* 573 * struct errcount_attribute - used to store the several error counts 574 */ 575struct errcount_attribute_data { 576 int n_layers; 577 int pos[EDAC_MAX_LAYERS]; 578 int layer0, layer1, layer2; 579}; 580 581/** 582 * edac_raw_error_desc - Raw error report structure 583 * @grain: minimum granularity for an error report, in bytes 584 * @error_count: number of errors of the same type 585 * @top_layer: top layer of the error (layer[0]) 586 * @mid_layer: middle layer of the error (layer[1]) 587 * @low_layer: low layer of the error (layer[2]) 588 * @page_frame_number: page where the error happened 589 * @offset_in_page: page offset 590 * @syndrome: syndrome of the error (or 0 if unknown or if 591 * the syndrome is not applicable) 592 * @msg: error message 593 * @location: location of the error 594 * @label: label of the affected DIMM(s) 595 * @other_detail: other driver-specific detail about the error 596 * @enable_per_layer_report: if false, the error affects all layers 597 * (typically, a memory controller error) 598 */ 599struct edac_raw_error_desc { 600 /* 601 * NOTE: everything before grain won't be cleaned by 602 * edac_raw_error_desc_clean() 603 */ 604 char location[LOCATION_SIZE]; 605 char label[(EDAC_MC_LABEL_LEN + 1 + sizeof(OTHER_LABEL)) * EDAC_MAX_LABELS]; 606 long grain; 607 608 /* the vars below and grain will be cleaned on every new error report */ 609 u16 error_count; 610 int top_layer; 611 int mid_layer; 612 int low_layer; 613 unsigned long page_frame_number; 614 unsigned long offset_in_page; 615 unsigned long syndrome; 616 const char *msg; 617 const char *other_detail; 618 bool enable_per_layer_report; 619}; 620 621/* MEMORY controller information structure 622 */ 623struct mem_ctl_info { 624 struct device dev; 625 struct bus_type bus; 626 627 struct list_head link; /* for global list of mem_ctl_info structs */ 628 629 struct module *owner; /* Module owner of this control struct */ 630 631 unsigned long mtype_cap; /* memory types supported by mc */ 632 unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */ 633 unsigned long edac_cap; /* configuration capabilities - this is 634 * closely related to edac_ctl_cap. The 635 * difference is that the controller may be 636 * capable of s4ecd4ed which would be listed 637 * in edac_ctl_cap, but if channels aren't 638 * capable of s4ecd4ed then the edac_cap would 639 * not have that capability. 640 */ 641 unsigned long scrub_cap; /* chipset scrub capabilities */ 642 enum scrub_type scrub_mode; /* current scrub mode */ 643 644 /* Translates sdram memory scrub rate given in bytes/sec to the 645 internal representation and configures whatever else needs 646 to be configured. 647 */ 648 int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw); 649 650 /* Get the current sdram memory scrub rate from the internal 651 representation and converts it to the closest matching 652 bandwidth in bytes/sec. 653 */ 654 int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci); 655 656 657 /* pointer to edac checking routine */ 658 void (*edac_check) (struct mem_ctl_info * mci); 659 660 /* 661 * Remaps memory pages: controller pages to physical pages. 662 * For most MC's, this will be NULL. 663 */ 664 /* FIXME - why not send the phys page to begin with? */ 665 unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci, 666 unsigned long page); 667 int mc_idx; 668 struct csrow_info **csrows; 669 unsigned nr_csrows, num_cschannel; 670 671 /* 672 * Memory Controller hierarchy 673 * 674 * There are basically two types of memory controller: the ones that 675 * sees memory sticks ("dimms"), and the ones that sees memory ranks. 676 * All old memory controllers enumerate memories per rank, but most 677 * of the recent drivers enumerate memories per DIMM, instead. 678 * When the memory controller is per rank, csbased is true. 679 */ 680 unsigned n_layers; 681 struct edac_mc_layer *layers; 682 bool csbased; 683 684 /* 685 * DIMM info. Will eventually remove the entire csrows_info some day 686 */ 687 unsigned tot_dimms; 688 struct dimm_info **dimms; 689 690 /* 691 * FIXME - what about controllers on other busses? - IDs must be 692 * unique. dev pointer should be sufficiently unique, but 693 * BUS:SLOT.FUNC numbers may not be unique. 694 */ 695 struct device *pdev; 696 const char *mod_name; 697 const char *mod_ver; 698 const char *ctl_name; 699 const char *dev_name; 700 void *pvt_info; 701 unsigned long start_time; /* mci load start time (in jiffies) */ 702 703 /* 704 * drivers shouldn't access those fields directly, as the core 705 * already handles that. 706 */ 707 u32 ce_noinfo_count, ue_noinfo_count; 708 u32 ue_mc, ce_mc; 709 u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS]; 710 711 struct completion complete; 712 713 /* Additional top controller level attributes, but specified 714 * by the low level driver. 715 * 716 * Set by the low level driver to provide attributes at the 717 * controller level. 718 * An array of structures, NULL terminated 719 * 720 * If attributes are desired, then set to array of attributes 721 * If no attributes are desired, leave NULL 722 */ 723 const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes; 724 725 /* work struct for this MC */ 726 struct delayed_work work; 727 728 /* 729 * Used to report an error - by being at the global struct 730 * makes the memory allocated by the EDAC core 731 */ 732 struct edac_raw_error_desc error_desc; 733 734 /* the internal state of this controller instance */ 735 int op_state; 736 737#ifdef CONFIG_EDAC_DEBUG 738 struct dentry *debugfs; 739 u8 fake_inject_layer[EDAC_MAX_LAYERS]; 740 u32 fake_inject_ue; 741 u16 fake_inject_count; 742#endif 743}; 744 745#endif 746