1/* 2 * SPEAr platform shared irq layer header file 3 * 4 * Copyright (C) 2009-2012 ST Microelectronics 5 * Viresh Kumar <viresh.linux@gmail.com> 6 * 7 * This file is licensed under the terms of the GNU General Public 8 * License version 2. This program is licensed "as is" without any 9 * warranty of any kind, whether express or implied. 10 */ 11 12#ifndef __SPEAR_SHIRQ_H 13#define __SPEAR_SHIRQ_H 14 15#include <linux/irq.h> 16#include <linux/types.h> 17 18/* 19 * struct shirq_regs: shared irq register configuration 20 * 21 * enb_reg: enable register offset 22 * reset_to_enb: val 1 indicates, we need to clear bit for enabling interrupt 23 * status_reg: status register offset 24 * status_reg_mask: status register valid mask 25 * clear_reg: clear register offset 26 * reset_to_clear: val 1 indicates, we need to clear bit for clearing interrupt 27 */ 28struct shirq_regs { 29 u32 enb_reg; 30 u32 reset_to_enb; 31 u32 status_reg; 32 u32 clear_reg; 33 u32 reset_to_clear; 34}; 35 36/* 37 * struct spear_shirq: shared irq structure 38 * 39 * irq: hardware irq number 40 * irq_base: base irq in linux domain 41 * irq_nr: no. of shared interrupts in a particular block 42 * irq_bit_off: starting bit offset in the status register 43 * invalid_irq: irq group is currently disabled 44 * base: base address of shared irq register 45 * regs: register configuration for shared irq block 46 */ 47struct spear_shirq { 48 u32 irq; 49 u32 irq_base; 50 u32 irq_nr; 51 u32 irq_bit_off; 52 int invalid_irq; 53 void __iomem *base; 54 struct shirq_regs regs; 55}; 56 57int __init spear300_shirq_of_init(struct device_node *np, 58 struct device_node *parent); 59int __init spear310_shirq_of_init(struct device_node *np, 60 struct device_node *parent); 61int __init spear320_shirq_of_init(struct device_node *np, 62 struct device_node *parent); 63 64#endif /* __SPEAR_SHIRQ_H */ 65