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19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/delay.h>
24#include <linux/pm.h>
25#include <linux/i2c.h>
26#include <linux/regmap.h>
27#include <linux/spi/spi.h>
28#include <linux/slab.h>
29#include <sound/core.h>
30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/soc.h>
33#include <sound/initval.h>
34#include <sound/tlv.h>
35
36#include "wm8900.h"
37
38
39#define WM8900_REG_RESET 0x0
40#define WM8900_REG_ID 0x0
41#define WM8900_REG_POWER1 0x1
42#define WM8900_REG_POWER2 0x2
43#define WM8900_REG_POWER3 0x3
44#define WM8900_REG_AUDIO1 0x4
45#define WM8900_REG_AUDIO2 0x5
46#define WM8900_REG_CLOCKING1 0x6
47#define WM8900_REG_CLOCKING2 0x7
48#define WM8900_REG_AUDIO3 0x8
49#define WM8900_REG_AUDIO4 0x9
50#define WM8900_REG_DACCTRL 0xa
51#define WM8900_REG_LDAC_DV 0xb
52#define WM8900_REG_RDAC_DV 0xc
53#define WM8900_REG_SIDETONE 0xd
54#define WM8900_REG_ADCCTRL 0xe
55#define WM8900_REG_LADC_DV 0xf
56#define WM8900_REG_RADC_DV 0x10
57#define WM8900_REG_GPIO 0x12
58#define WM8900_REG_INCTL 0x15
59#define WM8900_REG_LINVOL 0x16
60#define WM8900_REG_RINVOL 0x17
61#define WM8900_REG_INBOOSTMIX1 0x18
62#define WM8900_REG_INBOOSTMIX2 0x19
63#define WM8900_REG_ADCPATH 0x1a
64#define WM8900_REG_AUXBOOST 0x1b
65#define WM8900_REG_ADDCTL 0x1e
66#define WM8900_REG_FLLCTL1 0x24
67#define WM8900_REG_FLLCTL2 0x25
68#define WM8900_REG_FLLCTL3 0x26
69#define WM8900_REG_FLLCTL4 0x27
70#define WM8900_REG_FLLCTL5 0x28
71#define WM8900_REG_FLLCTL6 0x29
72#define WM8900_REG_LOUTMIXCTL1 0x2c
73#define WM8900_REG_ROUTMIXCTL1 0x2d
74#define WM8900_REG_BYPASS1 0x2e
75#define WM8900_REG_BYPASS2 0x2f
76#define WM8900_REG_AUXOUT_CTL 0x30
77#define WM8900_REG_LOUT1CTL 0x33
78#define WM8900_REG_ROUT1CTL 0x34
79#define WM8900_REG_LOUT2CTL 0x35
80#define WM8900_REG_ROUT2CTL 0x36
81#define WM8900_REG_HPCTL1 0x3a
82#define WM8900_REG_OUTBIASCTL 0x73
83
84#define WM8900_MAXREG 0x80
85
86#define WM8900_REG_ADDCTL_OUT1_DIS 0x80
87#define WM8900_REG_ADDCTL_OUT2_DIS 0x40
88#define WM8900_REG_ADDCTL_VMID_DIS 0x20
89#define WM8900_REG_ADDCTL_BIAS_SRC 0x10
90#define WM8900_REG_ADDCTL_VMID_SOFTST 0x04
91#define WM8900_REG_ADDCTL_TEMP_SD 0x02
92
93#define WM8900_REG_GPIO_TEMP_ENA 0x2
94
95#define WM8900_REG_POWER1_STARTUP_BIAS_ENA 0x0100
96#define WM8900_REG_POWER1_BIAS_ENA 0x0008
97#define WM8900_REG_POWER1_VMID_BUF_ENA 0x0004
98#define WM8900_REG_POWER1_FLL_ENA 0x0040
99
100#define WM8900_REG_POWER2_SYSCLK_ENA 0x8000
101#define WM8900_REG_POWER2_ADCL_ENA 0x0002
102#define WM8900_REG_POWER2_ADCR_ENA 0x0001
103
104#define WM8900_REG_POWER3_DACL_ENA 0x0002
105#define WM8900_REG_POWER3_DACR_ENA 0x0001
106
107#define WM8900_REG_AUDIO1_AIF_FMT_MASK 0x0018
108#define WM8900_REG_AUDIO1_LRCLK_INV 0x0080
109#define WM8900_REG_AUDIO1_BCLK_INV 0x0100
110
111#define WM8900_REG_CLOCKING1_BCLK_DIR 0x1
112#define WM8900_REG_CLOCKING1_MCLK_SRC 0x100
113#define WM8900_REG_CLOCKING1_BCLK_MASK 0x01e
114#define WM8900_REG_CLOCKING1_OPCLK_MASK 0x7000
115
116#define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0
117#define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c
118
119#define WM8900_REG_DACCTRL_MUTE 0x004
120#define WM8900_REG_DACCTRL_DAC_SB_FILT 0x100
121#define WM8900_REG_DACCTRL_AIF_LRCLKRATE 0x400
122
123#define WM8900_REG_AUDIO3_ADCLRC_DIR 0x0800
124
125#define WM8900_REG_AUDIO4_DACLRC_DIR 0x0800
126
127#define WM8900_REG_FLLCTL1_OSC_ENA 0x100
128
129#define WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF 0x100
130
131#define WM8900_REG_HPCTL1_HP_IPSTAGE_ENA 0x80
132#define WM8900_REG_HPCTL1_HP_OPSTAGE_ENA 0x40
133#define WM8900_REG_HPCTL1_HP_CLAMP_IP 0x20
134#define WM8900_REG_HPCTL1_HP_CLAMP_OP 0x10
135#define WM8900_REG_HPCTL1_HP_SHORT 0x08
136#define WM8900_REG_HPCTL1_HP_SHORT2 0x04
137
138#define WM8900_LRC_MASK 0x03ff
139
140struct wm8900_priv {
141 struct regmap *regmap;
142
143 u32 fll_in;
144 u32 fll_out;
145};
146
147
148
149
150
151static const struct reg_default wm8900_reg_defaults[] = {
152 { 1, 0x0000 },
153 { 2, 0xc000 },
154 { 3, 0x0000 },
155 { 4, 0x4050 },
156 { 5, 0x4000 },
157 { 6, 0x0008 },
158 { 7, 0x0000 },
159 { 8, 0x0040 },
160 { 9, 0x0040 },
161 { 10, 0x1004 },
162 { 11, 0x00c0 },
163 { 12, 0x00c0 },
164 { 13, 0x0000 },
165 { 14, 0x0100 },
166 { 15, 0x00c0 },
167 { 16, 0x00c0 },
168 { 17, 0x0000 },
169 { 18, 0xb001 },
170 { 19, 0x0000 },
171 { 20, 0x0000 },
172 { 21, 0x0044 },
173 { 22, 0x004c },
174 { 23, 0x004c },
175 { 24, 0x0044 },
176 { 25, 0x0044 },
177 { 26, 0x0000 },
178 { 27, 0x0044 },
179 { 28, 0x0000 },
180 { 29, 0x0000 },
181 { 30, 0x0002 },
182 { 31, 0x0000 },
183 { 32, 0x0000 },
184 { 33, 0x0000 },
185 { 34, 0x0000 },
186 { 35, 0x0000 },
187 { 36, 0x0008 },
188 { 37, 0x0000 },
189 { 38, 0x0000 },
190 { 39, 0x0008 },
191 { 40, 0x0097 },
192 { 41, 0x0100 },
193 { 42, 0x0000 },
194 { 43, 0x0000 },
195 { 44, 0x0050 },
196 { 45, 0x0050 },
197 { 46, 0x0055 },
198 { 47, 0x0055 },
199 { 48, 0x0055 },
200 { 49, 0x0000 },
201 { 50, 0x0000 },
202 { 51, 0x0079 },
203 { 52, 0x0079 },
204 { 53, 0x0079 },
205 { 54, 0x0079 },
206 { 55, 0x0000 },
207};
208
209static bool wm8900_volatile_register(struct device *dev, unsigned int reg)
210{
211 switch (reg) {
212 case WM8900_REG_ID:
213 return true;
214 default:
215 return false;
216 }
217}
218
219static void wm8900_reset(struct snd_soc_codec *codec)
220{
221 snd_soc_write(codec, WM8900_REG_RESET, 0);
222}
223
224static int wm8900_hp_event(struct snd_soc_dapm_widget *w,
225 struct snd_kcontrol *kcontrol, int event)
226{
227 struct snd_soc_codec *codec = w->codec;
228 u16 hpctl1 = snd_soc_read(codec, WM8900_REG_HPCTL1);
229
230 switch (event) {
231 case SND_SOC_DAPM_PRE_PMU:
232
233 hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP |
234 WM8900_REG_HPCTL1_HP_CLAMP_OP;
235 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
236 break;
237
238 case SND_SOC_DAPM_POST_PMU:
239
240 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_IP;
241 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT |
242 WM8900_REG_HPCTL1_HP_SHORT2 |
243 WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
244 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
245
246 msleep(400);
247
248
249 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP;
250 hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
251 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
252
253
254 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2;
255 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
256 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT;
257 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
258 break;
259
260 case SND_SOC_DAPM_PRE_PMD:
261
262 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT;
263 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
264
265
266 hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
267 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
268
269
270 hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP |
271 WM8900_REG_HPCTL1_HP_CLAMP_OP;
272 hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
273 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
274 break;
275
276 case SND_SOC_DAPM_POST_PMD:
277
278 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
279 break;
280
281 default:
282 BUG();
283 }
284
285 return 0;
286}
287
288static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 100, 0);
289
290static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 0);
291
292static const DECLARE_TLV_DB_SCALE(in_boost_tlv, -1200, 600, 0);
293
294static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1200, 100, 0);
295
296static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
297
298static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
299
300static const DECLARE_TLV_DB_SCALE(adc_svol_tlv, -3600, 300, 0);
301
302static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
303
304static const char *mic_bias_level_txt[] = { "0.9*AVDD", "0.65*AVDD" };
305
306static const struct soc_enum mic_bias_level =
307SOC_ENUM_SINGLE(WM8900_REG_INCTL, 8, 2, mic_bias_level_txt);
308
309static const char *dac_mute_rate_txt[] = { "Fast", "Slow" };
310
311static const struct soc_enum dac_mute_rate =
312SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 7, 2, dac_mute_rate_txt);
313
314static const char *dac_deemphasis_txt[] = {
315 "Disabled", "32kHz", "44.1kHz", "48kHz"
316};
317
318static const struct soc_enum dac_deemphasis =
319SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 4, 4, dac_deemphasis_txt);
320
321static const char *adc_hpf_cut_txt[] = {
322 "Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"
323};
324
325static const struct soc_enum adc_hpf_cut =
326SOC_ENUM_SINGLE(WM8900_REG_ADCCTRL, 5, 4, adc_hpf_cut_txt);
327
328static const char *lr_txt[] = {
329 "Left", "Right"
330};
331
332static const struct soc_enum aifl_src =
333SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 15, 2, lr_txt);
334
335static const struct soc_enum aifr_src =
336SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 14, 2, lr_txt);
337
338static const struct soc_enum dacl_src =
339SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 15, 2, lr_txt);
340
341static const struct soc_enum dacr_src =
342SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 14, 2, lr_txt);
343
344static const char *sidetone_txt[] = {
345 "Disabled", "Left ADC", "Right ADC"
346};
347
348static const struct soc_enum dacl_sidetone =
349SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 2, 3, sidetone_txt);
350
351static const struct soc_enum dacr_sidetone =
352SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 0, 3, sidetone_txt);
353
354static const struct snd_kcontrol_new wm8900_snd_controls[] = {
355SOC_ENUM("Mic Bias Level", mic_bias_level),
356
357SOC_SINGLE_TLV("Left Input PGA Volume", WM8900_REG_LINVOL, 0, 31, 0,
358 in_pga_tlv),
359SOC_SINGLE("Left Input PGA Switch", WM8900_REG_LINVOL, 6, 1, 1),
360SOC_SINGLE("Left Input PGA ZC Switch", WM8900_REG_LINVOL, 7, 1, 0),
361
362SOC_SINGLE_TLV("Right Input PGA Volume", WM8900_REG_RINVOL, 0, 31, 0,
363 in_pga_tlv),
364SOC_SINGLE("Right Input PGA Switch", WM8900_REG_RINVOL, 6, 1, 1),
365SOC_SINGLE("Right Input PGA ZC Switch", WM8900_REG_RINVOL, 7, 1, 0),
366
367SOC_SINGLE("DAC Soft Mute Switch", WM8900_REG_DACCTRL, 6, 1, 1),
368SOC_ENUM("DAC Mute Rate", dac_mute_rate),
369SOC_SINGLE("DAC Mono Switch", WM8900_REG_DACCTRL, 9, 1, 0),
370SOC_ENUM("DAC Deemphasis", dac_deemphasis),
371SOC_SINGLE("DAC Sigma-Delta Modulator Clock Switch", WM8900_REG_DACCTRL,
372 12, 1, 0),
373
374SOC_SINGLE("ADC HPF Switch", WM8900_REG_ADCCTRL, 8, 1, 0),
375SOC_ENUM("ADC HPF Cut-Off", adc_hpf_cut),
376SOC_DOUBLE("ADC Invert Switch", WM8900_REG_ADCCTRL, 1, 0, 1, 0),
377SOC_SINGLE_TLV("Left ADC Sidetone Volume", WM8900_REG_SIDETONE, 9, 12, 0,
378 adc_svol_tlv),
379SOC_SINGLE_TLV("Right ADC Sidetone Volume", WM8900_REG_SIDETONE, 5, 12, 0,
380 adc_svol_tlv),
381SOC_ENUM("Left Digital Audio Source", aifl_src),
382SOC_ENUM("Right Digital Audio Source", aifr_src),
383
384SOC_SINGLE_TLV("DAC Input Boost Volume", WM8900_REG_AUDIO2, 10, 4, 0,
385 dac_boost_tlv),
386SOC_ENUM("Left DAC Source", dacl_src),
387SOC_ENUM("Right DAC Source", dacr_src),
388SOC_ENUM("Left DAC Sidetone", dacl_sidetone),
389SOC_ENUM("Right DAC Sidetone", dacr_sidetone),
390SOC_DOUBLE("DAC Invert Switch", WM8900_REG_DACCTRL, 1, 0, 1, 0),
391
392SOC_DOUBLE_R_TLV("Digital Playback Volume",
393 WM8900_REG_LDAC_DV, WM8900_REG_RDAC_DV,
394 1, 96, 0, dac_tlv),
395SOC_DOUBLE_R_TLV("Digital Capture Volume",
396 WM8900_REG_LADC_DV, WM8900_REG_RADC_DV, 1, 119, 0, adc_tlv),
397
398SOC_SINGLE_TLV("LINPUT3 Bypass Volume", WM8900_REG_LOUTMIXCTL1, 4, 7, 0,
399 out_mix_tlv),
400SOC_SINGLE_TLV("RINPUT3 Bypass Volume", WM8900_REG_ROUTMIXCTL1, 4, 7, 0,
401 out_mix_tlv),
402SOC_SINGLE_TLV("Left AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 4, 7, 0,
403 out_mix_tlv),
404SOC_SINGLE_TLV("Right AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 0, 7, 0,
405 out_mix_tlv),
406
407SOC_SINGLE_TLV("LeftIn to RightOut Mixer Volume", WM8900_REG_BYPASS1, 0, 7, 0,
408 out_mix_tlv),
409SOC_SINGLE_TLV("LeftIn to LeftOut Mixer Volume", WM8900_REG_BYPASS1, 4, 7, 0,
410 out_mix_tlv),
411SOC_SINGLE_TLV("RightIn to LeftOut Mixer Volume", WM8900_REG_BYPASS2, 0, 7, 0,
412 out_mix_tlv),
413SOC_SINGLE_TLV("RightIn to RightOut Mixer Volume", WM8900_REG_BYPASS2, 4, 7, 0,
414 out_mix_tlv),
415
416SOC_SINGLE_TLV("IN2L Boost Volume", WM8900_REG_INBOOSTMIX1, 0, 3, 0,
417 in_boost_tlv),
418SOC_SINGLE_TLV("IN3L Boost Volume", WM8900_REG_INBOOSTMIX1, 4, 3, 0,
419 in_boost_tlv),
420SOC_SINGLE_TLV("IN2R Boost Volume", WM8900_REG_INBOOSTMIX2, 0, 3, 0,
421 in_boost_tlv),
422SOC_SINGLE_TLV("IN3R Boost Volume", WM8900_REG_INBOOSTMIX2, 4, 3, 0,
423 in_boost_tlv),
424SOC_SINGLE_TLV("Left AUX Boost Volume", WM8900_REG_AUXBOOST, 4, 3, 0,
425 in_boost_tlv),
426SOC_SINGLE_TLV("Right AUX Boost Volume", WM8900_REG_AUXBOOST, 0, 3, 0,
427 in_boost_tlv),
428
429SOC_DOUBLE_R_TLV("LINEOUT1 Volume", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
430 0, 63, 0, out_pga_tlv),
431SOC_DOUBLE_R("LINEOUT1 Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
432 6, 1, 1),
433SOC_DOUBLE_R("LINEOUT1 ZC Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
434 7, 1, 0),
435
436SOC_DOUBLE_R_TLV("LINEOUT2 Volume",
437 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL,
438 0, 63, 0, out_pga_tlv),
439SOC_DOUBLE_R("LINEOUT2 Switch",
440 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 6, 1, 1),
441SOC_DOUBLE_R("LINEOUT2 ZC Switch",
442 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 7, 1, 0),
443SOC_SINGLE("LINEOUT2 LP -12dB", WM8900_REG_LOUTMIXCTL1,
444 0, 1, 1),
445
446};
447
448static const struct snd_kcontrol_new wm8900_dapm_loutput2_control =
449SOC_DAPM_SINGLE("LINEOUT2L Switch", WM8900_REG_POWER3, 6, 1, 0);
450
451static const struct snd_kcontrol_new wm8900_dapm_routput2_control =
452SOC_DAPM_SINGLE("LINEOUT2R Switch", WM8900_REG_POWER3, 5, 1, 0);
453
454static const struct snd_kcontrol_new wm8900_loutmix_controls[] = {
455SOC_DAPM_SINGLE("LINPUT3 Bypass Switch", WM8900_REG_LOUTMIXCTL1, 7, 1, 0),
456SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 7, 1, 0),
457SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 7, 1, 0),
458SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 3, 1, 0),
459SOC_DAPM_SINGLE("DACL Switch", WM8900_REG_LOUTMIXCTL1, 8, 1, 0),
460};
461
462static const struct snd_kcontrol_new wm8900_routmix_controls[] = {
463SOC_DAPM_SINGLE("RINPUT3 Bypass Switch", WM8900_REG_ROUTMIXCTL1, 7, 1, 0),
464SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 3, 1, 0),
465SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 3, 1, 0),
466SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 7, 1, 0),
467SOC_DAPM_SINGLE("DACR Switch", WM8900_REG_ROUTMIXCTL1, 8, 1, 0),
468};
469
470static const struct snd_kcontrol_new wm8900_linmix_controls[] = {
471SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INBOOSTMIX1, 2, 1, 1),
472SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INBOOSTMIX1, 6, 1, 1),
473SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 6, 1, 1),
474SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 6, 1, 0),
475};
476
477static const struct snd_kcontrol_new wm8900_rinmix_controls[] = {
478SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INBOOSTMIX2, 2, 1, 1),
479SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INBOOSTMIX2, 6, 1, 1),
480SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 2, 1, 1),
481SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 2, 1, 0),
482};
483
484static const struct snd_kcontrol_new wm8900_linpga_controls[] = {
485SOC_DAPM_SINGLE("LINPUT1 Switch", WM8900_REG_INCTL, 6, 1, 0),
486SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INCTL, 5, 1, 0),
487SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INCTL, 4, 1, 0),
488};
489
490static const struct snd_kcontrol_new wm8900_rinpga_controls[] = {
491SOC_DAPM_SINGLE("RINPUT1 Switch", WM8900_REG_INCTL, 2, 1, 0),
492SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INCTL, 1, 1, 0),
493SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INCTL, 0, 1, 0),
494};
495
496static const char *wm8900_lp_mux[] = { "Disabled", "Enabled" };
497
498static const struct soc_enum wm8900_lineout2_lp_mux =
499SOC_ENUM_SINGLE(WM8900_REG_LOUTMIXCTL1, 1, 2, wm8900_lp_mux);
500
501static const struct snd_kcontrol_new wm8900_lineout2_lp =
502SOC_DAPM_ENUM("Route", wm8900_lineout2_lp_mux);
503
504static const struct snd_soc_dapm_widget wm8900_dapm_widgets[] = {
505
506
507SND_SOC_DAPM_OUTPUT("LINEOUT1L"),
508SND_SOC_DAPM_OUTPUT("LINEOUT1R"),
509SND_SOC_DAPM_OUTPUT("LINEOUT2L"),
510SND_SOC_DAPM_OUTPUT("LINEOUT2R"),
511SND_SOC_DAPM_OUTPUT("HP_L"),
512SND_SOC_DAPM_OUTPUT("HP_R"),
513
514SND_SOC_DAPM_INPUT("RINPUT1"),
515SND_SOC_DAPM_INPUT("LINPUT1"),
516SND_SOC_DAPM_INPUT("RINPUT2"),
517SND_SOC_DAPM_INPUT("LINPUT2"),
518SND_SOC_DAPM_INPUT("RINPUT3"),
519SND_SOC_DAPM_INPUT("LINPUT3"),
520SND_SOC_DAPM_INPUT("AUX"),
521
522SND_SOC_DAPM_VMID("VMID"),
523
524
525SND_SOC_DAPM_MIXER("Left Input PGA", WM8900_REG_POWER2, 3, 0,
526 wm8900_linpga_controls,
527 ARRAY_SIZE(wm8900_linpga_controls)),
528SND_SOC_DAPM_MIXER("Right Input PGA", WM8900_REG_POWER2, 2, 0,
529 wm8900_rinpga_controls,
530 ARRAY_SIZE(wm8900_rinpga_controls)),
531
532SND_SOC_DAPM_MIXER("Left Input Mixer", WM8900_REG_POWER2, 5, 0,
533 wm8900_linmix_controls,
534 ARRAY_SIZE(wm8900_linmix_controls)),
535SND_SOC_DAPM_MIXER("Right Input Mixer", WM8900_REG_POWER2, 4, 0,
536 wm8900_rinmix_controls,
537 ARRAY_SIZE(wm8900_rinmix_controls)),
538
539SND_SOC_DAPM_SUPPLY("Mic Bias", WM8900_REG_POWER1, 4, 0, NULL, 0),
540
541SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8900_REG_POWER2, 1, 0),
542SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8900_REG_POWER2, 0, 0),
543
544
545SND_SOC_DAPM_DAC("DACL", "Left HiFi Playback", WM8900_REG_POWER3, 1, 0),
546SND_SOC_DAPM_DAC("DACR", "Right HiFi Playback", WM8900_REG_POWER3, 0, 0),
547
548SND_SOC_DAPM_PGA_E("Headphone Amplifier", WM8900_REG_POWER3, 7, 0, NULL, 0,
549 wm8900_hp_event,
550 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
551 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
552
553SND_SOC_DAPM_PGA("LINEOUT1L PGA", WM8900_REG_POWER2, 8, 0, NULL, 0),
554SND_SOC_DAPM_PGA("LINEOUT1R PGA", WM8900_REG_POWER2, 7, 0, NULL, 0),
555
556SND_SOC_DAPM_MUX("LINEOUT2 LP", SND_SOC_NOPM, 0, 0, &wm8900_lineout2_lp),
557SND_SOC_DAPM_PGA("LINEOUT2L PGA", WM8900_REG_POWER3, 6, 0, NULL, 0),
558SND_SOC_DAPM_PGA("LINEOUT2R PGA", WM8900_REG_POWER3, 5, 0, NULL, 0),
559
560SND_SOC_DAPM_MIXER("Left Output Mixer", WM8900_REG_POWER3, 3, 0,
561 wm8900_loutmix_controls,
562 ARRAY_SIZE(wm8900_loutmix_controls)),
563SND_SOC_DAPM_MIXER("Right Output Mixer", WM8900_REG_POWER3, 2, 0,
564 wm8900_routmix_controls,
565 ARRAY_SIZE(wm8900_routmix_controls)),
566};
567
568
569static const struct snd_soc_dapm_route wm8900_dapm_routes[] = {
570
571{"Left Input PGA", "LINPUT1 Switch", "LINPUT1"},
572{"Left Input PGA", "LINPUT2 Switch", "LINPUT2"},
573{"Left Input PGA", "LINPUT3 Switch", "LINPUT3"},
574
575{"Right Input PGA", "RINPUT1 Switch", "RINPUT1"},
576{"Right Input PGA", "RINPUT2 Switch", "RINPUT2"},
577{"Right Input PGA", "RINPUT3 Switch", "RINPUT3"},
578
579{"Left Input Mixer", "LINPUT2 Switch", "LINPUT2"},
580{"Left Input Mixer", "LINPUT3 Switch", "LINPUT3"},
581{"Left Input Mixer", "AUX Switch", "AUX"},
582{"Left Input Mixer", "Input PGA Switch", "Left Input PGA"},
583
584{"Right Input Mixer", "RINPUT2 Switch", "RINPUT2"},
585{"Right Input Mixer", "RINPUT3 Switch", "RINPUT3"},
586{"Right Input Mixer", "AUX Switch", "AUX"},
587{"Right Input Mixer", "Input PGA Switch", "Right Input PGA"},
588
589{"ADCL", NULL, "Left Input Mixer"},
590{"ADCR", NULL, "Right Input Mixer"},
591
592
593{"LINEOUT1L", NULL, "LINEOUT1L PGA"},
594{"LINEOUT1L PGA", NULL, "Left Output Mixer"},
595{"LINEOUT1R", NULL, "LINEOUT1R PGA"},
596{"LINEOUT1R PGA", NULL, "Right Output Mixer"},
597
598{"LINEOUT2L PGA", NULL, "Left Output Mixer"},
599{"LINEOUT2 LP", "Disabled", "LINEOUT2L PGA"},
600{"LINEOUT2 LP", "Enabled", "Left Output Mixer"},
601{"LINEOUT2L", NULL, "LINEOUT2 LP"},
602
603{"LINEOUT2R PGA", NULL, "Right Output Mixer"},
604{"LINEOUT2 LP", "Disabled", "LINEOUT2R PGA"},
605{"LINEOUT2 LP", "Enabled", "Right Output Mixer"},
606{"LINEOUT2R", NULL, "LINEOUT2 LP"},
607
608{"Left Output Mixer", "LINPUT3 Bypass Switch", "LINPUT3"},
609{"Left Output Mixer", "AUX Bypass Switch", "AUX"},
610{"Left Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
611{"Left Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
612{"Left Output Mixer", "DACL Switch", "DACL"},
613
614{"Right Output Mixer", "RINPUT3 Bypass Switch", "RINPUT3"},
615{"Right Output Mixer", "AUX Bypass Switch", "AUX"},
616{"Right Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
617{"Right Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
618{"Right Output Mixer", "DACR Switch", "DACR"},
619
620
621
622
623
624
625
626
627{"Headphone Amplifier", NULL, "LINEOUT2 LP"},
628{"Headphone Amplifier", NULL, "LINEOUT2 LP"},
629{"HP_L", NULL, "Headphone Amplifier"},
630{"HP_R", NULL, "Headphone Amplifier"},
631};
632
633static int wm8900_hw_params(struct snd_pcm_substream *substream,
634 struct snd_pcm_hw_params *params,
635 struct snd_soc_dai *dai)
636{
637 struct snd_soc_codec *codec = dai->codec;
638 u16 reg;
639
640 reg = snd_soc_read(codec, WM8900_REG_AUDIO1) & ~0x60;
641
642 switch (params_format(params)) {
643 case SNDRV_PCM_FORMAT_S16_LE:
644 break;
645 case SNDRV_PCM_FORMAT_S20_3LE:
646 reg |= 0x20;
647 break;
648 case SNDRV_PCM_FORMAT_S24_LE:
649 reg |= 0x40;
650 break;
651 case SNDRV_PCM_FORMAT_S32_LE:
652 reg |= 0x60;
653 break;
654 default:
655 return -EINVAL;
656 }
657
658 snd_soc_write(codec, WM8900_REG_AUDIO1, reg);
659
660 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
661 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
662
663 if (params_rate(params) <= 24000)
664 reg |= WM8900_REG_DACCTRL_DAC_SB_FILT;
665 else
666 reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT;
667
668 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
669 }
670
671 return 0;
672}
673
674
675struct _fll_div {
676 u16 fll_ratio;
677 u16 fllclk_div;
678 u16 fll_slow_lock_ref;
679 u16 n;
680 u16 k;
681};
682
683
684
685#define FIXED_FLL_SIZE ((1 << 16) * 10)
686
687static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
688 unsigned int Fout)
689{
690 u64 Kpart;
691 unsigned int K, Ndiv, Nmod, target;
692 unsigned int div;
693
694 BUG_ON(!Fout);
695
696
697
698 target = Fout;
699 div = 1;
700 while (target < 90000000) {
701 div *= 2;
702 target *= 2;
703 }
704
705 if (target > 100000000)
706 printk(KERN_WARNING "wm8900: FLL rate %u out of range, Fref=%u"
707 " Fout=%u\n", target, Fref, Fout);
708 if (div > 32) {
709 printk(KERN_ERR "wm8900: Invalid FLL division rate %u, "
710 "Fref=%u, Fout=%u, target=%u\n",
711 div, Fref, Fout, target);
712 return -EINVAL;
713 }
714
715 fll_div->fllclk_div = div >> 2;
716
717 if (Fref < 48000)
718 fll_div->fll_slow_lock_ref = 1;
719 else
720 fll_div->fll_slow_lock_ref = 0;
721
722 Ndiv = target / Fref;
723
724 if (Fref < 1000000)
725 fll_div->fll_ratio = 8;
726 else
727 fll_div->fll_ratio = 1;
728
729 fll_div->n = Ndiv / fll_div->fll_ratio;
730 Nmod = (target / fll_div->fll_ratio) % Fref;
731
732
733 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
734
735 do_div(Kpart, Fref);
736
737 K = Kpart & 0xFFFFFFFF;
738
739 if ((K % 10) >= 5)
740 K += 5;
741
742
743 fll_div->k = K / 10;
744
745 BUG_ON(target != Fout * (fll_div->fllclk_div << 2));
746 BUG_ON(!K && target != Fref * fll_div->fll_ratio * fll_div->n);
747
748 return 0;
749}
750
751static int wm8900_set_fll(struct snd_soc_codec *codec,
752 int fll_id, unsigned int freq_in, unsigned int freq_out)
753{
754 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
755 struct _fll_div fll_div;
756
757 if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out)
758 return 0;
759
760
761 snd_soc_update_bits(codec, WM8900_REG_POWER1,
762 WM8900_REG_POWER1_FLL_ENA, 0);
763
764
765 if (!freq_in || !freq_out) {
766 snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
767 WM8900_REG_CLOCKING1_MCLK_SRC, 0);
768 snd_soc_update_bits(codec, WM8900_REG_FLLCTL1,
769 WM8900_REG_FLLCTL1_OSC_ENA, 0);
770 wm8900->fll_in = freq_in;
771 wm8900->fll_out = freq_out;
772
773 return 0;
774 }
775
776 if (fll_factors(&fll_div, freq_in, freq_out) != 0)
777 goto reenable;
778
779 wm8900->fll_in = freq_in;
780 wm8900->fll_out = freq_out;
781
782
783
784 snd_soc_write(codec, WM8900_REG_FLLCTL1,
785 fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA);
786
787 snd_soc_write(codec, WM8900_REG_FLLCTL4, fll_div.n >> 5);
788 snd_soc_write(codec, WM8900_REG_FLLCTL5,
789 (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f));
790
791 if (fll_div.k) {
792 snd_soc_write(codec, WM8900_REG_FLLCTL2,
793 (fll_div.k >> 8) | 0x100);
794 snd_soc_write(codec, WM8900_REG_FLLCTL3, fll_div.k & 0xff);
795 } else
796 snd_soc_write(codec, WM8900_REG_FLLCTL2, 0);
797
798 if (fll_div.fll_slow_lock_ref)
799 snd_soc_write(codec, WM8900_REG_FLLCTL6,
800 WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF);
801 else
802 snd_soc_write(codec, WM8900_REG_FLLCTL6, 0);
803
804 snd_soc_update_bits(codec, WM8900_REG_POWER1,
805 WM8900_REG_POWER1_FLL_ENA,
806 WM8900_REG_POWER1_FLL_ENA);
807
808reenable:
809 snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
810 WM8900_REG_CLOCKING1_MCLK_SRC,
811 WM8900_REG_CLOCKING1_MCLK_SRC);
812 return 0;
813}
814
815static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
816 int source, unsigned int freq_in, unsigned int freq_out)
817{
818 return wm8900_set_fll(codec_dai->codec, pll_id, freq_in, freq_out);
819}
820
821static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
822 int div_id, int div)
823{
824 struct snd_soc_codec *codec = codec_dai->codec;
825
826 switch (div_id) {
827 case WM8900_BCLK_DIV:
828 snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
829 WM8900_REG_CLOCKING1_BCLK_MASK, div);
830 break;
831 case WM8900_OPCLK_DIV:
832 snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
833 WM8900_REG_CLOCKING1_OPCLK_MASK, div);
834 break;
835 case WM8900_DAC_LRCLK:
836 snd_soc_update_bits(codec, WM8900_REG_AUDIO4,
837 WM8900_LRC_MASK, div);
838 break;
839 case WM8900_ADC_LRCLK:
840 snd_soc_update_bits(codec, WM8900_REG_AUDIO3,
841 WM8900_LRC_MASK, div);
842 break;
843 case WM8900_DAC_CLKDIV:
844 snd_soc_update_bits(codec, WM8900_REG_CLOCKING2,
845 WM8900_REG_CLOCKING2_DAC_CLKDIV, div);
846 break;
847 case WM8900_ADC_CLKDIV:
848 snd_soc_update_bits(codec, WM8900_REG_CLOCKING2,
849 WM8900_REG_CLOCKING2_ADC_CLKDIV, div);
850 break;
851 case WM8900_LRCLK_MODE:
852 snd_soc_update_bits(codec, WM8900_REG_DACCTRL,
853 WM8900_REG_DACCTRL_AIF_LRCLKRATE, div);
854 break;
855 default:
856 return -EINVAL;
857 }
858
859 return 0;
860}
861
862
863static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai,
864 unsigned int fmt)
865{
866 struct snd_soc_codec *codec = codec_dai->codec;
867 unsigned int clocking1, aif1, aif3, aif4;
868
869 clocking1 = snd_soc_read(codec, WM8900_REG_CLOCKING1);
870 aif1 = snd_soc_read(codec, WM8900_REG_AUDIO1);
871 aif3 = snd_soc_read(codec, WM8900_REG_AUDIO3);
872 aif4 = snd_soc_read(codec, WM8900_REG_AUDIO4);
873
874
875 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
876 case SND_SOC_DAIFMT_CBS_CFS:
877 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
878 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
879 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
880 break;
881 case SND_SOC_DAIFMT_CBS_CFM:
882 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
883 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
884 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
885 break;
886 case SND_SOC_DAIFMT_CBM_CFM:
887 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
888 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
889 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
890 break;
891 case SND_SOC_DAIFMT_CBM_CFS:
892 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
893 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
894 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
895 break;
896 default:
897 return -EINVAL;
898 }
899
900 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
901 case SND_SOC_DAIFMT_DSP_A:
902 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
903 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
904 break;
905 case SND_SOC_DAIFMT_DSP_B:
906 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
907 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
908 break;
909 case SND_SOC_DAIFMT_I2S:
910 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
911 aif1 |= 0x10;
912 break;
913 case SND_SOC_DAIFMT_RIGHT_J:
914 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
915 break;
916 case SND_SOC_DAIFMT_LEFT_J:
917 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
918 aif1 |= 0x8;
919 break;
920 default:
921 return -EINVAL;
922 }
923
924
925 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
926 case SND_SOC_DAIFMT_DSP_A:
927 case SND_SOC_DAIFMT_DSP_B:
928
929 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
930 case SND_SOC_DAIFMT_NB_NF:
931 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
932 break;
933 case SND_SOC_DAIFMT_IB_NF:
934 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
935 break;
936 default:
937 return -EINVAL;
938 }
939 break;
940 case SND_SOC_DAIFMT_I2S:
941 case SND_SOC_DAIFMT_RIGHT_J:
942 case SND_SOC_DAIFMT_LEFT_J:
943 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
944 case SND_SOC_DAIFMT_NB_NF:
945 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
946 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
947 break;
948 case SND_SOC_DAIFMT_IB_IF:
949 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
950 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
951 break;
952 case SND_SOC_DAIFMT_IB_NF:
953 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
954 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
955 break;
956 case SND_SOC_DAIFMT_NB_IF:
957 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
958 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
959 break;
960 default:
961 return -EINVAL;
962 }
963 break;
964 default:
965 return -EINVAL;
966 }
967
968 snd_soc_write(codec, WM8900_REG_CLOCKING1, clocking1);
969 snd_soc_write(codec, WM8900_REG_AUDIO1, aif1);
970 snd_soc_write(codec, WM8900_REG_AUDIO3, aif3);
971 snd_soc_write(codec, WM8900_REG_AUDIO4, aif4);
972
973 return 0;
974}
975
976static int wm8900_digital_mute(struct snd_soc_dai *codec_dai, int mute)
977{
978 struct snd_soc_codec *codec = codec_dai->codec;
979 u16 reg;
980
981 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
982
983 if (mute)
984 reg |= WM8900_REG_DACCTRL_MUTE;
985 else
986 reg &= ~WM8900_REG_DACCTRL_MUTE;
987
988 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
989
990 return 0;
991}
992
993#define WM8900_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
994 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
995 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
996
997#define WM8900_PCM_FORMATS \
998 (SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \
999 SNDRV_PCM_FORMAT_S24_LE)
1000
1001static const struct snd_soc_dai_ops wm8900_dai_ops = {
1002 .hw_params = wm8900_hw_params,
1003 .set_clkdiv = wm8900_set_dai_clkdiv,
1004 .set_pll = wm8900_set_dai_pll,
1005 .set_fmt = wm8900_set_dai_fmt,
1006 .digital_mute = wm8900_digital_mute,
1007};
1008
1009static struct snd_soc_dai_driver wm8900_dai = {
1010 .name = "wm8900-hifi",
1011 .playback = {
1012 .stream_name = "HiFi Playback",
1013 .channels_min = 1,
1014 .channels_max = 2,
1015 .rates = WM8900_RATES,
1016 .formats = WM8900_PCM_FORMATS,
1017 },
1018 .capture = {
1019 .stream_name = "HiFi Capture",
1020 .channels_min = 1,
1021 .channels_max = 2,
1022 .rates = WM8900_RATES,
1023 .formats = WM8900_PCM_FORMATS,
1024 },
1025 .ops = &wm8900_dai_ops,
1026};
1027
1028static int wm8900_set_bias_level(struct snd_soc_codec *codec,
1029 enum snd_soc_bias_level level)
1030{
1031 u16 reg;
1032
1033 switch (level) {
1034 case SND_SOC_BIAS_ON:
1035
1036 snd_soc_update_bits(codec, WM8900_REG_GPIO,
1037 WM8900_REG_GPIO_TEMP_ENA,
1038 WM8900_REG_GPIO_TEMP_ENA);
1039 snd_soc_update_bits(codec, WM8900_REG_ADDCTL,
1040 WM8900_REG_ADDCTL_TEMP_SD,
1041 WM8900_REG_ADDCTL_TEMP_SD);
1042 break;
1043
1044 case SND_SOC_BIAS_PREPARE:
1045 break;
1046
1047 case SND_SOC_BIAS_STANDBY:
1048
1049 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1050
1051 snd_soc_write(codec, WM8900_REG_POWER1,
1052 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1053
1054
1055 snd_soc_write(codec, WM8900_REG_ADDCTL,
1056 WM8900_REG_ADDCTL_BIAS_SRC |
1057 WM8900_REG_ADDCTL_VMID_SOFTST);
1058
1059
1060 snd_soc_write(codec, WM8900_REG_POWER1,
1061 WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1);
1062
1063
1064 schedule_timeout_interruptible(msecs_to_jiffies(400));
1065
1066
1067 snd_soc_write(codec, WM8900_REG_POWER1,
1068 WM8900_REG_POWER1_STARTUP_BIAS_ENA |
1069 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1070
1071 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
1072
1073 snd_soc_write(codec, WM8900_REG_POWER1,
1074 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1075 }
1076
1077 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1078 snd_soc_write(codec, WM8900_REG_POWER1,
1079 (reg & WM8900_REG_POWER1_FLL_ENA) |
1080 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1081 snd_soc_write(codec, WM8900_REG_POWER2,
1082 WM8900_REG_POWER2_SYSCLK_ENA);
1083 snd_soc_write(codec, WM8900_REG_POWER3, 0);
1084 break;
1085
1086 case SND_SOC_BIAS_OFF:
1087
1088 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1089 snd_soc_write(codec, WM8900_REG_POWER1,
1090 reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1091 snd_soc_write(codec, WM8900_REG_ADDCTL,
1092 WM8900_REG_ADDCTL_BIAS_SRC |
1093 WM8900_REG_ADDCTL_VMID_SOFTST);
1094
1095
1096 snd_soc_write(codec, WM8900_REG_POWER1,
1097 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1098 schedule_timeout_interruptible(msecs_to_jiffies(500));
1099
1100
1101 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
1102
1103
1104 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
1105 snd_soc_write(codec, WM8900_REG_POWER1, 0);
1106 snd_soc_write(codec, WM8900_REG_POWER2, 0);
1107 snd_soc_write(codec, WM8900_REG_POWER3, 0);
1108
1109
1110
1111
1112 schedule_timeout_interruptible(msecs_to_jiffies(1));
1113 snd_soc_write(codec, WM8900_REG_POWER2,
1114 WM8900_REG_POWER2_SYSCLK_ENA);
1115 break;
1116 }
1117 codec->dapm.bias_level = level;
1118 return 0;
1119}
1120
1121static int wm8900_suspend(struct snd_soc_codec *codec)
1122{
1123 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
1124 int fll_out = wm8900->fll_out;
1125 int fll_in = wm8900->fll_in;
1126 int ret;
1127
1128
1129 ret = wm8900_set_fll(codec, 0, 0, 0);
1130 if (ret != 0) {
1131 dev_err(codec->dev, "Failed to stop FLL\n");
1132 return ret;
1133 }
1134
1135 wm8900->fll_out = fll_out;
1136 wm8900->fll_in = fll_in;
1137
1138 wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF);
1139
1140 return 0;
1141}
1142
1143static int wm8900_resume(struct snd_soc_codec *codec)
1144{
1145 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
1146 int ret;
1147
1148 wm8900_reset(codec);
1149
1150 ret = regcache_sync(wm8900->regmap);
1151 if (ret != 0) {
1152 dev_err(codec->dev, "Failed to restore cache: %d\n", ret);
1153 return ret;
1154 }
1155
1156 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1157
1158
1159 if (wm8900->fll_out) {
1160 int fll_out = wm8900->fll_out;
1161 int fll_in = wm8900->fll_in;
1162
1163 wm8900->fll_in = 0;
1164 wm8900->fll_out = 0;
1165
1166 ret = wm8900_set_fll(codec, 0, fll_in, fll_out);
1167 if (ret != 0) {
1168 dev_err(codec->dev, "Failed to restart FLL\n");
1169 return ret;
1170 }
1171 }
1172
1173 return 0;
1174}
1175
1176static int wm8900_probe(struct snd_soc_codec *codec)
1177{
1178 int ret = 0, reg;
1179
1180 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP);
1181 if (ret != 0) {
1182 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1183 return ret;
1184 }
1185
1186 reg = snd_soc_read(codec, WM8900_REG_ID);
1187 if (reg != 0x8900) {
1188 dev_err(codec->dev, "Device is not a WM8900 - ID %x\n", reg);
1189 return -ENODEV;
1190 }
1191
1192 wm8900_reset(codec);
1193
1194
1195 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1196
1197
1198 snd_soc_update_bits(codec, WM8900_REG_LINVOL, 0x100, 0x100);
1199 snd_soc_update_bits(codec, WM8900_REG_RINVOL, 0x100, 0x100);
1200 snd_soc_update_bits(codec, WM8900_REG_LOUT1CTL, 0x100, 0x100);
1201 snd_soc_update_bits(codec, WM8900_REG_ROUT1CTL, 0x100, 0x100);
1202 snd_soc_update_bits(codec, WM8900_REG_LOUT2CTL, 0x100, 0x100);
1203 snd_soc_update_bits(codec, WM8900_REG_ROUT2CTL, 0x100, 0x100);
1204 snd_soc_update_bits(codec, WM8900_REG_LDAC_DV, 0x100, 0x100);
1205 snd_soc_update_bits(codec, WM8900_REG_RDAC_DV, 0x100, 0x100);
1206 snd_soc_update_bits(codec, WM8900_REG_LADC_DV, 0x100, 0x100);
1207 snd_soc_update_bits(codec, WM8900_REG_RADC_DV, 0x100, 0x100);
1208
1209
1210 snd_soc_write(codec, WM8900_REG_OUTBIASCTL, 0x81);
1211
1212 return 0;
1213}
1214
1215
1216static int wm8900_remove(struct snd_soc_codec *codec)
1217{
1218 wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF);
1219 return 0;
1220}
1221
1222static struct snd_soc_codec_driver soc_codec_dev_wm8900 = {
1223 .probe = wm8900_probe,
1224 .remove = wm8900_remove,
1225 .suspend = wm8900_suspend,
1226 .resume = wm8900_resume,
1227 .set_bias_level = wm8900_set_bias_level,
1228
1229 .controls = wm8900_snd_controls,
1230 .num_controls = ARRAY_SIZE(wm8900_snd_controls),
1231 .dapm_widgets = wm8900_dapm_widgets,
1232 .num_dapm_widgets = ARRAY_SIZE(wm8900_dapm_widgets),
1233 .dapm_routes = wm8900_dapm_routes,
1234 .num_dapm_routes = ARRAY_SIZE(wm8900_dapm_routes),
1235};
1236
1237static const struct regmap_config wm8900_regmap = {
1238 .reg_bits = 8,
1239 .val_bits = 16,
1240 .max_register = WM8900_MAXREG,
1241
1242 .reg_defaults = wm8900_reg_defaults,
1243 .num_reg_defaults = ARRAY_SIZE(wm8900_reg_defaults),
1244 .cache_type = REGCACHE_RBTREE,
1245
1246 .volatile_reg = wm8900_volatile_register,
1247};
1248
1249#if defined(CONFIG_SPI_MASTER)
1250static int wm8900_spi_probe(struct spi_device *spi)
1251{
1252 struct wm8900_priv *wm8900;
1253 int ret;
1254
1255 wm8900 = devm_kzalloc(&spi->dev, sizeof(struct wm8900_priv),
1256 GFP_KERNEL);
1257 if (wm8900 == NULL)
1258 return -ENOMEM;
1259
1260 wm8900->regmap = devm_regmap_init_spi(spi, &wm8900_regmap);
1261 if (IS_ERR(wm8900->regmap))
1262 return PTR_ERR(wm8900->regmap);
1263
1264 spi_set_drvdata(spi, wm8900);
1265
1266 ret = snd_soc_register_codec(&spi->dev,
1267 &soc_codec_dev_wm8900, &wm8900_dai, 1);
1268
1269 return ret;
1270}
1271
1272static int wm8900_spi_remove(struct spi_device *spi)
1273{
1274 snd_soc_unregister_codec(&spi->dev);
1275 return 0;
1276}
1277
1278static struct spi_driver wm8900_spi_driver = {
1279 .driver = {
1280 .name = "wm8900",
1281 .owner = THIS_MODULE,
1282 },
1283 .probe = wm8900_spi_probe,
1284 .remove = wm8900_spi_remove,
1285};
1286#endif
1287
1288#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1289static int wm8900_i2c_probe(struct i2c_client *i2c,
1290 const struct i2c_device_id *id)
1291{
1292 struct wm8900_priv *wm8900;
1293 int ret;
1294
1295 wm8900 = devm_kzalloc(&i2c->dev, sizeof(struct wm8900_priv),
1296 GFP_KERNEL);
1297 if (wm8900 == NULL)
1298 return -ENOMEM;
1299
1300 wm8900->regmap = devm_regmap_init_i2c(i2c, &wm8900_regmap);
1301 if (IS_ERR(wm8900->regmap))
1302 return PTR_ERR(wm8900->regmap);
1303
1304 i2c_set_clientdata(i2c, wm8900);
1305
1306 ret = snd_soc_register_codec(&i2c->dev,
1307 &soc_codec_dev_wm8900, &wm8900_dai, 1);
1308
1309 return ret;
1310}
1311
1312static int wm8900_i2c_remove(struct i2c_client *client)
1313{
1314 snd_soc_unregister_codec(&client->dev);
1315 return 0;
1316}
1317
1318static const struct i2c_device_id wm8900_i2c_id[] = {
1319 { "wm8900", 0 },
1320 { }
1321};
1322MODULE_DEVICE_TABLE(i2c, wm8900_i2c_id);
1323
1324static struct i2c_driver wm8900_i2c_driver = {
1325 .driver = {
1326 .name = "wm8900",
1327 .owner = THIS_MODULE,
1328 },
1329 .probe = wm8900_i2c_probe,
1330 .remove = wm8900_i2c_remove,
1331 .id_table = wm8900_i2c_id,
1332};
1333#endif
1334
1335static int __init wm8900_modinit(void)
1336{
1337 int ret = 0;
1338#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1339 ret = i2c_add_driver(&wm8900_i2c_driver);
1340 if (ret != 0) {
1341 printk(KERN_ERR "Failed to register wm8900 I2C driver: %d\n",
1342 ret);
1343 }
1344#endif
1345#if defined(CONFIG_SPI_MASTER)
1346 ret = spi_register_driver(&wm8900_spi_driver);
1347 if (ret != 0) {
1348 printk(KERN_ERR "Failed to register wm8900 SPI driver: %d\n",
1349 ret);
1350 }
1351#endif
1352 return ret;
1353}
1354module_init(wm8900_modinit);
1355
1356static void __exit wm8900_exit(void)
1357{
1358#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1359 i2c_del_driver(&wm8900_i2c_driver);
1360#endif
1361#if defined(CONFIG_SPI_MASTER)
1362 spi_unregister_driver(&wm8900_spi_driver);
1363#endif
1364}
1365module_exit(wm8900_exit);
1366
1367MODULE_DESCRIPTION("ASoC WM8900 driver");
1368MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfonmicro.com>");
1369MODULE_LICENSE("GPL");
1370
