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26#include <linux/platform_device.h>
27#include <linux/gpio.h>
28#include <linux/mtd/partitions.h>
29
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32
33#include <mach/common.h>
34#include <linux/platform_data/i2c-davinci.h>
35#include <mach/serial.h>
36#include <mach/mux.h>
37#include <linux/platform_data/mtd-davinci.h>
38#include <linux/platform_data/mmc-davinci.h>
39#include <linux/platform_data/usb-davinci.h>
40
41#include "davinci.h"
42
43#define NEUROS_OSD2_PHY_ID "davinci_mdio-0:01"
44#define LXT971_PHY_ID 0x001378e2
45#define LXT971_PHY_MASK 0xfffffff0
46
47#define NTOSD2_AUDIOSOC_I2C_ADDR 0x18
48#define NTOSD2_MSP430_I2C_ADDR 0x59
49#define NTOSD2_MSP430_IRQ 2
50
51
52
53
54
55
56#define NAND_BLOCK_SIZE SZ_128K
57
58static struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
59 {
60
61 .name = "bootloader",
62 .offset = 0,
63 .size = 15 * NAND_BLOCK_SIZE,
64 .mask_flags = MTD_WRITEABLE,
65 }, {
66
67 .name = "params",
68 .offset = MTDPART_OFS_APPEND,
69 .size = 1 * NAND_BLOCK_SIZE,
70 .mask_flags = 0,
71 }, {
72
73 .name = "kernel",
74 .offset = MTDPART_OFS_APPEND,
75 .size = SZ_4M,
76 .mask_flags = 0,
77 }, {
78
79 .name = "filesystem",
80 .offset = MTDPART_OFS_APPEND,
81 .size = MTDPART_SIZ_FULL,
82 .mask_flags = 0,
83 }
84
85};
86
87static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = {
88 .parts = davinci_ntosd2_nandflash_partition,
89 .nr_parts = ARRAY_SIZE(davinci_ntosd2_nandflash_partition),
90 .ecc_mode = NAND_ECC_HW,
91 .ecc_bits = 1,
92 .bbt_options = NAND_BBT_USE_FLASH,
93};
94
95static struct resource davinci_ntosd2_nandflash_resource[] = {
96 {
97 .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
98 .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
99 .flags = IORESOURCE_MEM,
100 }, {
101 .start = DM644X_ASYNC_EMIF_CONTROL_BASE,
102 .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
103 .flags = IORESOURCE_MEM,
104 },
105};
106
107static struct platform_device davinci_ntosd2_nandflash_device = {
108 .name = "davinci_nand",
109 .id = 0,
110 .dev = {
111 .platform_data = &davinci_ntosd2_nandflash_data,
112 },
113 .num_resources = ARRAY_SIZE(davinci_ntosd2_nandflash_resource),
114 .resource = davinci_ntosd2_nandflash_resource,
115};
116
117static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
118
119static struct platform_device davinci_fb_device = {
120 .name = "davincifb",
121 .id = -1,
122 .dev = {
123 .dma_mask = &davinci_fb_dma_mask,
124 .coherent_dma_mask = DMA_BIT_MASK(32),
125 },
126 .num_resources = 0,
127};
128
129static struct snd_platform_data dm644x_ntosd2_snd_data;
130
131static struct gpio_led ntosd2_leds[] = {
132 { .name = "led1_green", .gpio = GPIO(10), },
133 { .name = "led1_red", .gpio = GPIO(11), },
134 { .name = "led2_green", .gpio = GPIO(12), },
135 { .name = "led2_red", .gpio = GPIO(13), },
136};
137
138static struct gpio_led_platform_data ntosd2_leds_data = {
139 .num_leds = ARRAY_SIZE(ntosd2_leds),
140 .leds = ntosd2_leds,
141};
142
143static struct platform_device ntosd2_leds_dev = {
144 .name = "leds-gpio",
145 .id = -1,
146 .dev = {
147 .platform_data = &ntosd2_leds_data,
148 },
149};
150
151
152static struct platform_device *davinci_ntosd2_devices[] __initdata = {
153 &davinci_fb_device,
154 &ntosd2_leds_dev,
155};
156
157static struct davinci_uart_config uart_config __initdata = {
158 .enabled_uarts = (1 << 0),
159};
160
161static void __init davinci_ntosd2_map_io(void)
162{
163 dm644x_init();
164}
165
166static struct davinci_mmc_config davinci_ntosd2_mmc_config = {
167 .wires = 4,
168};
169
170#define HAS_ATA IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710)
171
172#define HAS_NAND IS_ENABLED(CONFIG_MTD_NAND_DAVINCI)
173
174static __init void davinci_ntosd2_init(void)
175{
176 struct clk *aemif_clk;
177 struct davinci_soc_info *soc_info = &davinci_soc_info;
178
179 aemif_clk = clk_get(NULL, "aemif");
180 clk_prepare_enable(aemif_clk);
181
182 if (HAS_ATA) {
183 if (HAS_NAND)
184 pr_warning("WARNING: both IDE and Flash are "
185 "enabled, but they share AEMIF pins.\n"
186 "\tDisable IDE for NAND/NOR support.\n");
187 davinci_init_ide();
188 } else if (HAS_NAND) {
189 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
190 davinci_cfg_reg(DM644X_ATAEN_DISABLE);
191
192
193 if (HAS_NAND)
194 platform_device_register(
195 &davinci_ntosd2_nandflash_device);
196 }
197
198 platform_add_devices(davinci_ntosd2_devices,
199 ARRAY_SIZE(davinci_ntosd2_devices));
200
201 davinci_serial_init(&uart_config);
202 dm644x_init_asp(&dm644x_ntosd2_snd_data);
203
204 soc_info->emac_pdata->phy_id = NEUROS_OSD2_PHY_ID;
205
206 davinci_setup_usb(1000, 8);
207
208
209
210
211
212
213
214
215 davinci_cfg_reg(DM644X_AEAW0);
216 davinci_cfg_reg(DM644X_AEAW1);
217 davinci_cfg_reg(DM644X_AEAW2);
218 davinci_cfg_reg(DM644X_AEAW3);
219 davinci_cfg_reg(DM644X_AEAW4);
220
221 davinci_setup_mmc(0, &davinci_ntosd2_mmc_config);
222}
223
224MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
225
226 .atag_offset = 0x100,
227 .map_io = davinci_ntosd2_map_io,
228 .init_irq = davinci_irq_init,
229 .init_time = davinci_timer_init,
230 .init_machine = davinci_ntosd2_init,
231 .init_late = davinci_init_late,
232 .dma_zone_size = SZ_128M,
233 .restart = davinci_restart,
234MACHINE_END
235
