1/* Copyright (c) 2009, Code Aurora Forum. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13#ifndef __ASM_ARCH_MSM_IRQS_7X30_H 14#define __ASM_ARCH_MSM_IRQS_7X30_H 15 16/* MSM ACPU Interrupt Numbers */ 17 18#define INT_DEBUG_TIMER_EXP 0 19#define INT_GPT0_TIMER_EXP 1 20#define INT_GPT1_TIMER_EXP 2 21#define INT_WDT0_ACCSCSSBARK 3 22#define INT_WDT1_ACCSCSSBARK 4 23#define INT_AVS_SVIC 5 24#define INT_AVS_SVIC_SW_DONE 6 25#define INT_SC_DBG_RX_FULL 7 26#define INT_SC_DBG_TX_EMPTY 8 27#define INT_ARM11_PM 9 28#define INT_AVS_REQ_DOWN 10 29#define INT_AVS_REQ_UP 11 30#define INT_SC_ACG 12 31/* SCSS_VICFIQSTS0[13:15] are RESERVED */ 32#define INT_L2_SVICCPUIRPTREQ 16 33#define INT_L2_SVICDMANSIRPTREQ 17 34#define INT_L2_SVICDMASIRPTREQ 18 35#define INT_L2_SVICSLVIRPTREQ 19 36#define INT_AD5A_MPROC_APPS_0 20 37#define INT_AD5A_MPROC_APPS_1 21 38#define INT_A9_M2A_0 22 39#define INT_A9_M2A_1 23 40#define INT_A9_M2A_2 24 41#define INT_A9_M2A_3 25 42#define INT_A9_M2A_4 26 43#define INT_A9_M2A_5 27 44#define INT_A9_M2A_6 28 45#define INT_A9_M2A_7 29 46#define INT_A9_M2A_8 30 47#define INT_A9_M2A_9 31 48 49#define INT_AXI_EBI1_SC (32 + 0) 50#define INT_IMEM_ERR (32 + 1) 51#define INT_AXI_EBI0_SC (32 + 2) 52#define INT_PBUS_SC_IRQC (32 + 3) 53#define INT_PERPH_BUS_BPM (32 + 4) 54#define INT_CC_TEMP_SENSE (32 + 5) 55#define INT_UXMC_EBI0 (32 + 6) 56#define INT_UXMC_EBI1 (32 + 7) 57#define INT_EBI2_OP_DONE (32 + 8) 58#define INT_EBI2_WR_ER_DONE (32 + 9) 59#define INT_TCSR_SPSS_CE (32 + 10) 60#define INT_EMDH (32 + 11) 61#define INT_PMDH (32 + 12) 62#define INT_MDC (32 + 13) 63#define INT_MIDI_TO_SUPSS (32 + 14) 64#define INT_LPA_2 (32 + 15) 65#define INT_GPIO_GROUP1_SECURE (32 + 16) 66#define INT_GPIO_GROUP2_SECURE (32 + 17) 67#define INT_GPIO_GROUP1 (32 + 18) 68#define INT_GPIO_GROUP2 (32 + 19) 69#define INT_MPRPH_SOFTRESET (32 + 20) 70#define INT_PWB_I2C (32 + 21) 71#define INT_PWB_I2C_2 (32 + 22) 72#define INT_TSSC_SAMPLE (32 + 23) 73#define INT_TSSC_PENUP (32 + 24) 74#define INT_TCHSCRN_SSBI (32 + 25) 75#define INT_FM_RDS (32 + 26) 76#define INT_KEYSENSE (32 + 27) 77#define INT_USB_OTG_HS (32 + 28) 78#define INT_USB_OTG_HS2 (32 + 29) 79#define INT_USB_OTG_HS3 (32 + 30) 80#define INT_CSI (32 + 31) 81 82#define INT_SPI_OUTPUT (64 + 0) 83#define INT_SPI_INPUT (64 + 1) 84#define INT_SPI_ERROR (64 + 2) 85#define INT_UART1 (64 + 3) 86#define INT_UART1_RX (64 + 4) 87#define INT_UART2 (64 + 5) 88#define INT_UART2_RX (64 + 6) 89#define INT_UART3 (64 + 7) 90#define INT_UART3_RX (64 + 8) 91#define INT_UART1DM_IRQ (64 + 9) 92#define INT_UART1DM_RX (64 + 10) 93#define INT_UART2DM_IRQ (64 + 11) 94#define INT_UART2DM_RX (64 + 12) 95#define INT_TSIF (64 + 13) 96#define INT_ADM_SC1 (64 + 14) 97#define INT_ADM_SC2 (64 + 15) 98#define INT_MDP (64 + 16) 99#define INT_VPE (64 + 17) 100#define INT_GRP_2D (64 + 18) 101#define INT_GRP_3D (64 + 19) 102#define INT_ROTATOR (64 + 20) 103#define INT_MFC720 (64 + 21) 104#define INT_JPEG (64 + 22) 105#define INT_VFE (64 + 23) 106#define INT_TV_ENC (64 + 24) 107#define INT_PMIC_SSBI (64 + 25) 108#define INT_MPM_1 (64 + 26) 109#define INT_TCSR_SPSS_SAMPLE (64 + 27) 110#define INT_TCSR_SPSS_PENUP (64 + 28) 111#define INT_MPM_2 (64 + 29) 112#define INT_SDC1_0 (64 + 30) 113#define INT_SDC1_1 (64 + 31) 114 115#define INT_SDC3_0 (96 + 0) 116#define INT_SDC3_1 (96 + 1) 117#define INT_SDC2_0 (96 + 2) 118#define INT_SDC2_1 (96 + 3) 119#define INT_SDC4_0 (96 + 4) 120#define INT_SDC4_1 (96 + 5) 121#define INT_PWB_QUP_IN (96 + 6) 122#define INT_PWB_QUP_OUT (96 + 7) 123#define INT_PWB_QUP_ERR (96 + 8) 124#define INT_SCSS_WDT0_BITE (96 + 9) 125/* SCSS_VICFIQSTS3[10:31] are RESERVED */ 126 127/* Retrofit universal macro names */ 128#define INT_ADM_AARM INT_ADM_SC2 129#define INT_USB_HS INT_USB_OTG_HS 130#define INT_USB_OTG INT_USB_OTG_HS 131#define INT_TCHSCRN1 INT_TSSC_SAMPLE 132#define INT_TCHSCRN2 INT_TSSC_PENUP 133#define INT_GP_TIMER_EXP INT_GPT0_TIMER_EXP 134#define INT_ADSP_A11 INT_AD5A_MPROC_APPS_0 135#define INT_ADSP_A9_A11 INT_AD5A_MPROC_APPS_1 136#define INT_MDDI_EXT INT_EMDH 137#define INT_MDDI_PRI INT_PMDH 138#define INT_MDDI_CLIENT INT_MDC 139#define INT_NAND_WR_ER_DONE INT_EBI2_WR_ER_DONE 140#define INT_NAND_OP_DONE INT_EBI2_OP_DONE 141 142#define NR_MSM_IRQS 128 143#define NR_GPIO_IRQS 182 144#define PMIC8058_IRQ_BASE (NR_MSM_IRQS + NR_GPIO_IRQS) 145#define NR_PMIC8058_GPIO_IRQS 40 146#define NR_PMIC8058_MPP_IRQS 12 147#define NR_PMIC8058_MISC_IRQS 8 148#define NR_PMIC8058_IRQS (NR_PMIC8058_GPIO_IRQS +\ 149 NR_PMIC8058_MPP_IRQS +\ 150 NR_PMIC8058_MISC_IRQS) 151#define NR_BOARD_IRQS NR_PMIC8058_IRQS 152 153#endif /* __ASM_ARCH_MSM_IRQS_7X30_H */ 154