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12#include <linux/kernel.h>
13#include <linux/slab.h>
14#include <linux/string.h>
15#include <linux/delay.h>
16#include <linux/gpio.h>
17#include <linux/platform_data/gpio-omap.h>
18
19#include "soc.h"
20#include "omap_device.h"
21#include "omap-pm.h"
22
23#include "mux.h"
24#include "mmc.h"
25#include "hsmmc.h"
26#include "control.h"
27
28#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
29
30static u16 control_pbias_offset;
31static u16 control_devconf1_offset;
32
33#define HSMMC_NAME_LEN 9
34
35#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
36
37static int hsmmc_get_context_loss(struct device *dev)
38{
39 return omap_pm_get_dev_context_loss_count(dev);
40}
41
42#else
43#define hsmmc_get_context_loss NULL
44#endif
45
46static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
47 int power_on, int vdd)
48{
49 u32 reg, prog_io;
50 struct omap_mmc_platform_data *mmc = dev->platform_data;
51
52 if (mmc->slots[0].remux)
53 mmc->slots[0].remux(dev, slot, power_on);
54
55
56
57
58
59
60
61
62
63
64
65 if (power_on) {
66 if (cpu_is_omap2430()) {
67 reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
68 if ((1 << vdd) >= MMC_VDD_30_31)
69 reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
70 else
71 reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
72 omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
73 }
74
75 if (mmc->slots[0].internal_clock) {
76 reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
77 reg |= OMAP2_MMCSDIO1ADPCLKISEL;
78 omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
79 }
80
81 reg = omap_ctrl_readl(control_pbias_offset);
82 if (cpu_is_omap3630()) {
83
84 prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
85 prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
86 omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
87 } else {
88 reg |= OMAP2_PBIASSPEEDCTRL0;
89 }
90 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
91 omap_ctrl_writel(reg, control_pbias_offset);
92 } else {
93 reg = omap_ctrl_readl(control_pbias_offset);
94 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
95 omap_ctrl_writel(reg, control_pbias_offset);
96 }
97}
98
99static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
100 int power_on, int vdd)
101{
102 u32 reg;
103
104
105 msleep(100);
106
107 if (power_on) {
108 reg = omap_ctrl_readl(control_pbias_offset);
109 reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
110 if ((1 << vdd) <= MMC_VDD_165_195)
111 reg &= ~OMAP2_PBIASLITEVMODE0;
112 else
113 reg |= OMAP2_PBIASLITEVMODE0;
114 omap_ctrl_writel(reg, control_pbias_offset);
115 } else {
116 reg = omap_ctrl_readl(control_pbias_offset);
117 reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
118 OMAP2_PBIASLITEVMODE0);
119 omap_ctrl_writel(reg, control_pbias_offset);
120 }
121}
122
123static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
124{
125 u32 reg;
126
127 reg = omap_ctrl_readl(control_devconf1_offset);
128 if (mmc->slots[0].internal_clock)
129 reg |= OMAP2_MMCSDIO2ADPCLKISEL;
130 else
131 reg &= ~OMAP2_MMCSDIO2ADPCLKISEL;
132 omap_ctrl_writel(reg, control_devconf1_offset);
133}
134
135static void hsmmc2_before_set_reg(struct device *dev, int slot,
136 int power_on, int vdd)
137{
138 struct omap_mmc_platform_data *mmc = dev->platform_data;
139
140 if (mmc->slots[0].remux)
141 mmc->slots[0].remux(dev, slot, power_on);
142
143 if (power_on)
144 hsmmc2_select_input_clk_src(mmc);
145}
146
147static int am35x_hsmmc2_set_power(struct device *dev, int slot,
148 int power_on, int vdd)
149{
150 struct omap_mmc_platform_data *mmc = dev->platform_data;
151
152 if (power_on)
153 hsmmc2_select_input_clk_src(mmc);
154
155 return 0;
156}
157
158static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
159 int vdd)
160{
161 return 0;
162}
163
164static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
165 int controller_nr)
166{
167 if (gpio_is_valid(mmc_controller->slots[0].switch_pin) &&
168 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
169 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
170 OMAP_PIN_INPUT_PULLUP);
171 if (gpio_is_valid(mmc_controller->slots[0].gpio_wp) &&
172 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
173 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
174 OMAP_PIN_INPUT_PULLUP);
175 if (cpu_is_omap34xx()) {
176 if (controller_nr == 0) {
177 omap_mux_init_signal("sdmmc1_clk",
178 OMAP_PIN_INPUT_PULLUP);
179 omap_mux_init_signal("sdmmc1_cmd",
180 OMAP_PIN_INPUT_PULLUP);
181 omap_mux_init_signal("sdmmc1_dat0",
182 OMAP_PIN_INPUT_PULLUP);
183 if (mmc_controller->slots[0].caps &
184 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
185 omap_mux_init_signal("sdmmc1_dat1",
186 OMAP_PIN_INPUT_PULLUP);
187 omap_mux_init_signal("sdmmc1_dat2",
188 OMAP_PIN_INPUT_PULLUP);
189 omap_mux_init_signal("sdmmc1_dat3",
190 OMAP_PIN_INPUT_PULLUP);
191 }
192 if (mmc_controller->slots[0].caps &
193 MMC_CAP_8_BIT_DATA) {
194 omap_mux_init_signal("sdmmc1_dat4",
195 OMAP_PIN_INPUT_PULLUP);
196 omap_mux_init_signal("sdmmc1_dat5",
197 OMAP_PIN_INPUT_PULLUP);
198 omap_mux_init_signal("sdmmc1_dat6",
199 OMAP_PIN_INPUT_PULLUP);
200 omap_mux_init_signal("sdmmc1_dat7",
201 OMAP_PIN_INPUT_PULLUP);
202 }
203 }
204 if (controller_nr == 1) {
205
206 omap_mux_init_signal("sdmmc2_clk",
207 OMAP_PIN_INPUT_PULLUP);
208 omap_mux_init_signal("sdmmc2_cmd",
209 OMAP_PIN_INPUT_PULLUP);
210 omap_mux_init_signal("sdmmc2_dat0",
211 OMAP_PIN_INPUT_PULLUP);
212
213
214
215
216
217 if (mmc_controller->slots[0].caps &
218 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
219 omap_mux_init_signal("sdmmc2_dat1",
220 OMAP_PIN_INPUT_PULLUP);
221 omap_mux_init_signal("sdmmc2_dat2",
222 OMAP_PIN_INPUT_PULLUP);
223 omap_mux_init_signal("sdmmc2_dat3",
224 OMAP_PIN_INPUT_PULLUP);
225 }
226 if (mmc_controller->slots[0].caps &
227 MMC_CAP_8_BIT_DATA) {
228 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
229 OMAP_PIN_INPUT_PULLUP);
230 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
231 OMAP_PIN_INPUT_PULLUP);
232 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
233 OMAP_PIN_INPUT_PULLUP);
234 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
235 OMAP_PIN_INPUT_PULLUP);
236 }
237 }
238
239
240
241
242 }
243}
244
245static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
246 struct omap_mmc_platform_data *mmc)
247{
248 char *hc_name;
249
250 hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
251 if (!hc_name) {
252 pr_err("Cannot allocate memory for controller slot name\n");
253 kfree(hc_name);
254 return -ENOMEM;
255 }
256
257 if (c->name)
258 strncpy(hc_name, c->name, HSMMC_NAME_LEN);
259 else
260 snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
261 c->mmc, 1);
262 mmc->slots[0].name = hc_name;
263 mmc->nr_slots = 1;
264 mmc->slots[0].caps = c->caps;
265 mmc->slots[0].pm_caps = c->pm_caps;
266 mmc->slots[0].internal_clock = !c->ext_clock;
267 mmc->max_freq = c->max_freq;
268 mmc->reg_offset = 0;
269 mmc->get_context_loss_count = hsmmc_get_context_loss;
270
271 mmc->slots[0].switch_pin = c->gpio_cd;
272 mmc->slots[0].gpio_wp = c->gpio_wp;
273
274 mmc->slots[0].remux = c->remux;
275 mmc->slots[0].init_card = c->init_card;
276
277 if (c->cover_only)
278 mmc->slots[0].cover = 1;
279
280 if (c->nonremovable)
281 mmc->slots[0].nonremovable = 1;
282
283 if (c->power_saving)
284 mmc->slots[0].power_saving = 1;
285
286 if (c->no_off)
287 mmc->slots[0].no_off = 1;
288
289 if (c->no_off_init)
290 mmc->slots[0].no_regulator_off_init = c->no_off_init;
291
292 if (c->vcc_aux_disable_is_sleep)
293 mmc->slots[0].vcc_aux_disable_is_sleep = 1;
294
295
296
297
298
299
300
301
302 if (soc_is_am35xx())
303 mmc->slots[0].ocr_mask = MMC_VDD_165_195 |
304 MMC_VDD_26_27 |
305 MMC_VDD_27_28 |
306 MMC_VDD_29_30 |
307 MMC_VDD_30_31 |
308 MMC_VDD_31_32;
309 else
310 mmc->slots[0].ocr_mask = c->ocr_mask;
311
312 if (!soc_is_am35xx())
313 mmc->slots[0].features |= HSMMC_HAS_PBIAS;
314
315 switch (c->mmc) {
316 case 1:
317 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
318
319 mmc->slots[0].before_set_reg =
320 omap_hsmmc1_before_set_reg;
321 mmc->slots[0].after_set_reg =
322 omap_hsmmc1_after_set_reg;
323 }
324
325 if (soc_is_am35xx())
326 mmc->slots[0].set_power = nop_mmc_set_power;
327
328
329 if (cpu_is_omap3630() &&
330 (c->caps & MMC_CAP_8_BIT_DATA)) {
331 c->caps &= ~MMC_CAP_8_BIT_DATA;
332 c->caps |= MMC_CAP_4_BIT_DATA;
333 mmc->slots[0].caps = c->caps;
334 }
335 break;
336 case 2:
337 if (soc_is_am35xx())
338 mmc->slots[0].set_power = am35x_hsmmc2_set_power;
339
340 if (c->ext_clock)
341 c->transceiver = 1;
342 if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
343 c->caps &= ~MMC_CAP_8_BIT_DATA;
344 c->caps |= MMC_CAP_4_BIT_DATA;
345 }
346 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
347
348 mmc->slots[0].before_set_reg = hsmmc2_before_set_reg;
349 mmc->slots[0].after_set_reg = NULL;
350 }
351 break;
352 case 3:
353 case 4:
354 case 5:
355 mmc->slots[0].before_set_reg = NULL;
356 mmc->slots[0].after_set_reg = NULL;
357 break;
358 default:
359 pr_err("MMC%d configuration not supported!\n", c->mmc);
360 kfree(hc_name);
361 return -ENODEV;
362 }
363 return 0;
364}
365
366static int omap_hsmmc_done;
367
368void omap_hsmmc_late_init(struct omap2_hsmmc_info *c)
369{
370 struct platform_device *pdev;
371 struct omap_mmc_platform_data *mmc_pdata;
372 int res;
373
374 if (omap_hsmmc_done != 1)
375 return;
376
377 omap_hsmmc_done++;
378
379 for (; c->mmc; c++) {
380 if (!c->deferred)
381 continue;
382
383 pdev = c->pdev;
384 if (!pdev)
385 continue;
386
387 mmc_pdata = pdev->dev.platform_data;
388 if (!mmc_pdata)
389 continue;
390
391 mmc_pdata->slots[0].switch_pin = c->gpio_cd;
392 mmc_pdata->slots[0].gpio_wp = c->gpio_wp;
393
394 res = omap_device_register(pdev);
395 if (res)
396 pr_err("Could not late init MMC %s\n",
397 c->name);
398 }
399}
400
401#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
402
403static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
404 int ctrl_nr)
405{
406 struct omap_hwmod *oh;
407 struct omap_hwmod *ohs[1];
408 struct omap_device *od;
409 struct platform_device *pdev;
410 char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
411 struct omap_mmc_platform_data *mmc_data;
412 struct omap_mmc_dev_attr *mmc_dev_attr;
413 char *name;
414 int res;
415
416 mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
417 if (!mmc_data) {
418 pr_err("Cannot allocate memory for mmc device!\n");
419 return;
420 }
421
422 res = omap_hsmmc_pdata_init(hsmmcinfo, mmc_data);
423 if (res < 0)
424 goto free_mmc;
425
426 omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
427
428 name = "omap_hsmmc";
429 res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
430 "mmc%d", ctrl_nr);
431 WARN(res >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
432 "String buffer overflow in MMC%d device setup\n", ctrl_nr);
433
434 oh = omap_hwmod_lookup(oh_name);
435 if (!oh) {
436 pr_err("Could not look up %s\n", oh_name);
437 goto free_name;
438 }
439 ohs[0] = oh;
440 if (oh->dev_attr != NULL) {
441 mmc_dev_attr = oh->dev_attr;
442 mmc_data->controller_flags = mmc_dev_attr->flags;
443
444
445
446
447 if (hsmmcinfo->transceiver)
448 mmc_data->controller_flags &=
449 ~OMAP_HSMMC_BROKEN_MULTIBLOCK_READ;
450 }
451
452 pdev = platform_device_alloc(name, ctrl_nr - 1);
453 if (!pdev) {
454 pr_err("Could not allocate pdev for %s\n", name);
455 goto free_name;
456 }
457 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
458
459 od = omap_device_alloc(pdev, ohs, 1);
460 if (IS_ERR(od)) {
461 pr_err("Could not allocate od for %s\n", name);
462 goto put_pdev;
463 }
464
465 res = platform_device_add_data(pdev, mmc_data,
466 sizeof(struct omap_mmc_platform_data));
467 if (res) {
468 pr_err("Could not add pdata for %s\n", name);
469 goto put_pdev;
470 }
471
472 hsmmcinfo->pdev = pdev;
473
474 if (hsmmcinfo->deferred)
475 goto free_mmc;
476
477 res = omap_device_register(pdev);
478 if (res) {
479 pr_err("Could not register od for %s\n", name);
480 goto free_od;
481 }
482
483 goto free_mmc;
484
485free_od:
486 omap_device_delete(od);
487
488put_pdev:
489 platform_device_put(pdev);
490
491free_name:
492 kfree(mmc_data->slots[0].name);
493
494free_mmc:
495 kfree(mmc_data);
496}
497
498void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers)
499{
500 if (omap_hsmmc_done)
501 return;
502
503 omap_hsmmc_done = 1;
504
505 if (cpu_is_omap2430()) {
506 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
507 control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
508 } else {
509 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
510 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
511 }
512
513 for (; controllers->mmc; controllers++)
514 omap_hsmmc_init_one(controllers, controllers->mmc);
515
516}
517
518#endif
519
