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13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18
19#include <asm/exception.h>
20#include <asm/mach/irq.h>
21#include <linux/irqdomain.h>
22#include <linux/of.h>
23#include <linux/of_address.h>
24#include <linux/of_irq.h>
25
26#include "soc.h"
27#include "iomap.h"
28#include "common.h"
29
30
31
32#define INTC_REVISION 0x0000
33#define INTC_SYSCONFIG 0x0010
34#define INTC_SYSSTATUS 0x0014
35#define INTC_SIR 0x0040
36#define INTC_CONTROL 0x0048
37#define INTC_PROTECTION 0x004C
38#define INTC_IDLE 0x0050
39#define INTC_THRESHOLD 0x0068
40#define INTC_MIR0 0x0084
41#define INTC_MIR_CLEAR0 0x0088
42#define INTC_MIR_SET0 0x008c
43#define INTC_PENDING_IRQ0 0x0098
44
45#define IRQ_BITS_PER_REG 32
46
47#define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
48#define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
49#define INTCPS_SIR_IRQ_OFFSET 0x0040
50#define ACTIVEIRQ_MASK 0x7f
51#define INTCPS_NR_MIR_REGS 3
52#define INTCPS_NR_IRQS 96
53
54
55
56
57
58
59
60static struct omap_irq_bank {
61 void __iomem *base_reg;
62 unsigned int nr_irqs;
63} __attribute__ ((aligned(4))) irq_banks[] = {
64 {
65
66 .nr_irqs = 96,
67 },
68};
69
70static struct irq_domain *domain;
71
72
73struct omap3_intc_regs {
74 u32 sysconfig;
75 u32 protection;
76 u32 idle;
77 u32 threshold;
78 u32 ilr[INTCPS_NR_IRQS];
79 u32 mir[INTCPS_NR_MIR_REGS];
80};
81
82
83
84static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
85{
86 __raw_writel(val, bank->base_reg + reg);
87}
88
89static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
90{
91 return __raw_readl(bank->base_reg + reg);
92}
93
94
95static void omap_ack_irq(struct irq_data *d)
96{
97 intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
98}
99
100static void omap_mask_ack_irq(struct irq_data *d)
101{
102 irq_gc_mask_disable_reg(d);
103 omap_ack_irq(d);
104}
105
106static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
107{
108 unsigned long tmp;
109
110 tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
111 pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
112 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
113
114 tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
115 tmp |= 1 << 1;
116 intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
117
118 while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
119 ;
120
121
122 intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
123}
124
125int omap_irq_pending(void)
126{
127 int i;
128
129 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
130 struct omap_irq_bank *bank = irq_banks + i;
131 int irq;
132
133 for (irq = 0; irq < bank->nr_irqs; irq += 32)
134 if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
135 ((irq >> 5) << 5)))
136 return 1;
137 }
138 return 0;
139}
140
141static __init void
142omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
143{
144 struct irq_chip_generic *gc;
145 struct irq_chip_type *ct;
146
147 gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
148 handle_level_irq);
149 ct = gc->chip_types;
150 ct->chip.irq_ack = omap_mask_ack_irq;
151 ct->chip.irq_mask = irq_gc_mask_disable_reg;
152 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
153 ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
154
155 ct->regs.enable = INTC_MIR_CLEAR0;
156 ct->regs.disable = INTC_MIR_SET0;
157 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
158 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
159}
160
161static void __init omap_init_irq(u32 base, int nr_irqs,
162 struct device_node *node)
163{
164 void __iomem *omap_irq_base;
165 unsigned long nr_of_irqs = 0;
166 unsigned int nr_banks = 0;
167 int i, j, irq_base;
168
169 omap_irq_base = ioremap(base, SZ_4K);
170 if (WARN_ON(!omap_irq_base))
171 return;
172
173 irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
174 if (irq_base < 0) {
175 pr_warn("Couldn't allocate IRQ numbers\n");
176 irq_base = 0;
177 }
178
179 domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
180 &irq_domain_simple_ops, NULL);
181
182 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
183 struct omap_irq_bank *bank = irq_banks + i;
184
185 bank->nr_irqs = nr_irqs;
186
187
188 bank->base_reg = ioremap(base, SZ_4K);
189 if (!bank->base_reg) {
190 pr_err("Could not ioremap irq bank%i\n", i);
191 continue;
192 }
193
194 omap_irq_bank_init_one(bank);
195
196 for (j = 0; j < bank->nr_irqs; j += 32)
197 omap_alloc_gc(bank->base_reg + j, j + irq_base, 32);
198
199 nr_of_irqs += bank->nr_irqs;
200 nr_banks++;
201 }
202
203 pr_info("Total of %ld interrupts on %d active controller%s\n",
204 nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
205}
206
207void __init omap2_init_irq(void)
208{
209 omap_init_irq(OMAP24XX_IC_BASE, 96, NULL);
210}
211
212void __init omap3_init_irq(void)
213{
214 omap_init_irq(OMAP34XX_IC_BASE, 96, NULL);
215}
216
217void __init ti81xx_init_irq(void)
218{
219 omap_init_irq(OMAP34XX_IC_BASE, 128, NULL);
220}
221
222static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
223{
224 u32 irqnr;
225
226 do {
227 irqnr = readl_relaxed(base_addr + 0x98);
228 if (irqnr)
229 goto out;
230
231 irqnr = readl_relaxed(base_addr + 0xb8);
232 if (irqnr)
233 goto out;
234
235 irqnr = readl_relaxed(base_addr + 0xd8);
236#ifdef CONFIG_SOC_TI81XX
237 if (irqnr)
238 goto out;
239 irqnr = readl_relaxed(base_addr + 0xf8);
240#endif
241
242out:
243 if (!irqnr)
244 break;
245
246 irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
247 irqnr &= ACTIVEIRQ_MASK;
248
249 if (irqnr) {
250 irqnr = irq_find_mapping(domain, irqnr);
251 handle_IRQ(irqnr, regs);
252 }
253 } while (irqnr);
254}
255
256asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
257{
258 void __iomem *base_addr = OMAP2_IRQ_BASE;
259 omap_intc_handle_irq(base_addr, regs);
260}
261
262int __init intc_of_init(struct device_node *node,
263 struct device_node *parent)
264{
265 struct resource res;
266 u32 nr_irq = 96;
267
268 if (WARN_ON(!node))
269 return -ENODEV;
270
271 if (of_address_to_resource(node, 0, &res)) {
272 WARN(1, "unable to get intc registers\n");
273 return -EINVAL;
274 }
275
276 if (of_property_read_u32(node, "ti,intc-size", &nr_irq))
277 pr_warn("unable to get intc-size, default to %d\n", nr_irq);
278
279 omap_init_irq(res.start, nr_irq, of_node_get(node));
280
281 return 0;
282}
283
284static struct of_device_id irq_match[] __initdata = {
285 { .compatible = "ti,omap2-intc", .data = intc_of_init, },
286 { }
287};
288
289void __init omap_intc_of_init(void)
290{
291 of_irq_init(irq_match);
292}
293
294#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
295static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
296
297void omap_intc_save_context(void)
298{
299 int ind = 0, i = 0;
300 for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
301 struct omap_irq_bank *bank = irq_banks + ind;
302 intc_context[ind].sysconfig =
303 intc_bank_read_reg(bank, INTC_SYSCONFIG);
304 intc_context[ind].protection =
305 intc_bank_read_reg(bank, INTC_PROTECTION);
306 intc_context[ind].idle =
307 intc_bank_read_reg(bank, INTC_IDLE);
308 intc_context[ind].threshold =
309 intc_bank_read_reg(bank, INTC_THRESHOLD);
310 for (i = 0; i < INTCPS_NR_IRQS; i++)
311 intc_context[ind].ilr[i] =
312 intc_bank_read_reg(bank, (0x100 + 0x4*i));
313 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
314 intc_context[ind].mir[i] =
315 intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
316 (0x20 * i));
317 }
318}
319
320void omap_intc_restore_context(void)
321{
322 int ind = 0, i = 0;
323
324 for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
325 struct omap_irq_bank *bank = irq_banks + ind;
326 intc_bank_write_reg(intc_context[ind].sysconfig,
327 bank, INTC_SYSCONFIG);
328 intc_bank_write_reg(intc_context[ind].sysconfig,
329 bank, INTC_SYSCONFIG);
330 intc_bank_write_reg(intc_context[ind].protection,
331 bank, INTC_PROTECTION);
332 intc_bank_write_reg(intc_context[ind].idle,
333 bank, INTC_IDLE);
334 intc_bank_write_reg(intc_context[ind].threshold,
335 bank, INTC_THRESHOLD);
336 for (i = 0; i < INTCPS_NR_IRQS; i++)
337 intc_bank_write_reg(intc_context[ind].ilr[i],
338 bank, (0x100 + 0x4*i));
339 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
340 intc_bank_write_reg(intc_context[ind].mir[i],
341 &irq_banks[0], INTC_MIR0 + (0x20 * i));
342 }
343
344}
345
346void omap3_intc_suspend(void)
347{
348
349 omap_ack_irq(NULL);
350}
351
352void omap3_intc_prepare_idle(void)
353{
354
355
356
357
358 intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
359}
360
361void omap3_intc_resume_idle(void)
362{
363
364 intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
365}
366
367asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
368{
369 void __iomem *base_addr = OMAP3_IRQ_BASE;
370 omap_intc_handle_irq(base_addr, regs);
371}
372#endif
373
