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11#ifndef __ARCH_ARM_MACH_OMAP2_SDRAM_HYNIX_H8MBX00U0MER0EM
12#define __ARCH_ARM_MACH_OMAP2_SDRAM_HYNIX_H8MBX00U0MER0EM
13
14#include "sdrc.h"
15
16
17static struct omap_sdrc_params h8mbx00u0mer0em_sdrc_params[] = {
18 [0] = {
19 .rate = 200000000,
20 .actim_ctrla = 0xa2e1b4c6,
21 .actim_ctrlb = 0x0002131c,
22 .rfr_ctrl = 0x0005e601,
23 .mr = 0x00000032,
24 },
25 [1] = {
26 .rate = 166000000,
27 .actim_ctrla = 0x629db4c6,
28 .actim_ctrlb = 0x00012214,
29 .rfr_ctrl = 0x0004dc01,
30 .mr = 0x00000032,
31 },
32 [2] = {
33 .rate = 100000000,
34 .actim_ctrla = 0x51912284,
35 .actim_ctrlb = 0x0002120e,
36 .rfr_ctrl = 0x0002d101,
37 .mr = 0x00000022,
38 },
39 [3] = {
40 .rate = 83000000,
41 .actim_ctrla = 0x31512283,
42 .actim_ctrlb = 0x0001220a,
43 .rfr_ctrl = 0x00025501,
44 .mr = 0x00000022,
45 },
46 [4] = {
47 .rate = 0
48 },
49};
50
51#endif
52