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24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/list.h>
28#include <linux/errno.h>
29#include <linux/err.h>
30#include <linux/device.h>
31#include <linux/syscore_ops.h>
32#include <linux/interrupt.h>
33#include <linux/ioport.h>
34#include <linux/mutex.h>
35#include <linux/gpio.h>
36#include <linux/clk.h>
37#include <linux/io.h>
38
39#include <mach/hardware.h>
40#include <linux/atomic.h>
41#include <asm/irq.h>
42
43#include <mach/regs-clock.h>
44
45#include <plat/clock.h>
46#include <plat/cpu.h>
47#include <plat/pm.h>
48
49#include <plat/gpio-core.h>
50#include <plat/gpio-cfg.h>
51#include <plat/gpio-cfg-helpers.h>
52
53#include "common.h"
54
55
56
57static unsigned long s3c2442_camif_upll_round(struct clk *clk,
58 unsigned long rate)
59{
60 unsigned long parent_rate = clk_get_rate(clk->parent);
61 int div;
62
63 if (rate > parent_rate)
64 return parent_rate;
65
66 div = parent_rate / rate;
67
68 if (div == 3)
69 return parent_rate / 3;
70
71
72
73 div /= 2;
74
75 if (div < 1)
76 div = 1;
77 else if (div > 16)
78 div = 16;
79
80 return parent_rate / (div * 2);
81}
82
83static int s3c2442_camif_upll_setrate(struct clk *clk, unsigned long rate)
84{
85 unsigned long parent_rate = clk_get_rate(clk->parent);
86 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
87
88 rate = s3c2442_camif_upll_round(clk, rate);
89
90 camdivn &= ~S3C2442_CAMDIVN_CAMCLK_DIV3;
91
92 if (rate == parent_rate) {
93 camdivn &= ~S3C2440_CAMDIVN_CAMCLK_SEL;
94 } else if ((parent_rate / rate) == 3) {
95 camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
96 camdivn |= S3C2442_CAMDIVN_CAMCLK_DIV3;
97 } else {
98 camdivn &= ~S3C2440_CAMDIVN_CAMCLK_MASK;
99 camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
100 camdivn |= (((parent_rate / rate) / 2) - 1);
101 }
102
103 __raw_writel(camdivn, S3C2440_CAMDIVN);
104
105 return 0;
106}
107
108
109
110static struct clk s3c2442_clk_cam = {
111 .name = "camif",
112 .id = -1,
113 .enable = s3c2410_clkcon_enable,
114 .ctrlbit = S3C2440_CLKCON_CAMERA,
115};
116
117static struct clk s3c2442_clk_cam_upll = {
118 .name = "camif-upll",
119 .id = -1,
120 .ops = &(struct clk_ops) {
121 .set_rate = s3c2442_camif_upll_setrate,
122 .round_rate = s3c2442_camif_upll_round,
123 },
124};
125
126static int s3c2442_clk_add(struct device *dev, struct subsys_interface *sif)
127{
128 struct clk *clock_upll;
129 struct clk *clock_h;
130 struct clk *clock_p;
131
132 clock_p = clk_get(NULL, "pclk");
133 clock_h = clk_get(NULL, "hclk");
134 clock_upll = clk_get(NULL, "upll");
135
136 if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) {
137 printk(KERN_ERR "S3C2442: Failed to get parent clocks\n");
138 return -EINVAL;
139 }
140
141 s3c2442_clk_cam.parent = clock_h;
142 s3c2442_clk_cam_upll.parent = clock_upll;
143
144 s3c24xx_register_clock(&s3c2442_clk_cam);
145 s3c24xx_register_clock(&s3c2442_clk_cam_upll);
146
147 clk_disable(&s3c2442_clk_cam);
148
149 return 0;
150}
151
152static struct subsys_interface s3c2442_clk_interface = {
153 .name = "s3c2442_clk",
154 .subsys = &s3c2442_subsys,
155 .add_dev = s3c2442_clk_add,
156};
157
158static __init int s3c2442_clk_init(void)
159{
160 return subsys_interface_register(&s3c2442_clk_interface);
161}
162
163arch_initcall(s3c2442_clk_init);
164
165
166static struct device s3c2442_dev = {
167 .bus = &s3c2442_subsys,
168};
169
170int __init s3c2442_init(void)
171{
172 printk("S3C2442: Initialising architecture\n");
173
174#ifdef CONFIG_PM
175 register_syscore_ops(&s3c2410_pm_syscore_ops);
176 register_syscore_ops(&s3c24xx_irq_syscore_ops);
177#endif
178 register_syscore_ops(&s3c244x_pm_syscore_ops);
179
180 return device_register(&s3c2442_dev);
181}
182
183void __init s3c2442_map_io(void)
184{
185 s3c244x_map_io();
186
187 s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1down;
188 s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1down;
189}
190
