LXR linux/arch/arm/mach-sa1100/time.c

   1/*
   2 * linux/arch/arm/mach-sa1100/time.c
   3 *
   4 * Copyright (C) 1998 Deborah Wallach.
   5 * Twiddles  (C) 1999 Hugo Fiennes <hugo@empeg.com>
   6 *
   7 * 2000/03/29 (C) Nicolas Pitre <nico@fluxnic.net>
   8 *      Rewritten: big cleanup, much simpler, better HZ accuracy.
   9 *
  10 */
  11#include <linux/init.h>
  12#include <linux/errno.h>
  13#include <linux/interrupt.h>
  14#include <linux/irq.h>
  15#include <linux/timex.h>
  16#include <linux/clockchips.h>
  17#include <linux/sched_clock.h>
  18
  19#include <asm/mach/time.h>
  20#include <mach/hardware.h>
  21#include <mach/irqs.h>
  22
  23static u32 notrace sa1100_read_sched_clock(void)
  24{
  25        return readl_relaxed(OSCR);
  26}
  27
  28#define MIN_OSCR_DELTA 2
  29
  30static irqreturn_t sa1100_ost0_interrupt(int irq, void *dev_id)
  31{
  32        struct clock_event_device *c = dev_id;
  33
  34        /* Disarm the compare/match, signal the event. */
  35        writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
  36        writel_relaxed(OSSR_M0, OSSR);
  37        c->event_handler(c);
  38
  39        return IRQ_HANDLED;
  40}
  41
  42static int
  43sa1100_osmr0_set_next_event(unsigned long delta, struct clock_event_device *c)
  44{
  45        unsigned long next, oscr;
  46
  47        writel_relaxed(readl_relaxed(OIER) | OIER_E0, OIER);
  48        next = readl_relaxed(OSCR) + delta;
  49        writel_relaxed(next, OSMR0);
  50        oscr = readl_relaxed(OSCR);
  51
  52        return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
  53}
  54
  55static void
  56sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c)
  57{
  58        switch (mode) {
  59        case CLOCK_EVT_MODE_ONESHOT:
  60        case CLOCK_EVT_MODE_UNUSED:
  61        case CLOCK_EVT_MODE_SHUTDOWN:
  62                writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
  63                writel_relaxed(OSSR_M0, OSSR);
  64                break;
  65
  66        case CLOCK_EVT_MODE_RESUME:
  67        case CLOCK_EVT_MODE_PERIODIC:
  68                break;
  69        }
  70}
  71
  72#ifdef CONFIG_PM
  73unsigned long osmr[4], oier;
  74
  75static void sa1100_timer_suspend(struct clock_event_device *cedev)
  76{
  77        osmr[0] = readl_relaxed(OSMR0);
  78        osmr[1] = readl_relaxed(OSMR1);
  79        osmr[2] = readl_relaxed(OSMR2);
  80        osmr[3] = readl_relaxed(OSMR3);
  81        oier = readl_relaxed(OIER);
  82}
  83
  84static void sa1100_timer_resume(struct clock_event_device *cedev)
  85{
  86        writel_relaxed(0x0f, OSSR);
  87        writel_relaxed(osmr[0], OSMR0);
  88        writel_relaxed(osmr[1], OSMR1);
  89        writel_relaxed(osmr[2], OSMR2);
  90        writel_relaxed(osmr[3], OSMR3);
  91        writel_relaxed(oier, OIER);
  92
  93        /*
  94         * OSMR0 is the system timer: make sure OSCR is sufficiently behind
  95         */
  96        writel_relaxed(OSMR0 - LATCH, OSCR);
  97}
  98#else
  99#define sa1100_timer_suspend NULL
 100#define sa1100_timer_resume NULL
 101#endif
 102
 103static struct clock_event_device ckevt_sa1100_osmr0 = {
 104        .name           = "osmr0",
 105        .features       = CLOCK_EVT_FEAT_ONESHOT,
 106        .rating         = 200,
 107        .set_next_event = sa1100_osmr0_set_next_event,
 108        .set_mode       = sa1100_osmr0_set_mode,
 109        .suspend        = sa1100_timer_suspend,
 110        .resume         = sa1100_timer_resume,
 111};
 112
 113static struct irqaction sa1100_timer_irq = {
 114        .name           = "ost0",
 115        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 116        .handler        = sa1100_ost0_interrupt,
 117        .dev_id         = &ckevt_sa1100_osmr0,
 118};
 119
 120void __init sa1100_timer_init(void)
 121{
 122        writel_relaxed(0, OIER);
 123        writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
 124
 125        setup_sched_clock(sa1100_read_sched_clock, 32, 3686400);
 126
 127        ckevt_sa1100_osmr0.cpumask = cpumask_of(0);
 128
 129        setup_irq(IRQ_OST0, &sa1100_timer_irq);
 130
 131        clocksource_mmio_init(OSCR, "oscr", CLOCK_TICK_RATE, 200, 32,
 132                clocksource_mmio_readl_up);
 133        clockevents_config_and_register(&ckevt_sa1100_osmr0, 3686400,
 134                                        MIN_OSCR_DELTA * 2, 0x7fffffff);
 135}
 136