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10#include <linux/module.h>
11#include <linux/kernel.h>
12#include <linux/errno.h>
13#include <linux/init.h>
14#include <linux/mman.h>
15#include <linux/nodemask.h>
16#include <linux/memblock.h>
17#include <linux/fs.h>
18#include <linux/vmalloc.h>
19#include <linux/sizes.h>
20
21#include <asm/cp15.h>
22#include <asm/cputype.h>
23#include <asm/sections.h>
24#include <asm/cachetype.h>
25#include <asm/setup.h>
26#include <asm/smp_plat.h>
27#include <asm/tlb.h>
28#include <asm/highmem.h>
29#include <asm/system_info.h>
30#include <asm/traps.h>
31
32#include <asm/mach/arch.h>
33#include <asm/mach/map.h>
34#include <asm/mach/pci.h>
35
36#include "mm.h"
37#include "tcm.h"
38
39
40
41
42
43struct page *empty_zero_page;
44EXPORT_SYMBOL(empty_zero_page);
45
46
47
48
49pmd_t *top_pmd;
50
51#define CPOLICY_UNCACHED 0
52#define CPOLICY_BUFFERED 1
53#define CPOLICY_WRITETHROUGH 2
54#define CPOLICY_WRITEBACK 3
55#define CPOLICY_WRITEALLOC 4
56
57static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
58static unsigned int ecc_mask __initdata = 0;
59pgprot_t pgprot_user;
60pgprot_t pgprot_kernel;
61pgprot_t pgprot_hyp_device;
62pgprot_t pgprot_s2;
63pgprot_t pgprot_s2_device;
64
65EXPORT_SYMBOL(pgprot_user);
66EXPORT_SYMBOL(pgprot_kernel);
67
68struct cachepolicy {
69 const char policy[16];
70 unsigned int cr_mask;
71 pmdval_t pmd;
72 pteval_t pte;
73 pteval_t pte_s2;
74};
75
76#ifdef CONFIG_ARM_LPAE
77#define s2_policy(policy) policy
78#else
79#define s2_policy(policy) 0
80#endif
81
82static struct cachepolicy cache_policies[] __initdata = {
83 {
84 .policy = "uncached",
85 .cr_mask = CR_W|CR_C,
86 .pmd = PMD_SECT_UNCACHED,
87 .pte = L_PTE_MT_UNCACHED,
88 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
89 }, {
90 .policy = "buffered",
91 .cr_mask = CR_C,
92 .pmd = PMD_SECT_BUFFERED,
93 .pte = L_PTE_MT_BUFFERABLE,
94 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
95 }, {
96 .policy = "writethrough",
97 .cr_mask = 0,
98 .pmd = PMD_SECT_WT,
99 .pte = L_PTE_MT_WRITETHROUGH,
100 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
101 }, {
102 .policy = "writeback",
103 .cr_mask = 0,
104 .pmd = PMD_SECT_WB,
105 .pte = L_PTE_MT_WRITEBACK,
106 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
107 }, {
108 .policy = "writealloc",
109 .cr_mask = 0,
110 .pmd = PMD_SECT_WBWA,
111 .pte = L_PTE_MT_WRITEALLOC,
112 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
113 }
114};
115
116#ifdef CONFIG_CPU_CP15
117
118
119
120
121
122
123static int __init early_cachepolicy(char *p)
124{
125 int i;
126
127 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
128 int len = strlen(cache_policies[i].policy);
129
130 if (memcmp(p, cache_policies[i].policy, len) == 0) {
131 cachepolicy = i;
132 cr_alignment &= ~cache_policies[i].cr_mask;
133 cr_no_alignment &= ~cache_policies[i].cr_mask;
134 break;
135 }
136 }
137 if (i == ARRAY_SIZE(cache_policies))
138 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
139
140
141
142
143
144
145
146 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
147 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
148 cachepolicy = CPOLICY_WRITEBACK;
149 }
150 flush_cache_all();
151 set_cr(cr_alignment);
152 return 0;
153}
154early_param("cachepolicy", early_cachepolicy);
155
156static int __init early_nocache(char *__unused)
157{
158 char *p = "buffered";
159 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
160 early_cachepolicy(p);
161 return 0;
162}
163early_param("nocache", early_nocache);
164
165static int __init early_nowrite(char *__unused)
166{
167 char *p = "uncached";
168 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
169 early_cachepolicy(p);
170 return 0;
171}
172early_param("nowb", early_nowrite);
173
174#ifndef CONFIG_ARM_LPAE
175static int __init early_ecc(char *p)
176{
177 if (memcmp(p, "on", 2) == 0)
178 ecc_mask = PMD_PROTECTION;
179 else if (memcmp(p, "off", 3) == 0)
180 ecc_mask = 0;
181 return 0;
182}
183early_param("ecc", early_ecc);
184#endif
185
186static int __init noalign_setup(char *__unused)
187{
188 cr_alignment &= ~CR_A;
189 cr_no_alignment &= ~CR_A;
190 set_cr(cr_alignment);
191 return 1;
192}
193__setup("noalign", noalign_setup);
194
195#ifndef CONFIG_SMP
196void adjust_cr(unsigned long mask, unsigned long set)
197{
198 unsigned long flags;
199
200 mask &= ~CR_A;
201
202 set &= mask;
203
204 local_irq_save(flags);
205
206 cr_no_alignment = (cr_no_alignment & ~mask) | set;
207 cr_alignment = (cr_alignment & ~mask) | set;
208
209 set_cr((get_cr() & ~mask) | set);
210
211 local_irq_restore(flags);
212}
213#endif
214
215#else
216
217static int __init early_cachepolicy(char *p)
218{
219 pr_warning("cachepolicy kernel parameter not supported without cp15\n");
220}
221early_param("cachepolicy", early_cachepolicy);
222
223static int __init noalign_setup(char *__unused)
224{
225 pr_warning("noalign kernel parameter not supported without cp15\n");
226}
227__setup("noalign", noalign_setup);
228
229#endif
230
231#define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
232#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
233
234static struct mem_type mem_types[] = {
235 [MT_DEVICE] = {
236 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
237 L_PTE_SHARED,
238 .prot_l1 = PMD_TYPE_TABLE,
239 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
240 .domain = DOMAIN_IO,
241 },
242 [MT_DEVICE_NONSHARED] = {
243 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
244 .prot_l1 = PMD_TYPE_TABLE,
245 .prot_sect = PROT_SECT_DEVICE,
246 .domain = DOMAIN_IO,
247 },
248 [MT_DEVICE_CACHED] = {
249 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
250 .prot_l1 = PMD_TYPE_TABLE,
251 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
252 .domain = DOMAIN_IO,
253 },
254 [MT_DEVICE_WC] = {
255 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
256 .prot_l1 = PMD_TYPE_TABLE,
257 .prot_sect = PROT_SECT_DEVICE,
258 .domain = DOMAIN_IO,
259 },
260 [MT_UNCACHED] = {
261 .prot_pte = PROT_PTE_DEVICE,
262 .prot_l1 = PMD_TYPE_TABLE,
263 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
264 .domain = DOMAIN_IO,
265 },
266 [MT_CACHECLEAN] = {
267 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
268 .domain = DOMAIN_KERNEL,
269 },
270#ifndef CONFIG_ARM_LPAE
271 [MT_MINICLEAN] = {
272 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
273 .domain = DOMAIN_KERNEL,
274 },
275#endif
276 [MT_LOW_VECTORS] = {
277 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
278 L_PTE_RDONLY,
279 .prot_l1 = PMD_TYPE_TABLE,
280 .domain = DOMAIN_USER,
281 },
282 [MT_HIGH_VECTORS] = {
283 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
284 L_PTE_USER | L_PTE_RDONLY,
285 .prot_l1 = PMD_TYPE_TABLE,
286 .domain = DOMAIN_USER,
287 },
288 [MT_MEMORY] = {
289 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
290 .prot_l1 = PMD_TYPE_TABLE,
291 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
292 .domain = DOMAIN_KERNEL,
293 },
294 [MT_ROM] = {
295 .prot_sect = PMD_TYPE_SECT,
296 .domain = DOMAIN_KERNEL,
297 },
298 [MT_MEMORY_NONCACHED] = {
299 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
300 L_PTE_MT_BUFFERABLE,
301 .prot_l1 = PMD_TYPE_TABLE,
302 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
303 .domain = DOMAIN_KERNEL,
304 },
305 [MT_MEMORY_DTCM] = {
306 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
307 L_PTE_XN,
308 .prot_l1 = PMD_TYPE_TABLE,
309 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
310 .domain = DOMAIN_KERNEL,
311 },
312 [MT_MEMORY_ITCM] = {
313 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
314 .prot_l1 = PMD_TYPE_TABLE,
315 .domain = DOMAIN_KERNEL,
316 },
317 [MT_MEMORY_SO] = {
318 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
319 L_PTE_MT_UNCACHED | L_PTE_XN,
320 .prot_l1 = PMD_TYPE_TABLE,
321 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
322 PMD_SECT_UNCACHED | PMD_SECT_XN,
323 .domain = DOMAIN_KERNEL,
324 },
325 [MT_MEMORY_DMA_READY] = {
326 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
327 .prot_l1 = PMD_TYPE_TABLE,
328 .domain = DOMAIN_KERNEL,
329 },
330};
331
332const struct mem_type *get_mem_type(unsigned int type)
333{
334 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
335}
336EXPORT_SYMBOL(get_mem_type);
337
338
339
340
341static void __init build_mem_type_table(void)
342{
343 struct cachepolicy *cp;
344 unsigned int cr = get_cr();
345 pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
346 pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
347 int cpu_arch = cpu_architecture();
348 int i;
349
350 if (cpu_arch < CPU_ARCH_ARMv6) {
351#if defined(CONFIG_CPU_DCACHE_DISABLE)
352 if (cachepolicy > CPOLICY_BUFFERED)
353 cachepolicy = CPOLICY_BUFFERED;
354#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
355 if (cachepolicy > CPOLICY_WRITETHROUGH)
356 cachepolicy = CPOLICY_WRITETHROUGH;
357#endif
358 }
359 if (cpu_arch < CPU_ARCH_ARMv5) {
360 if (cachepolicy >= CPOLICY_WRITEALLOC)
361 cachepolicy = CPOLICY_WRITEBACK;
362 ecc_mask = 0;
363 }
364 if (is_smp())
365 cachepolicy = CPOLICY_WRITEALLOC;
366
367
368
369
370
371
372 if (cpu_arch < CPU_ARCH_ARMv5)
373 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
374 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
375 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
376 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
377 mem_types[i].prot_sect &= ~PMD_SECT_S;
378
379
380
381
382
383
384 if (cpu_is_xscale() || cpu_is_xsc3()) {
385 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
386 mem_types[i].prot_sect &= ~PMD_BIT4;
387 mem_types[i].prot_l1 &= ~PMD_BIT4;
388 }
389 } else if (cpu_arch < CPU_ARCH_ARMv6) {
390 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
391 if (mem_types[i].prot_l1)
392 mem_types[i].prot_l1 |= PMD_BIT4;
393 if (mem_types[i].prot_sect)
394 mem_types[i].prot_sect |= PMD_BIT4;
395 }
396 }
397
398
399
400
401 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
402 if (!cpu_is_xsc3()) {
403
404
405
406
407 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
408 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
409 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
410 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
411 }
412 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
413
414
415
416
417
418
419
420 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
421 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
422 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
423 } else if (cpu_is_xsc3()) {
424
425
426
427
428
429
430
431 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
432 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
433 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
434 } else {
435
436
437
438
439
440
441
442 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
443 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
444 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
445 }
446 } else {
447
448
449
450 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
451 }
452
453
454
455
456 cp = &cache_policies[cachepolicy];
457 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
458 s2_pgprot = cp->pte_s2;
459 hyp_device_pgprot = s2_device_pgprot = mem_types[MT_DEVICE].prot_pte;
460
461
462
463
464 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
465#ifndef CONFIG_ARM_LPAE
466
467
468
469
470 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
471 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
472 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
473#endif
474
475 if (is_smp()) {
476
477
478
479
480 user_pgprot |= L_PTE_SHARED;
481 kern_pgprot |= L_PTE_SHARED;
482 vecs_pgprot |= L_PTE_SHARED;
483 s2_pgprot |= L_PTE_SHARED;
484 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
485 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
486 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
487 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
488 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
489 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
490 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
491 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
492 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
493 }
494 }
495
496
497
498
499
500 if (cpu_arch >= CPU_ARCH_ARMv6) {
501 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
502
503 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
504 PMD_SECT_BUFFERED;
505 } else {
506
507 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
508 PMD_SECT_TEX(1);
509 }
510 } else {
511 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
512 }
513
514#ifdef CONFIG_ARM_LPAE
515
516
517
518 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
519 mem_types[i].prot_pte |= PTE_EXT_AF;
520 if (mem_types[i].prot_sect)
521 mem_types[i].prot_sect |= PMD_SECT_AF;
522 }
523 kern_pgprot |= PTE_EXT_AF;
524 vecs_pgprot |= PTE_EXT_AF;
525#endif
526
527 for (i = 0; i < 16; i++) {
528 pteval_t v = pgprot_val(protection_map[i]);
529 protection_map[i] = __pgprot(v | user_pgprot);
530 }
531
532 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
533 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
534
535 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
536 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
537 L_PTE_DIRTY | kern_pgprot);
538 pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
539 pgprot_s2_device = __pgprot(s2_device_pgprot);
540 pgprot_hyp_device = __pgprot(hyp_device_pgprot);
541
542 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
543 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
544 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
545 mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
546 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
547 mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
548 mem_types[MT_ROM].prot_sect |= cp->pmd;
549
550 switch (cp->pmd) {
551 case PMD_SECT_WT:
552 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
553 break;
554 case PMD_SECT_WB:
555 case PMD_SECT_WBWA:
556 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
557 break;
558 }
559 printk("Memory policy: ECC %sabled, Data cache %s\n",
560 ecc_mask ? "en" : "dis", cp->policy);
561
562 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
563 struct mem_type *t = &mem_types[i];
564 if (t->prot_l1)
565 t->prot_l1 |= PMD_DOMAIN(t->domain);
566 if (t->prot_sect)
567 t->prot_sect |= PMD_DOMAIN(t->domain);
568 }
569}
570
571#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
572pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
573 unsigned long size, pgprot_t vma_prot)
574{
575 if (!pfn_valid(pfn))
576 return pgprot_noncached(vma_prot);
577 else if (file->f_flags & O_SYNC)
578 return pgprot_writecombine(vma_prot);
579 return vma_prot;
580}
581EXPORT_SYMBOL(phys_mem_access_prot);
582#endif
583
584#define vectors_base() (vectors_high() ? 0xffff0000 : 0)
585
586static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
587{
588 void *ptr = __va(memblock_alloc(sz, align));
589 memset(ptr, 0, sz);
590 return ptr;
591}
592
593static void __init *early_alloc(unsigned long sz)
594{
595 return early_alloc_aligned(sz, sz);
596}
597
598static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
599{
600 if (pmd_none(*pmd)) {
601 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
602 __pmd_populate(pmd, __pa(pte), prot);
603 }
604 BUG_ON(pmd_bad(*pmd));
605 return pte_offset_kernel(pmd, addr);
606}
607
608static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
609 unsigned long end, unsigned long pfn,
610 const struct mem_type *type)
611{
612 pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
613 do {
614 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
615 pfn++;
616 } while (pte++, addr += PAGE_SIZE, addr != end);
617}
618
619static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
620 unsigned long end, phys_addr_t phys,
621 const struct mem_type *type)
622{
623 pmd_t *p = pmd;
624
625#ifndef CONFIG_ARM_LPAE
626
627
628
629
630
631
632
633
634
635 if (addr & SECTION_SIZE)
636 pmd++;
637#endif
638 do {
639 *pmd = __pmd(phys | type->prot_sect);
640 phys += SECTION_SIZE;
641 } while (pmd++, addr += SECTION_SIZE, addr != end);
642
643 flush_pmd_entry(p);
644}
645
646static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
647 unsigned long end, phys_addr_t phys,
648 const struct mem_type *type)
649{
650 pmd_t *pmd = pmd_offset(pud, addr);
651 unsigned long next;
652
653 do {
654
655
656
657
658 next = pmd_addr_end(addr, end);
659
660
661
662
663
664 if (type->prot_sect &&
665 ((addr | next | phys) & ~SECTION_MASK) == 0) {
666 __map_init_section(pmd, addr, next, phys, type);
667 } else {
668 alloc_init_pte(pmd, addr, next,
669 __phys_to_pfn(phys), type);
670 }
671
672 phys += next - addr;
673
674 } while (pmd++, addr = next, addr != end);
675}
676
677static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
678 unsigned long end, phys_addr_t phys,
679 const struct mem_type *type)
680{
681 pud_t *pud = pud_offset(pgd, addr);
682 unsigned long next;
683
684 do {
685 next = pud_addr_end(addr, end);
686 alloc_init_pmd(pud, addr, next, phys, type);
687 phys += next - addr;
688 } while (pud++, addr = next, addr != end);
689}
690
691#ifndef CONFIG_ARM_LPAE
692static void __init create_36bit_mapping(struct map_desc *md,
693 const struct mem_type *type)
694{
695 unsigned long addr, length, end;
696 phys_addr_t phys;
697 pgd_t *pgd;
698
699 addr = md->virtual;
700 phys = __pfn_to_phys(md->pfn);
701 length = PAGE_ALIGN(md->length);
702
703 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
704 printk(KERN_ERR "MM: CPU does not support supersection "
705 "mapping for 0x%08llx at 0x%08lx\n",
706 (long long)__pfn_to_phys((u64)md->pfn), addr);
707 return;
708 }
709
710
711
712
713
714
715
716 if (type->domain) {
717 printk(KERN_ERR "MM: invalid domain in supersection "
718 "mapping for 0x%08llx at 0x%08lx\n",
719 (long long)__pfn_to_phys((u64)md->pfn), addr);
720 return;
721 }
722
723 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
724 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
725 " at 0x%08lx invalid alignment\n",
726 (long long)__pfn_to_phys((u64)md->pfn), addr);
727 return;
728 }
729
730
731
732
733
734 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
735
736 pgd = pgd_offset_k(addr);
737 end = addr + length;
738 do {
739 pud_t *pud = pud_offset(pgd, addr);
740 pmd_t *pmd = pmd_offset(pud, addr);
741 int i;
742
743 for (i = 0; i < 16; i++)
744 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
745
746 addr += SUPERSECTION_SIZE;
747 phys += SUPERSECTION_SIZE;
748 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
749 } while (addr != end);
750}
751#endif
752
753
754
755
756
757
758
759
760static void __init create_mapping(struct map_desc *md)
761{
762 unsigned long addr, length, end;
763 phys_addr_t phys;
764 const struct mem_type *type;
765 pgd_t *pgd;
766
767 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
768 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
769 " at 0x%08lx in user region\n",
770 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
771 return;
772 }
773
774 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
775 md->virtual >= PAGE_OFFSET &&
776 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
777 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
778 " at 0x%08lx out of vmalloc space\n",
779 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
780 }
781
782 type = &mem_types[md->type];
783
784#ifndef CONFIG_ARM_LPAE
785
786
787
788 if (md->pfn >= 0x100000) {
789 create_36bit_mapping(md, type);
790 return;
791 }
792#endif
793
794 addr = md->virtual & PAGE_MASK;
795 phys = __pfn_to_phys(md->pfn);
796 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
797
798 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
799 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
800 "be mapped using pages, ignoring.\n",
801 (long long)__pfn_to_phys(md->pfn), addr);
802 return;
803 }
804
805 pgd = pgd_offset_k(addr);
806 end = addr + length;
807 do {
808 unsigned long next = pgd_addr_end(addr, end);
809
810 alloc_init_pud(pgd, addr, next, phys, type);
811
812 phys += next - addr;
813 addr = next;
814 } while (pgd++, addr != end);
815}
816
817
818
819
820void __init iotable_init(struct map_desc *io_desc, int nr)
821{
822 struct map_desc *md;
823 struct vm_struct *vm;
824 struct static_vm *svm;
825
826 if (!nr)
827 return;
828
829 svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm));
830
831 for (md = io_desc; nr; md++, nr--) {
832 create_mapping(md);
833
834 vm = &svm->vm;
835 vm->addr = (void *)(md->virtual & PAGE_MASK);
836 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
837 vm->phys_addr = __pfn_to_phys(md->pfn);
838 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
839 vm->flags |= VM_ARM_MTYPE(md->type);
840 vm->caller = iotable_init;
841 add_static_vm_early(svm++);
842 }
843}
844
845void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
846 void *caller)
847{
848 struct vm_struct *vm;
849 struct static_vm *svm;
850
851 svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm));
852
853 vm = &svm->vm;
854 vm->addr = (void *)addr;
855 vm->size = size;
856 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
857 vm->caller = caller;
858 add_static_vm_early(svm);
859}
860
861#ifndef CONFIG_ARM_LPAE
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876static void __init pmd_empty_section_gap(unsigned long addr)
877{
878 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
879}
880
881static void __init fill_pmd_gaps(void)
882{
883 struct static_vm *svm;
884 struct vm_struct *vm;
885 unsigned long addr, next = 0;
886 pmd_t *pmd;
887
888 list_for_each_entry(svm, &static_vmlist, list) {
889 vm = &svm->vm;
890 addr = (unsigned long)vm->addr;
891 if (addr < next)
892 continue;
893
894
895
896
897
898
899 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
900 pmd = pmd_off_k(addr);
901 if (pmd_none(*pmd))
902 pmd_empty_section_gap(addr & PMD_MASK);
903 }
904
905
906
907
908
909
910 addr += vm->size;
911 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
912 pmd = pmd_off_k(addr) + 1;
913 if (pmd_none(*pmd))
914 pmd_empty_section_gap(addr);
915 }
916
917
918 next = (addr + PMD_SIZE - 1) & PMD_MASK;
919 }
920}
921
922#else
923#define fill_pmd_gaps() do { } while (0)
924#endif
925
926#if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
927static void __init pci_reserve_io(void)
928{
929 struct static_vm *svm;
930
931 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
932 if (svm)
933 return;
934
935 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
936}
937#else
938#define pci_reserve_io() do { } while (0)
939#endif
940
941#ifdef CONFIG_DEBUG_LL
942void __init debug_ll_io_init(void)
943{
944 struct map_desc map;
945
946 debug_ll_addr(&map.pfn, &map.virtual);
947 if (!map.pfn || !map.virtual)
948 return;
949 map.pfn = __phys_to_pfn(map.pfn);
950 map.virtual &= PAGE_MASK;
951 map.length = PAGE_SIZE;
952 map.type = MT_DEVICE;
953 iotable_init(&map, 1);
954}
955#endif
956
957static void * __initdata vmalloc_min =
958 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
959
960
961
962
963
964
965static int __init early_vmalloc(char *arg)
966{
967 unsigned long vmalloc_reserve = memparse(arg, NULL);
968
969 if (vmalloc_reserve < SZ_16M) {
970 vmalloc_reserve = SZ_16M;
971 printk(KERN_WARNING
972 "vmalloc area too small, limiting to %luMB\n",
973 vmalloc_reserve >> 20);
974 }
975
976 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
977 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
978 printk(KERN_WARNING
979 "vmalloc area is too big, limiting to %luMB\n",
980 vmalloc_reserve >> 20);
981 }
982
983 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
984 return 0;
985}
986early_param("vmalloc", early_vmalloc);
987
988phys_addr_t arm_lowmem_limit __initdata = 0;
989
990void __init sanity_check_meminfo(void)
991{
992 phys_addr_t memblock_limit = 0;
993 int i, j, highmem = 0;
994 phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1;
995
996 for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
997 struct membank *bank = &meminfo.bank[j];
998 phys_addr_t size_limit;
999
1000 *bank = meminfo.bank[i];
1001 size_limit = bank->size;
1002
1003 if (bank->start >= vmalloc_limit)
1004 highmem = 1;
1005 else
1006 size_limit = vmalloc_limit - bank->start;
1007
1008 bank->highmem = highmem;
1009
1010#ifdef CONFIG_HIGHMEM
1011
1012
1013
1014
1015 if (!highmem && bank->size > size_limit) {
1016 if (meminfo.nr_banks >= NR_BANKS) {
1017 printk(KERN_CRIT "NR_BANKS too low, "
1018 "ignoring high memory\n");
1019 } else {
1020 memmove(bank + 1, bank,
1021 (meminfo.nr_banks - i) * sizeof(*bank));
1022 meminfo.nr_banks++;
1023 i++;
1024 bank[1].size -= size_limit;
1025 bank[1].start = vmalloc_limit;
1026 bank[1].highmem = highmem = 1;
1027 j++;
1028 }
1029 bank->size = size_limit;
1030 }
1031#else
1032
1033
1034
1035 if (highmem) {
1036 printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
1037 "(!CONFIG_HIGHMEM).\n",
1038 (unsigned long long)bank->start,
1039 (unsigned long long)bank->start + bank->size - 1);
1040 continue;
1041 }
1042
1043
1044
1045
1046
1047 if (bank->size > size_limit) {
1048 printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
1049 "to -%.8llx (vmalloc region overlap).\n",
1050 (unsigned long long)bank->start,
1051 (unsigned long long)bank->start + bank->size - 1,
1052 (unsigned long long)bank->start + size_limit - 1);
1053 bank->size = size_limit;
1054 }
1055#endif
1056 if (!bank->highmem) {
1057 phys_addr_t bank_end = bank->start + bank->size;
1058
1059 if (bank_end > arm_lowmem_limit)
1060 arm_lowmem_limit = bank_end;
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075 if (!memblock_limit) {
1076 if (!IS_ALIGNED(bank->start, SECTION_SIZE))
1077 memblock_limit = bank->start;
1078 else if (!IS_ALIGNED(bank_end, SECTION_SIZE))
1079 memblock_limit = bank_end;
1080 }
1081 }
1082 j++;
1083 }
1084#ifdef CONFIG_HIGHMEM
1085 if (highmem) {
1086 const char *reason = NULL;
1087
1088 if (cache_is_vipt_aliasing()) {
1089
1090
1091
1092
1093
1094 reason = "with VIPT aliasing cache";
1095 }
1096 if (reason) {
1097 printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
1098 reason);
1099 while (j > 0 && meminfo.bank[j - 1].highmem)
1100 j--;
1101 }
1102 }
1103#endif
1104 meminfo.nr_banks = j;
1105 high_memory = __va(arm_lowmem_limit - 1) + 1;
1106
1107
1108
1109
1110
1111
1112 if (memblock_limit)
1113 memblock_limit = round_down(memblock_limit, SECTION_SIZE);
1114 if (!memblock_limit)
1115 memblock_limit = arm_lowmem_limit;
1116
1117 memblock_set_current_limit(memblock_limit);
1118}
1119
1120static inline void prepare_page_table(void)
1121{
1122 unsigned long addr;
1123 phys_addr_t end;
1124
1125
1126
1127
1128 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1129 pmd_clear(pmd_off_k(addr));
1130
1131#ifdef CONFIG_XIP_KERNEL
1132
1133 addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
1134#endif
1135 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1136 pmd_clear(pmd_off_k(addr));
1137
1138
1139
1140
1141 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1142 if (end >= arm_lowmem_limit)
1143 end = arm_lowmem_limit;
1144
1145
1146
1147
1148
1149 for (addr = __phys_to_virt(end);
1150 addr < VMALLOC_START; addr += PMD_SIZE)
1151 pmd_clear(pmd_off_k(addr));
1152}
1153
1154#ifdef CONFIG_ARM_LPAE
1155
1156#define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1157 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1158#else
1159#define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1160#endif
1161
1162
1163
1164
1165void __init arm_mm_memblock_reserve(void)
1166{
1167
1168
1169
1170
1171 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1172
1173#ifdef CONFIG_SA1111
1174
1175
1176
1177
1178 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1179#endif
1180}
1181
1182
1183
1184
1185
1186
1187
1188
1189static void __init devicemaps_init(struct machine_desc *mdesc)
1190{
1191 struct map_desc map;
1192 unsigned long addr;
1193 void *vectors;
1194
1195
1196
1197
1198 vectors = early_alloc(PAGE_SIZE * 2);
1199
1200 early_trap_init(vectors);
1201
1202 for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
1203 pmd_clear(pmd_off_k(addr));
1204
1205
1206
1207
1208
1209#ifdef CONFIG_XIP_KERNEL
1210 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1211 map.virtual = MODULES_VADDR;
1212 map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1213 map.type = MT_ROM;
1214 create_mapping(&map);
1215#endif
1216
1217
1218
1219
1220#ifdef FLUSH_BASE
1221 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1222 map.virtual = FLUSH_BASE;
1223 map.length = SZ_1M;
1224 map.type = MT_CACHECLEAN;
1225 create_mapping(&map);
1226#endif
1227#ifdef FLUSH_BASE_MINICACHE
1228 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1229 map.virtual = FLUSH_BASE_MINICACHE;
1230 map.length = SZ_1M;
1231 map.type = MT_MINICLEAN;
1232 create_mapping(&map);
1233#endif
1234
1235
1236
1237
1238
1239
1240 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1241 map.virtual = 0xffff0000;
1242 map.length = PAGE_SIZE;
1243#ifdef CONFIG_KUSER_HELPERS
1244 map.type = MT_HIGH_VECTORS;
1245#else
1246 map.type = MT_LOW_VECTORS;
1247#endif
1248 create_mapping(&map);
1249
1250 if (!vectors_high()) {
1251 map.virtual = 0;
1252 map.length = PAGE_SIZE * 2;
1253 map.type = MT_LOW_VECTORS;
1254 create_mapping(&map);
1255 }
1256
1257
1258 map.pfn += 1;
1259 map.virtual = 0xffff0000 + PAGE_SIZE;
1260 map.length = PAGE_SIZE;
1261 map.type = MT_LOW_VECTORS;
1262 create_mapping(&map);
1263
1264
1265
1266
1267 if (mdesc->map_io)
1268 mdesc->map_io();
1269 else
1270 debug_ll_io_init();
1271 fill_pmd_gaps();
1272
1273
1274 pci_reserve_io();
1275
1276
1277
1278
1279
1280
1281
1282 local_flush_tlb_all();
1283 flush_cache_all();
1284}
1285
1286static void __init kmap_init(void)
1287{
1288#ifdef CONFIG_HIGHMEM
1289 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1290 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1291#endif
1292}
1293
1294static void __init map_lowmem(void)
1295{
1296 struct memblock_region *reg;
1297
1298
1299 for_each_memblock(memory, reg) {
1300 phys_addr_t start = reg->base;
1301 phys_addr_t end = start + reg->size;
1302 struct map_desc map;
1303
1304 if (end > arm_lowmem_limit)
1305 end = arm_lowmem_limit;
1306 if (start >= end)
1307 break;
1308
1309 map.pfn = __phys_to_pfn(start);
1310 map.virtual = __phys_to_virt(start);
1311 map.length = end - start;
1312 map.type = MT_MEMORY;
1313
1314 create_mapping(&map);
1315 }
1316}
1317
1318
1319
1320
1321
1322void __init paging_init(struct machine_desc *mdesc)
1323{
1324 void *zero_page;
1325
1326 build_mem_type_table();
1327 prepare_page_table();
1328 map_lowmem();
1329 dma_contiguous_remap();
1330 devicemaps_init(mdesc);
1331 kmap_init();
1332 tcm_init();
1333
1334 top_pmd = pmd_off_k(0xffff0000);
1335
1336
1337 zero_page = early_alloc(PAGE_SIZE);
1338
1339 bootmem_init();
1340
1341 empty_zero_page = virt_to_page(zero_page);
1342 __flush_dcache_page(NULL, empty_zero_page);
1343}
1344