LXR linux/arch/hexagon/kernel/irq

   1/*
   2 * First-level interrupt controller model for Hexagon.
   3 *
   4 * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 and
   8 * only version 2 as published by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  18 * 02110-1301, USA.
  19 */
  20
  21#include <linux/interrupt.h>
  22#include <asm/irq.h>
  23#include <asm/hexagon_vm.h>
  24
  25static void mask_irq(struct irq_data *data)
  26{
  27        __vmintop_locdis((long) data->irq);
  28}
  29
  30static void mask_irq_num(unsigned int irq)
  31{
  32        __vmintop_locdis((long) irq);
  33}
  34
  35static void unmask_irq(struct irq_data *data)
  36{
  37        __vmintop_locen((long) data->irq);
  38}
  39
  40/*  This is actually all we need for handle_fasteoi_irq  */
  41static void eoi_irq(struct irq_data *data)
  42{
  43        __vmintop_globen((long) data->irq);
  44}
  45
  46/* Power mamangement wake call. We don't need this, however,
  47 * if this is absent, then an -ENXIO error is returned to the
  48 * msm_serial driver, and it fails to correctly initialize.
  49 * This is a bug in the msm_serial driver, but, for now, we
  50 * work around it here, by providing this bogus handler.
  51 * XXX FIXME!!! remove this when msm_serial is fixed.
  52 */
  53static int set_wake(struct irq_data *data, unsigned int on)
  54{
  55        return 0;
  56}
  57
  58static struct irq_chip hexagon_irq_chip = {
  59        .name           = "HEXAGON",
  60        .irq_mask       = mask_irq,
  61        .irq_unmask     = unmask_irq,
  62        .irq_set_wake   = set_wake,
  63        .irq_eoi        = eoi_irq
  64};
  65
  66/**
  67 * The hexagon core comes with a first-level interrupt controller
  68 * with 32 total possible interrupts.  When the core is embedded
  69 * into different systems/platforms, it is typically wrapped by
  70 * macro cells that provide one or more second-level interrupt
  71 * controllers that are cascaded into one or more of the first-level
  72 * interrupts handled here. The precise wiring of these other
  73 * irqs varies from platform to platform, and are set up & configured
  74 * in the platform-specific files.
  75 *
  76 * The first-level interrupt controller is wrapped by the VM, which
  77 * virtualizes the interrupt controller for us.  It provides a very
  78 * simple, fast & efficient API, and so the fasteoi handler is
  79 * appropriate for this case.
  80 */
  81void __init init_IRQ(void)
  82{
  83        int irq;
  84
  85        for (irq = 0; irq < HEXAGON_CPUINTS; irq++) {
  86                mask_irq_num(irq);
  87                irq_set_chip_and_handler(irq, &hexagon_irq_chip,
  88                                                 handle_fasteoi_irq);
  89        }
  90}
  91