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8#include <linux/export.h>
9#include <linux/bootmem.h>
10#include <linux/console.h>
11#include <linux/cpu.h>
12#include <linux/delay.h>
13#include <linux/errno.h>
14#include <linux/fs.h>
15#include <linux/genhd.h>
16#include <linux/init.h>
17#include <linux/initrd.h>
18#include <linux/interrupt.h>
19#include <linux/kernel.h>
20#include <linux/memblock.h>
21#include <linux/mm.h>
22#include <linux/of_fdt.h>
23#include <linux/of_platform.h>
24#include <linux/pfn.h>
25#include <linux/root_dev.h>
26#include <linux/sched.h>
27#include <linux/seq_file.h>
28#include <linux/start_kernel.h>
29#include <linux/string.h>
30
31#include <asm/cachepart.h>
32#include <asm/clock.h>
33#include <asm/core_reg.h>
34#include <asm/cpu.h>
35#include <asm/da.h>
36#include <asm/highmem.h>
37#include <asm/hwthread.h>
38#include <asm/l2cache.h>
39#include <asm/mach/arch.h>
40#include <asm/metag_mem.h>
41#include <asm/metag_regs.h>
42#include <asm/mmu.h>
43#include <asm/mmzone.h>
44#include <asm/processor.h>
45#include <asm/prom.h>
46#include <asm/sections.h>
47#include <asm/setup.h>
48#include <asm/traps.h>
49
50
51#define DEFAULT_PRIV (TXPRIVEXT_COPRO_BITS | \
52 TXPRIVEXT_TXTRIGGER_BIT | \
53 TXPRIVEXT_TXGBLCREG_BIT | \
54 TXPRIVEXT_ILOCK_BIT | \
55 TXPRIVEXT_TXITACCYC_BIT | \
56 TXPRIVEXT_TXDIVTIME_BIT | \
57 TXPRIVEXT_TXAMAREGX_BIT | \
58 TXPRIVEXT_TXTIMERI_BIT | \
59 TXPRIVEXT_TXSTATUS_BIT | \
60 TXPRIVEXT_TXDISABLE_BIT)
61
62
63#ifdef CONFIG_METAG_META12
64#define META2_PRIV 0
65#else
66#define META2_PRIV (TXPRIVEXT_TXTIMER_BIT | \
67 TXPRIVEXT_TRACE_BIT)
68#endif
69
70
71#ifdef CONFIG_METAG_UNALIGNED
72#define UNALIGNED_PRIV TXPRIVEXT_ALIGNREW_BIT
73#else
74#define UNALIGNED_PRIV 0
75#endif
76
77#define PRIV_BITS (DEFAULT_PRIV | \
78 META2_PRIV | \
79 UNALIGNED_PRIV)
80
81
82
83
84
85
86
87
88
89
90
91#ifdef CONFIG_METAG_META12
92#define PRIVSYSR_BITS TXPRIVSYSR_ALL_BITS
93#else
94#define PRIVSYSR_BITS (TXPRIVSYSR_ALL_BITS & ~TXPRIVSYSR_CORECODE_BIT)
95#endif
96
97
98#define PIOREG_BITS 0xffffffff
99
100
101
102
103
104#define PSYREG_BITS 0xfffffffb
105
106
107extern char _heap_start[];
108
109#ifdef CONFIG_METAG_BUILTIN_DTB
110extern u32 __dtb_start[];
111#endif
112
113#ifdef CONFIG_DA_CONSOLE
114
115extern struct console dash_console;
116#endif
117
118struct machine_desc *machine_desc __initdata;
119
120
121
122
123
124
125u8 cpu_2_hwthread_id[NR_CPUS] __read_mostly = {
126 [0 ... NR_CPUS-1] = BAD_HWTHREAD_ID
127};
128EXPORT_SYMBOL_GPL(cpu_2_hwthread_id);
129
130
131
132
133
134
135u8 hwthread_id_2_cpu[4] __read_mostly = {
136 [0 ... 3] = BAD_CPU_ID
137};
138
139
140
141
142
143
144
145
146unsigned int meta_memoffset;
147EXPORT_SYMBOL(meta_memoffset);
148
149static char __initdata *original_cmd_line;
150
151DEFINE_PER_CPU(PTBI, pTBI);
152
153
154
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156
157
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162
163
164
165static int __init parse_hwthread_map(char *p)
166{
167 int cpu;
168
169 while (*p) {
170 cpu = (*p++) - '0';
171 if (cpu < 0 || cpu > 9)
172 goto err_cpu;
173
174 p++;
175 cpu_2_hwthread_id[cpu] = (*p++) - '0';
176 if (cpu_2_hwthread_id[cpu] >= 4)
177 goto err_thread;
178 hwthread_id_2_cpu[cpu_2_hwthread_id[cpu]] = cpu;
179
180 if (*p == ',')
181 p++;
182 }
183
184 return 0;
185err_cpu:
186 pr_err("%s: hwthread_map cpu argument out of range\n", __func__);
187 return -EINVAL;
188err_thread:
189 pr_err("%s: hwthread_map thread argument out of range\n", __func__);
190 return -EINVAL;
191}
192early_param("hwthread_map", parse_hwthread_map);
193
194void __init dump_machine_table(void)
195{
196 struct machine_desc *p;
197 const char **compat;
198
199 pr_info("Available machine support:\n\tNAME\t\tCOMPATIBLE LIST\n");
200 for_each_machine_desc(p) {
201 pr_info("\t%s\t[", p->name);
202 for (compat = p->dt_compat; compat && *compat; ++compat)
203 printk(" '%s'", *compat);
204 printk(" ]\n");
205 }
206
207 pr_info("\nPlease check your kernel config and/or bootloader.\n");
208
209 hard_processor_halt(HALT_PANIC);
210}
211
212#ifdef CONFIG_METAG_HALT_ON_PANIC
213static int metag_panic_event(struct notifier_block *this, unsigned long event,
214 void *ptr)
215{
216 hard_processor_halt(HALT_PANIC);
217 return NOTIFY_DONE;
218}
219
220static struct notifier_block metag_panic_block = {
221 metag_panic_event,
222 NULL,
223 0
224};
225#endif
226
227void __init setup_arch(char **cmdline_p)
228{
229 unsigned long start_pfn;
230 unsigned long text_start = (unsigned long)(&_stext);
231 unsigned long cpu = smp_processor_id();
232 unsigned long heap_start, heap_end;
233 unsigned long start_pte;
234 PTBI _pTBI;
235 PTBISEG p_heap;
236 int heap_id, i;
237
238 metag_cache_probe();
239
240 metag_da_probe();
241#ifdef CONFIG_DA_CONSOLE
242 if (metag_da_enabled()) {
243
244 register_console(&dash_console);
245 add_preferred_console("ttyDA", 1, NULL);
246 }
247#endif
248
249
250 machine_desc = setup_machine_fdt(original_cmd_line);
251
252 if (!machine_desc) {
253#ifdef CONFIG_METAG_BUILTIN_DTB
254
255 machine_desc = setup_machine_fdt(__dtb_start);
256 if (!machine_desc)
257 panic("Invalid embedded device tree.");
258#else
259
260 machine_desc = default_machine_desc();
261#endif
262#ifndef CONFIG_CMDLINE_FORCE
263
264 if (boot_command_line[0] && original_cmd_line[0])
265 strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
266 strlcat(boot_command_line, original_cmd_line,
267 COMMAND_LINE_SIZE);
268#endif
269 }
270 setup_meta_clocks(machine_desc->clocks);
271
272 *cmdline_p = boot_command_line;
273 parse_early_param();
274
275
276
277
278 check_for_cache_aliasing(cpu);
279
280
281#ifdef CONFIG_METAG_HALT_ON_PANIC
282 atomic_notifier_chain_register(&panic_notifier_list,
283 &metag_panic_block);
284#endif
285
286#ifdef CONFIG_DUMMY_CONSOLE
287 conswitchp = &dummy_con;
288#endif
289
290 if (!(__core_reg_get(TXSTATUS) & TXSTATUS_PSTAT_BIT))
291 panic("Privilege must be enabled for this thread.");
292
293 _pTBI = __TBI(TBID_ISTAT_BIT);
294
295 per_cpu(pTBI, cpu) = _pTBI;
296
297 if (!per_cpu(pTBI, cpu))
298 panic("No TBI found!");
299
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303
304
305
306
307
308
309 for (i = 0; i <= TBID_SIGNUM_MAX; i++)
310 if (i != TBID_SIGNUM_LWK)
311 _pTBI->fnSigs[i] = __TBIUnExpXXX;
312
313
314
315
316 if (PAGE_OFFSET != text_start)
317 panic("Kernel not loaded at PAGE_OFFSET (%#x) but at %#lx.",
318 PAGE_OFFSET, text_start);
319
320 start_pte = mmu_read_second_level_page(text_start);
321
322
323
324
325 if (!(start_pte & _PAGE_KERNEL))
326 panic("kernel pte does not have PRIV set");
327
328
329
330
331
332
333 meta_memoffset = text_start - (start_pte & PAGE_MASK);
334
335
336 heap_id = (__TBIThreadId() & TBID_THREAD_BITS)
337 + TBID_SEG(0, TBID_SEGSCOPE_LOCAL, TBID_SEGTYPE_HEAP);
338
339 p_heap = __TBIFindSeg(NULL, heap_id);
340
341 if (!p_heap)
342 panic("Could not find heap from TBI!");
343
344
345 heap_start = (unsigned long) &_heap_start;
346
347
348
349
350 if (is_global_space(text_start)) {
351 pr_debug("WARNING: running in global space!\n");
352 heap_end = (unsigned long)p_heap->pGAddr + p_heap->Bytes;
353 } else {
354 heap_end = (unsigned long)p_heap->pLAddr + p_heap->Bytes;
355 }
356
357 ROOT_DEV = Root_RAM0;
358
359
360
361
362
363
364 init_mm.start_code = (unsigned long)(&_stext);
365 init_mm.end_code = (unsigned long)(&_etext);
366 init_mm.end_data = (unsigned long)(&_edata);
367 init_mm.brk = (unsigned long)heap_start;
368
369 min_low_pfn = PFN_UP(__pa(text_start));
370 max_low_pfn = PFN_DOWN(__pa(heap_end));
371
372 pfn_base = min_low_pfn;
373
374
375
376
377 max_pfn = max_low_pfn + ((1 << MAX_ORDER) - 1);
378 max_pfn &= ~((1 << MAX_ORDER) - 1);
379
380 start_pfn = PFN_UP(__pa(heap_start));
381
382 if (min_low_pfn & ((1 << MAX_ORDER) - 1)) {
383
384
385
386
387
388
389
390
391 panic("Kernel must be %d byte aligned, currently at %#lx.",
392 1 << (MAX_ORDER + PAGE_SHIFT),
393 min_low_pfn << PAGE_SHIFT);
394 }
395
396#ifdef CONFIG_HIGHMEM
397 highstart_pfn = highend_pfn = max_pfn;
398 high_memory = (void *) __va(PFN_PHYS(highstart_pfn));
399#else
400 high_memory = (void *)__va(PFN_PHYS(max_pfn));
401#endif
402
403 paging_init(heap_end);
404
405 setup_priv();
406
407
408 cpu_2_hwthread_id[smp_processor_id()] = hard_processor_id();
409 hwthread_id_2_cpu[hard_processor_id()] = smp_processor_id();
410
411
412 copy_fdt();
413 unflatten_device_tree();
414
415#ifdef CONFIG_SMP
416 smp_init_cpus();
417#endif
418
419 if (machine_desc->init_early)
420 machine_desc->init_early();
421}
422
423static int __init customize_machine(void)
424{
425
426 if (machine_desc->init_machine)
427 machine_desc->init_machine();
428 else
429 of_platform_populate(NULL, of_default_bus_match_table, NULL,
430 NULL);
431 return 0;
432}
433arch_initcall(customize_machine);
434
435static int __init init_machine_late(void)
436{
437 if (machine_desc->init_late)
438 machine_desc->init_late();
439 return 0;
440}
441late_initcall(init_machine_late);
442
443#ifdef CONFIG_PROC_FS
444
445
446
447static const char *get_cpu_capabilities(unsigned int txenable)
448{
449#ifdef CONFIG_METAG_META21
450
451 int coreid = metag_in32(METAC_CORE_ID);
452 unsigned int dsp_type = (coreid >> 3) & 7;
453 unsigned int fpu_type = (coreid >> 7) & 3;
454
455 switch (dsp_type | fpu_type << 3) {
456 case (0x00): return "EDSP";
457 case (0x01): return "DSP";
458 case (0x08): return "EDSP+LFPU";
459 case (0x09): return "DSP+LFPU";
460 case (0x10): return "EDSP+FPU";
461 case (0x11): return "DSP+FPU";
462 }
463 return "UNKNOWN";
464
465#else
466 if (!(txenable & TXENABLE_CLASS_BITS))
467 return "DSP";
468 else
469 return "";
470#endif
471}
472
473static int show_cpuinfo(struct seq_file *m, void *v)
474{
475 const char *cpu;
476 unsigned int txenable, thread_id, major, minor;
477 unsigned long clockfreq = get_coreclock();
478#ifdef CONFIG_SMP
479 int i;
480 unsigned long lpj;
481#endif
482
483 cpu = "META";
484
485 txenable = __core_reg_get(TXENABLE);
486 major = (txenable & TXENABLE_MAJOR_REV_BITS) >> TXENABLE_MAJOR_REV_S;
487 minor = (txenable & TXENABLE_MINOR_REV_BITS) >> TXENABLE_MINOR_REV_S;
488 thread_id = (txenable >> 8) & 0x3;
489
490#ifdef CONFIG_SMP
491 for_each_online_cpu(i) {
492 lpj = per_cpu(cpu_data, i).loops_per_jiffy;
493 txenable = core_reg_read(TXUCT_ID, TXENABLE_REGNUM,
494 cpu_2_hwthread_id[i]);
495
496 seq_printf(m, "CPU:\t\t%s %d.%d (thread %d)\n"
497 "Clocking:\t%lu.%1luMHz\n"
498 "BogoMips:\t%lu.%02lu\n"
499 "Calibration:\t%lu loops\n"
500 "Capabilities:\t%s\n\n",
501 cpu, major, minor, i,
502 clockfreq / 1000000, (clockfreq / 100000) % 10,
503 lpj / (500000 / HZ), (lpj / (5000 / HZ)) % 100,
504 lpj,
505 get_cpu_capabilities(txenable));
506 }
507#else
508 seq_printf(m, "CPU:\t\t%s %d.%d (thread %d)\n"
509 "Clocking:\t%lu.%1luMHz\n"
510 "BogoMips:\t%lu.%02lu\n"
511 "Calibration:\t%lu loops\n"
512 "Capabilities:\t%s\n",
513 cpu, major, minor, thread_id,
514 clockfreq / 1000000, (clockfreq / 100000) % 10,
515 loops_per_jiffy / (500000 / HZ),
516 (loops_per_jiffy / (5000 / HZ)) % 100,
517 loops_per_jiffy,
518 get_cpu_capabilities(txenable));
519#endif
520
521#ifdef CONFIG_METAG_L2C
522 if (meta_l2c_is_present()) {
523 seq_printf(m, "L2 cache:\t%s\n"
524 "L2 cache size:\t%d KB\n",
525 meta_l2c_is_enabled() ? "enabled" : "disabled",
526 meta_l2c_size() >> 10);
527 }
528#endif
529 return 0;
530}
531
532static void *c_start(struct seq_file *m, loff_t *pos)
533{
534 return (void *)(*pos == 0);
535}
536static void *c_next(struct seq_file *m, void *v, loff_t *pos)
537{
538 return NULL;
539}
540static void c_stop(struct seq_file *m, void *v)
541{
542}
543const struct seq_operations cpuinfo_op = {
544 .start = c_start,
545 .next = c_next,
546 .stop = c_stop,
547 .show = show_cpuinfo,
548};
549#endif
550
551void __init metag_start_kernel(char *args)
552{
553
554
555
556 __core_reg_set(TXTIMER, 0);
557
558
559 memset(__bss_start, 0,
560 (unsigned long)__bss_stop - (unsigned long)__bss_start);
561
562
563 original_cmd_line = args;
564
565 current_thread_info()->cpu = hard_processor_id();
566
567 start_kernel();
568}
569
570
571
572
573
574
575
576void setup_priv(void)
577{
578 unsigned int offset = hard_processor_id() << TXPRIVREG_STRIDE_S;
579
580 __core_reg_set(TXPRIVEXT, PRIV_BITS);
581
582 metag_out32(PRIVSYSR_BITS, T0PRIVSYSR + offset);
583 metag_out32(PIOREG_BITS, T0PIOREG + offset);
584 metag_out32(PSYREG_BITS, T0PSYREG + offset);
585}
586
587PTBI pTBI_get(unsigned int cpu)
588{
589 return per_cpu(pTBI, cpu);
590}
591EXPORT_SYMBOL(pTBI_get);
592
593#if defined(CONFIG_METAG_DSP) && defined(CONFIG_METAG_FPU)
594static char capabilities[] = "dsp fpu";
595#elif defined(CONFIG_METAG_DSP)
596static char capabilities[] = "dsp";
597#elif defined(CONFIG_METAG_FPU)
598static char capabilities[] = "fpu";
599#else
600static char capabilities[] = "";
601#endif
602
603static struct ctl_table caps_kern_table[] = {
604 {
605 .procname = "capabilities",
606 .data = capabilities,
607 .maxlen = sizeof(capabilities),
608 .mode = 0444,
609 .proc_handler = proc_dostring,
610 },
611 {}
612};
613
614static struct ctl_table caps_root_table[] = {
615 {
616 .procname = "kernel",
617 .mode = 0555,
618 .child = caps_kern_table,
619 },
620 {}
621};
622
623static int __init capabilities_register_sysctl(void)
624{
625 struct ctl_table_header *caps_table_header;
626
627 caps_table_header = register_sysctl_table(caps_root_table);
628 if (!caps_table_header) {
629 pr_err("Unable to register CAPABILITIES sysctl\n");
630 return -ENOMEM;
631 }
632
633 return 0;
634}
635
636core_initcall(capabilities_register_sysctl);
637