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10#include <linux/compiler.h>
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/console.h>
14#include <linux/delay.h>
15#include <linux/export.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/serial.h>
19#include <linux/smp.h>
20#include <linux/types.h>
21#include <linux/string.h>
22#include <linux/tty.h>
23#include <linux/time.h>
24#include <linux/platform_device.h>
25#include <linux/serial_core.h>
26#include <linux/serial_8250.h>
27#include <linux/of_fdt.h>
28#include <linux/libfdt.h>
29#include <linux/kexec.h>
30
31#include <asm/processor.h>
32#include <asm/reboot.h>
33#include <asm/smp-ops.h>
34#include <asm/irq_cpu.h>
35#include <asm/mipsregs.h>
36#include <asm/bootinfo.h>
37#include <asm/sections.h>
38#include <asm/time.h>
39
40#include <asm/octeon/octeon.h>
41#include <asm/octeon/pci-octeon.h>
42#include <asm/octeon/cvmx-mio-defs.h>
43
44extern struct plat_smp_ops octeon_smp_ops;
45
46#ifdef CONFIG_PCI
47extern void pci_console_init(const char *arg);
48#endif
49
50static unsigned long long MAX_MEMORY = 512ull << 20;
51
52struct octeon_boot_descriptor *octeon_boot_desc_ptr;
53
54struct cvmx_bootinfo *octeon_bootinfo;
55EXPORT_SYMBOL(octeon_bootinfo);
56
57static unsigned long long RESERVE_LOW_MEM = 0ull;
58#ifdef CONFIG_KEXEC
59#ifdef CONFIG_SMP
60
61
62
63
64static void octeon_kexec_smp_down(void *ignored)
65{
66 int cpu = smp_processor_id();
67
68 local_irq_disable();
69 set_cpu_online(cpu, false);
70 while (!atomic_read(&kexec_ready_to_reboot))
71 cpu_relax();
72
73 asm volatile (
74 " sync \n"
75 " synci ($0) \n");
76
77 relocated_kexec_smp_wait(NULL);
78}
79#endif
80
81#define OCTEON_DDR0_BASE (0x0ULL)
82#define OCTEON_DDR0_SIZE (0x010000000ULL)
83#define OCTEON_DDR1_BASE (0x410000000ULL)
84#define OCTEON_DDR1_SIZE (0x010000000ULL)
85#define OCTEON_DDR2_BASE (0x020000000ULL)
86#define OCTEON_DDR2_SIZE (0x3e0000000ULL)
87#define OCTEON_MAX_PHY_MEM_SIZE (16*1024*1024*1024ULL)
88
89static struct kimage *kimage_ptr;
90
91static void kexec_bootmem_init(uint64_t mem_size, uint32_t low_reserved_bytes)
92{
93 int64_t addr;
94 struct cvmx_bootmem_desc *bootmem_desc;
95
96 bootmem_desc = cvmx_bootmem_get_desc();
97
98 if (mem_size > OCTEON_MAX_PHY_MEM_SIZE) {
99 mem_size = OCTEON_MAX_PHY_MEM_SIZE;
100 pr_err("Error: requested memory too large,"
101 "truncating to maximum size\n");
102 }
103
104 bootmem_desc->major_version = CVMX_BOOTMEM_DESC_MAJ_VER;
105 bootmem_desc->minor_version = CVMX_BOOTMEM_DESC_MIN_VER;
106
107 addr = (OCTEON_DDR0_BASE + RESERVE_LOW_MEM + low_reserved_bytes);
108 bootmem_desc->head_addr = 0;
109
110 if (mem_size <= OCTEON_DDR0_SIZE) {
111 __cvmx_bootmem_phy_free(addr,
112 mem_size - RESERVE_LOW_MEM -
113 low_reserved_bytes, 0);
114 return;
115 }
116
117 __cvmx_bootmem_phy_free(addr,
118 OCTEON_DDR0_SIZE - RESERVE_LOW_MEM -
119 low_reserved_bytes, 0);
120
121 mem_size -= OCTEON_DDR0_SIZE;
122
123 if (mem_size > OCTEON_DDR1_SIZE) {
124 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, OCTEON_DDR1_SIZE, 0);
125 __cvmx_bootmem_phy_free(OCTEON_DDR2_BASE,
126 mem_size - OCTEON_DDR1_SIZE, 0);
127 } else
128 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, mem_size, 0);
129}
130
131static int octeon_kexec_prepare(struct kimage *image)
132{
133 int i;
134 char *bootloader = "kexec";
135
136 octeon_boot_desc_ptr->argc = 0;
137 for (i = 0; i < image->nr_segments; i++) {
138 if (!strncmp(bootloader, (char *)image->segment[i].buf,
139 strlen(bootloader))) {
140
141
142
143
144 int argc = 0, offt;
145 char *str = (char *)image->segment[i].buf;
146 char *ptr = strchr(str, ' ');
147 while (ptr && (OCTEON_ARGV_MAX_ARGS > argc)) {
148 *ptr = '\0';
149 if (ptr[1] != ' ') {
150 offt = (int)(ptr - str + 1);
151 octeon_boot_desc_ptr->argv[argc] =
152 image->segment[i].mem + offt;
153 argc++;
154 }
155 ptr = strchr(ptr + 1, ' ');
156 }
157 octeon_boot_desc_ptr->argc = argc;
158 break;
159 }
160 }
161
162
163
164
165
166 kimage_ptr = image;
167 return 0;
168}
169
170static void octeon_generic_shutdown(void)
171{
172 int i;
173#ifdef CONFIG_SMP
174 int cpu;
175#endif
176 struct cvmx_bootmem_desc *bootmem_desc;
177 void *named_block_array_ptr;
178
179 bootmem_desc = cvmx_bootmem_get_desc();
180 named_block_array_ptr =
181 cvmx_phys_to_ptr(bootmem_desc->named_block_array_addr);
182
183#ifdef CONFIG_SMP
184
185 for_each_online_cpu(cpu)
186 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
187#else
188 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
189#endif
190 if (kimage_ptr != kexec_crash_image) {
191 memset(named_block_array_ptr,
192 0x0,
193 CVMX_BOOTMEM_NUM_NAMED_BLOCKS *
194 sizeof(struct cvmx_bootmem_named_block_desc));
195
196
197
198
199 kexec_bootmem_init(octeon_bootinfo->dram_size*1024ULL*1024ULL,
200 0x100000);
201
202
203
204 for (i = 0; i < kimage_ptr->nr_segments; i++)
205 cvmx_bootmem_alloc_address(
206 kimage_ptr->segment[i].memsz + 2*PAGE_SIZE,
207 kimage_ptr->segment[i].mem - PAGE_SIZE,
208 PAGE_SIZE);
209 } else {
210
211
212
213
214 struct cvmx_bootmem_named_block_desc *ptr =
215 (struct cvmx_bootmem_named_block_desc *)
216 named_block_array_ptr;
217
218 for (i = 0; i < bootmem_desc->named_block_num_blocks; i++)
219 if (ptr[i].size)
220 cvmx_bootmem_free_named(ptr[i].name);
221 }
222 kexec_args[2] = 1UL;
223 kexec_args[3] = (unsigned long)octeon_boot_desc_ptr;
224#ifdef CONFIG_SMP
225 secondary_kexec_args[2] = 0UL;
226 secondary_kexec_args[3] = (unsigned long)octeon_boot_desc_ptr;
227#endif
228}
229
230static void octeon_shutdown(void)
231{
232 octeon_generic_shutdown();
233#ifdef CONFIG_SMP
234 smp_call_function(octeon_kexec_smp_down, NULL, 0);
235 smp_wmb();
236 while (num_online_cpus() > 1) {
237 cpu_relax();
238 mdelay(1);
239 }
240#endif
241}
242
243static void octeon_crash_shutdown(struct pt_regs *regs)
244{
245 octeon_generic_shutdown();
246 default_machine_crash_shutdown(regs);
247}
248
249#endif
250
251#ifdef CONFIG_CAVIUM_RESERVE32
252uint64_t octeon_reserve32_memory;
253EXPORT_SYMBOL(octeon_reserve32_memory);
254#endif
255
256#ifdef CONFIG_KEXEC
257
258
259static uint64_t crashk_size, crashk_base;
260#endif
261
262static int octeon_uart;
263
264extern asmlinkage void handle_int(void);
265extern asmlinkage void plat_irq_dispatch(void);
266
267
268
269
270
271
272int octeon_is_simulation(void)
273{
274 return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM;
275}
276EXPORT_SYMBOL(octeon_is_simulation);
277
278
279
280
281
282
283
284int octeon_is_pci_host(void)
285{
286#ifdef CONFIG_PCI
287 return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST;
288#else
289 return 0;
290#endif
291}
292
293
294
295
296
297
298uint64_t octeon_get_clock_rate(void)
299{
300 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();
301
302 return sysinfo->cpu_clock_hz;
303}
304EXPORT_SYMBOL(octeon_get_clock_rate);
305
306static u64 octeon_io_clock_rate;
307
308u64 octeon_get_io_clock_rate(void)
309{
310 return octeon_io_clock_rate;
311}
312EXPORT_SYMBOL(octeon_get_io_clock_rate);
313
314
315
316
317
318
319
320
321
322void octeon_write_lcd(const char *s)
323{
324 if (octeon_bootinfo->led_display_base_addr) {
325 void __iomem *lcd_address =
326 ioremap_nocache(octeon_bootinfo->led_display_base_addr,
327 8);
328 int i;
329 for (i = 0; i < 8; i++, s++) {
330 if (*s)
331 iowrite8(*s, lcd_address + i);
332 else
333 iowrite8(' ', lcd_address + i);
334 }
335 iounmap(lcd_address);
336 }
337}
338
339
340
341
342
343
344int octeon_get_boot_uart(void)
345{
346 int uart;
347#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
348 uart = 1;
349#else
350 uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ?
351 1 : 0;
352#endif
353 return uart;
354}
355
356
357
358
359
360
361int octeon_get_boot_coremask(void)
362{
363 return octeon_boot_desc_ptr->core_mask;
364}
365
366
367
368
369void octeon_check_cpu_bist(void)
370{
371 const int coreid = cvmx_get_core_num();
372 unsigned long long mask;
373 unsigned long long bist_val;
374
375
376 mask = 0x1f00000000ull;
377 bist_val = read_octeon_c0_icacheerr();
378 if (bist_val & mask)
379 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n",
380 coreid, bist_val);
381
382 bist_val = read_octeon_c0_dcacheerr();
383 if (bist_val & 1)
384 pr_err("Core%d L1 Dcache parity error: "
385 "CacheErr(dcache) = 0x%llx\n",
386 coreid, bist_val);
387
388 mask = 0xfc00000000000000ull;
389 bist_val = read_c0_cvmmemctl();
390 if (bist_val & mask)
391 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n",
392 coreid, bist_val);
393
394 write_octeon_c0_dcacheerr(0);
395}
396
397
398
399
400
401
402static void octeon_restart(char *command)
403{
404
405#ifdef CONFIG_SMP
406 int cpu;
407 for_each_online_cpu(cpu)
408 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
409#else
410 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
411#endif
412
413 mb();
414 while (1)
415 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
416}
417
418
419
420
421
422
423
424static void octeon_kill_core(void *arg)
425{
426 if (octeon_is_simulation())
427
428 asm volatile ("break" ::: "memory");
429
430 local_irq_disable();
431
432 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
433
434 while (true)
435 asm volatile ("wait" ::: "memory");
436}
437
438
439
440
441
442static void octeon_halt(void)
443{
444 smp_call_function(octeon_kill_core, NULL, 0);
445
446 switch (octeon_bootinfo->board_type) {
447 case CVMX_BOARD_TYPE_NAO38:
448
449 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1);
450 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000);
451 break;
452 default:
453 octeon_write_lcd("PowerOff");
454 break;
455 }
456
457 octeon_kill_core(NULL);
458}
459
460
461
462
463
464
465const char *octeon_board_type_string(void)
466{
467 static char name[80];
468 sprintf(name, "%s (%s)",
469 cvmx_board_type_to_string(octeon_bootinfo->board_type),
470 octeon_model_get_string(read_c0_prid()));
471 return name;
472}
473
474const char *get_system_type(void)
475 __attribute__ ((alias("octeon_board_type_string")));
476
477void octeon_user_io_init(void)
478{
479 union octeon_cvmemctl cvmmemctl;
480 union cvmx_iob_fau_timeout fau_timeout;
481 union cvmx_pow_nw_tim nm_tim;
482
483
484 cvmmemctl.u64 = read_c0_cvmmemctl();
485
486
487
488 cvmmemctl.s.dismarkwblongto = 1;
489
490
491 cvmmemctl.s.dismrgclrwbto = 0;
492
493
494
495 cvmmemctl.s.iobdmascrmsb = 0;
496
497
498
499
500 cvmmemctl.s.syncwsmarked = 0;
501
502 cvmmemctl.s.dissyncws = 0;
503
504 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
505 cvmmemctl.s.diswbfst = 1;
506 else
507 cvmmemctl.s.diswbfst = 0;
508
509
510 cvmmemctl.s.xkmemenas = 0;
511
512
513
514 cvmmemctl.s.xkmemenau = 0;
515
516
517
518 cvmmemctl.s.xkioenas = 0;
519
520
521
522 cvmmemctl.s.xkioenau = 0;
523
524
525
526 cvmmemctl.s.allsyncw = 0;
527
528
529
530 cvmmemctl.s.nomerge = 0;
531
532
533
534
535 cvmmemctl.s.didtto = 0;
536
537 cvmmemctl.s.csrckalwys = 0;
538
539 cvmmemctl.s.mclkalwys = 0;
540
541
542
543
544
545
546 cvmmemctl.s.wbfltime = 0;
547
548 cvmmemctl.s.istrnol2 = 0;
549
550
551
552
553
554
555
556 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
557 cvmmemctl.s.wbthresh = 4;
558 else
559 cvmmemctl.s.wbthresh = 10;
560
561
562
563#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
564 cvmmemctl.s.cvmsegenak = 1;
565#else
566 cvmmemctl.s.cvmsegenak = 0;
567#endif
568
569
570 cvmmemctl.s.cvmsegenas = 0;
571
572
573 cvmmemctl.s.cvmsegenau = 0;
574
575
576 cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE;
577
578 write_c0_cvmmemctl(cvmmemctl.u64);
579
580 if (smp_processor_id() == 0)
581 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
582 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
583 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
584
585
586 fau_timeout.u64 = 0;
587 fau_timeout.s.tout_val = 0xfff;
588
589 fau_timeout.s.tout_enb = 0;
590 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64);
591
592 nm_tim.u64 = 0;
593
594 nm_tim.s.nw_tim = 3;
595 cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64);
596
597 write_octeon_c0_icacheerr(0);
598 write_c0_derraddr1(0);
599}
600
601
602
603
604void __init prom_init(void)
605{
606 struct cvmx_sysinfo *sysinfo;
607 const char *arg;
608 char *p;
609 int i;
610 int argc;
611#ifdef CONFIG_CAVIUM_RESERVE32
612 int64_t addr = -1;
613#endif
614
615
616
617
618 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3;
619 octeon_bootinfo =
620 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
621 cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr));
622
623 sysinfo = cvmx_sysinfo_get();
624 memset(sysinfo, 0, sizeof(*sysinfo));
625 sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20;
626 sysinfo->phy_mem_desc_ptr =
627 cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr);
628 sysinfo->core_mask = octeon_bootinfo->core_mask;
629 sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr;
630 sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz;
631 sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2;
632 sysinfo->board_type = octeon_bootinfo->board_type;
633 sysinfo->board_rev_major = octeon_bootinfo->board_rev_major;
634 sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor;
635 memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base,
636 sizeof(sysinfo->mac_addr_base));
637 sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count;
638 memcpy(sysinfo->board_serial_number,
639 octeon_bootinfo->board_serial_number,
640 sizeof(sysinfo->board_serial_number));
641 sysinfo->compact_flash_common_base_addr =
642 octeon_bootinfo->compact_flash_common_base_addr;
643 sysinfo->compact_flash_attribute_base_addr =
644 octeon_bootinfo->compact_flash_attribute_base_addr;
645 sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr;
646 sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
647 sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
648
649 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
650
651 union cvmx_mio_rst_boot rst_boot;
652 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
653 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
654 } else {
655 octeon_io_clock_rate = sysinfo->cpu_clock_hz;
656 }
657
658
659
660
661
662 if (!octeon_is_simulation() &&
663 octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) {
664 cvmx_write_csr(CVMX_LED_EN, 0);
665 cvmx_write_csr(CVMX_LED_PRT, 0);
666 cvmx_write_csr(CVMX_LED_DBG, 0);
667 cvmx_write_csr(CVMX_LED_PRT_FMT, 0);
668 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32);
669 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32);
670 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0);
671 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0);
672 cvmx_write_csr(CVMX_LED_EN, 1);
673 }
674#ifdef CONFIG_CAVIUM_RESERVE32
675
676
677
678
679
680
681
682
683
684
685 addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20,
686 0, 0, 2 << 20,
687 "CAVIUM_RESERVE32", 0);
688 if (addr < 0)
689 pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n");
690 else
691 octeon_reserve32_memory = addr;
692#endif
693
694#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2
695 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) {
696 pr_info("Skipping L2 locking due to reduced L2 cache size\n");
697 } else {
698 uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000;
699#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB
700
701 cvmx_l2c_lock_mem_region(ebase, 0x100);
702#endif
703#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION
704
705 cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80);
706#endif
707#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
708
709 cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80);
710#endif
711#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT
712 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100);
713 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80);
714#endif
715#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY
716 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480);
717#endif
718 }
719#endif
720
721 octeon_check_cpu_bist();
722
723 octeon_uart = octeon_get_boot_uart();
724
725#ifdef CONFIG_SMP
726 octeon_write_lcd("LinuxSMP");
727#else
728 octeon_write_lcd("Linux");
729#endif
730
731#ifdef CONFIG_CAVIUM_GDB
732
733
734
735
736 if (octeon_get_boot_debug_flag()) {
737 cvmx_write_csr(CVMX_CIU_DINT, 1 << cvmx_get_core_num());
738 cvmx_read_csr(CVMX_CIU_DINT);
739 }
740#endif
741
742 octeon_setup_delays();
743
744
745
746
747
748
749
750 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
751 OCTEON_IS_MODEL(OCTEON_CN31XX))
752 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0);
753 else
754 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1);
755
756
757 if (octeon_is_simulation())
758 MAX_MEMORY = 64ull << 20;
759
760 arg = strstr(arcs_cmdline, "mem=");
761 if (arg) {
762 MAX_MEMORY = memparse(arg + 4, &p);
763 if (MAX_MEMORY == 0)
764 MAX_MEMORY = 32ull << 30;
765 if (*p == '@')
766 RESERVE_LOW_MEM = memparse(p + 1, &p);
767 }
768
769 arcs_cmdline[0] = 0;
770 argc = octeon_boot_desc_ptr->argc;
771 for (i = 0; i < argc; i++) {
772 const char *arg =
773 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]);
774 if ((strncmp(arg, "MEM=", 4) == 0) ||
775 (strncmp(arg, "mem=", 4) == 0)) {
776 MAX_MEMORY = memparse(arg + 4, &p);
777 if (MAX_MEMORY == 0)
778 MAX_MEMORY = 32ull << 30;
779 if (*p == '@')
780 RESERVE_LOW_MEM = memparse(p + 1, &p);
781 } else if (strcmp(arg, "ecc_verbose") == 0) {
782#ifdef CONFIG_CAVIUM_REPORT_SINGLE_BIT_ECC
783 __cvmx_interrupt_ecc_report_single_bit_errors = 1;
784 pr_notice("Reporting of single bit ECC errors is "
785 "turned on\n");
786#endif
787#ifdef CONFIG_KEXEC
788 } else if (strncmp(arg, "crashkernel=", 12) == 0) {
789 crashk_size = memparse(arg+12, &p);
790 if (*p == '@')
791 crashk_base = memparse(p+1, &p);
792 strcat(arcs_cmdline, " ");
793 strcat(arcs_cmdline, arg);
794
795
796
797
798
799#endif
800 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 <
801 sizeof(arcs_cmdline) - 1) {
802 strcat(arcs_cmdline, " ");
803 strcat(arcs_cmdline, arg);
804 }
805 }
806
807 if (strstr(arcs_cmdline, "console=") == NULL) {
808#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
809 strcat(arcs_cmdline, " console=ttyS0,115200");
810#else
811 if (octeon_uart == 1)
812 strcat(arcs_cmdline, " console=ttyS1,115200");
813 else
814 strcat(arcs_cmdline, " console=ttyS0,115200");
815#endif
816 }
817
818 if (octeon_is_simulation()) {
819
820
821
822
823
824 strcat(arcs_cmdline, " rw root=1f00 slram=root,0x40000000,+1073741824");
825 }
826
827 mips_hpt_frequency = octeon_get_clock_rate();
828
829 octeon_init_cvmcount();
830
831 _machine_restart = octeon_restart;
832 _machine_halt = octeon_halt;
833
834#ifdef CONFIG_KEXEC
835 _machine_kexec_shutdown = octeon_shutdown;
836 _machine_crash_shutdown = octeon_crash_shutdown;
837 _machine_kexec_prepare = octeon_kexec_prepare;
838#endif
839
840 octeon_user_io_init();
841 register_smp_ops(&octeon_smp_ops);
842}
843
844
845#ifndef CONFIG_CRASH_DUMP
846static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size)
847{
848 if (addr > *mem && addr < *mem + *size) {
849 u64 inc = addr - *mem;
850 add_memory_region(*mem, inc, BOOT_MEM_RAM);
851 *mem += inc;
852 *size -= inc;
853 }
854
855 if (addr == *mem && *size > PAGE_SIZE) {
856 *mem += PAGE_SIZE;
857 *size -= PAGE_SIZE;
858 }
859}
860#endif
861
862void __init plat_mem_setup(void)
863{
864 uint64_t mem_alloc_size;
865 uint64_t total;
866 uint64_t crashk_end;
867#ifndef CONFIG_CRASH_DUMP
868 int64_t memory;
869 uint64_t kernel_start;
870 uint64_t kernel_size;
871#endif
872
873 total = 0;
874 crashk_end = 0;
875
876
877
878
879
880
881
882
883 mem_alloc_size = 4 << 20;
884 if (mem_alloc_size > MAX_MEMORY)
885 mem_alloc_size = MAX_MEMORY;
886
887
888#ifdef CONFIG_CRASH_DUMP
889 add_memory_region(RESERVE_LOW_MEM, MAX_MEMORY, BOOT_MEM_RAM);
890 total += MAX_MEMORY;
891#else
892#ifdef CONFIG_KEXEC
893 if (crashk_size > 0) {
894 add_memory_region(crashk_base, crashk_size, BOOT_MEM_RAM);
895 crashk_end = crashk_base + crashk_size;
896 }
897#endif
898
899
900
901
902
903 cvmx_bootmem_lock();
904 while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX)
905 && (total < MAX_MEMORY)) {
906 memory = cvmx_bootmem_phy_alloc(mem_alloc_size,
907 __pa_symbol(&__init_end), -1,
908 0x100000,
909 CVMX_BOOTMEM_FLAG_NO_LOCKING);
910 if (memory >= 0) {
911 u64 size = mem_alloc_size;
912#ifdef CONFIG_KEXEC
913 uint64_t end;
914#endif
915
916
917
918
919
920
921
922 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE,
923 &memory, &size);
924 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE +
925 CVMX_PCIE_BAR1_PHYS_SIZE,
926 &memory, &size);
927#ifdef CONFIG_KEXEC
928 end = memory + mem_alloc_size;
929
930
931
932
933
934
935 if (memory < crashk_base && end > crashk_end) {
936
937 add_memory_region(memory,
938 crashk_base - memory,
939 BOOT_MEM_RAM);
940 total += crashk_base - memory;
941 add_memory_region(crashk_end,
942 end - crashk_end,
943 BOOT_MEM_RAM);
944 total += end - crashk_end;
945 continue;
946 }
947
948 if (memory >= crashk_base && end <= crashk_end)
949
950
951
952
953 continue;
954
955 if (memory > crashk_base && memory < crashk_end &&
956 end > crashk_end) {
957
958
959
960
961 mem_alloc_size -= crashk_end - memory;
962 memory = crashk_end;
963 } else if (memory < crashk_base && end > crashk_base &&
964 end < crashk_end)
965
966
967
968
969 mem_alloc_size -= end - crashk_base;
970#endif
971 add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
972 total += mem_alloc_size;
973
974 mem_alloc_size = 4 << 20;
975 } else {
976 break;
977 }
978 }
979 cvmx_bootmem_unlock();
980
981 kernel_start = (unsigned long) _text;
982 kernel_size = _end - _text;
983
984
985 kernel_start &= ~0xffffffff80000000ULL;
986 add_memory_region(kernel_start, kernel_size, BOOT_MEM_RAM);
987#endif
988
989#ifdef CONFIG_CAVIUM_RESERVE32
990
991
992
993
994
995 if (octeon_reserve32_memory)
996 cvmx_bootmem_free_named("CAVIUM_RESERVE32");
997#endif
998
999 if (total == 0)
1000 panic("Unable to allocate memory from "
1001 "cvmx_bootmem_phy_alloc\n");
1002}
1003
1004
1005
1006
1007
1008int prom_putchar(char c)
1009{
1010 uint64_t lsrval;
1011
1012
1013 do {
1014 lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart));
1015 } while ((lsrval & 0x20) == 0);
1016
1017
1018 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull);
1019 return 1;
1020}
1021EXPORT_SYMBOL(prom_putchar);
1022
1023void prom_free_prom_memory(void)
1024{
1025 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) {
1026
1027 u32 insn;
1028 u32 *foo;
1029
1030 foo = &insn;
1031
1032 asm volatile("# before" : : : "memory");
1033 prefetch(foo);
1034 asm volatile(
1035 ".set push\n\t"
1036 ".set noreorder\n\t"
1037 "bal 1f\n\t"
1038 "nop\n"
1039 "1:\tlw %0,-12($31)\n\t"
1040 ".set pop\n\t"
1041 : "=r" (insn) : : "$31", "memory");
1042
1043 if ((insn >> 26) != 0x33)
1044 panic("No PREF instruction at Core-14449 probe point.");
1045
1046 if (((insn >> 16) & 0x1f) != 28)
1047 panic("Core-14449 WAR not in place (%04x).\n"
1048 "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", insn);
1049 }
1050}
1051
1052int octeon_prune_device_tree(void);
1053
1054extern const char __dtb_octeon_3xxx_begin;
1055extern const char __dtb_octeon_3xxx_end;
1056extern const char __dtb_octeon_68xx_begin;
1057extern const char __dtb_octeon_68xx_end;
1058void __init device_tree_init(void)
1059{
1060 int dt_size;
1061 struct boot_param_header *fdt;
1062 bool do_prune;
1063
1064 if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) {
1065 fdt = phys_to_virt(octeon_bootinfo->fdt_addr);
1066 if (fdt_check_header(fdt))
1067 panic("Corrupt Device Tree passed to kernel.");
1068 dt_size = be32_to_cpu(fdt->totalsize);
1069 do_prune = false;
1070 } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
1071 fdt = (struct boot_param_header *)&__dtb_octeon_68xx_begin;
1072 dt_size = &__dtb_octeon_68xx_end - &__dtb_octeon_68xx_begin;
1073 do_prune = true;
1074 } else {
1075 fdt = (struct boot_param_header *)&__dtb_octeon_3xxx_begin;
1076 dt_size = &__dtb_octeon_3xxx_end - &__dtb_octeon_3xxx_begin;
1077 do_prune = true;
1078 }
1079
1080
1081 initial_boot_params = early_init_dt_alloc_memory_arch(dt_size, 8);
1082 if (initial_boot_params == NULL)
1083 panic("Could not allocate initial_boot_params\n");
1084 memcpy(initial_boot_params, fdt, dt_size);
1085
1086 if (do_prune) {
1087 octeon_prune_device_tree();
1088 pr_info("Using internal Device Tree.\n");
1089 } else {
1090 pr_info("Using passed Device Tree.\n");
1091 }
1092 unflatten_device_tree();
1093}
1094
1095static int __initdata disable_octeon_edac_p;
1096
1097static int __init disable_octeon_edac(char *str)
1098{
1099 disable_octeon_edac_p = 1;
1100 return 0;
1101}
1102early_param("disable_octeon_edac", disable_octeon_edac);
1103
1104static char *edac_device_names[] = {
1105 "octeon_l2c_edac",
1106 "octeon_pc_edac",
1107};
1108
1109static int __init edac_devinit(void)
1110{
1111 struct platform_device *dev;
1112 int i, err = 0;
1113 int num_lmc;
1114 char *name;
1115
1116 if (disable_octeon_edac_p)
1117 return 0;
1118
1119 for (i = 0; i < ARRAY_SIZE(edac_device_names); i++) {
1120 name = edac_device_names[i];
1121 dev = platform_device_register_simple(name, -1, NULL, 0);
1122 if (IS_ERR(dev)) {
1123 pr_err("Registation of %s failed!\n", name);
1124 err = PTR_ERR(dev);
1125 }
1126 }
1127
1128 num_lmc = OCTEON_IS_MODEL(OCTEON_CN68XX) ? 4 :
1129 (OCTEON_IS_MODEL(OCTEON_CN56XX) ? 2 : 1);
1130 for (i = 0; i < num_lmc; i++) {
1131 dev = platform_device_register_simple("octeon_lmc_edac",
1132 i, NULL, 0);
1133 if (IS_ERR(dev)) {
1134 pr_err("Registation of octeon_lmc_edac %d failed!\n", i);
1135 err = PTR_ERR(dev);
1136 }
1137 }
1138
1139 return err;
1140}
1141device_initcall(edac_devinit);
1142