1#ifndef BCM63XX_DEV_ENET_H_
2#define BCM63XX_DEV_ENET_H_
3
4#include <linux/if_ether.h>
5#include <linux/init.h>
6
7#include <bcm63xx_regs.h>
8
9
10
11
12struct bcm63xx_enet_platform_data {
13 char mac_addr[ETH_ALEN];
14
15 int has_phy;
16
17
18 int use_internal_phy;
19
20
21 int phy_id;
22 int has_phy_interrupt;
23 int phy_interrupt;
24
25
26
27 int pause_auto;
28 int pause_rx;
29 int pause_tx;
30
31
32 int force_speed_100;
33 int force_duplex_full;
34
35
36
37 int (*mii_config)(struct net_device *dev, int probe,
38 int (*mii_read)(struct net_device *dev,
39 int phy_id, int reg),
40 void (*mii_write)(struct net_device *dev,
41 int phy_id, int reg, int val));
42
43
44 u32 dma_chan_en_mask;
45
46
47 u32 dma_chan_int_mask;
48
49
50 bool dma_has_sram;
51
52
53 unsigned int dma_chan_width;
54
55
56 unsigned int dma_desc_shift;
57};
58
59
60
61
62#define ENETSW_MAX_PORT 8
63#define ENETSW_PORTS_6328 5
64#define ENETSW_PORTS_6368 6
65
66#define ENETSW_RGMII_PORT0 4
67
68struct bcm63xx_enetsw_port {
69 int used;
70 int phy_id;
71
72 int bypass_link;
73 int force_speed;
74 int force_duplex_full;
75
76 const char *name;
77};
78
79struct bcm63xx_enetsw_platform_data {
80 char mac_addr[ETH_ALEN];
81 int num_ports;
82 struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
83
84
85 u32 dma_chan_en_mask;
86
87
88 u32 dma_chan_int_mask;
89
90
91 unsigned int dma_chan_width;
92
93
94 bool dma_has_sram;
95};
96
97int __init bcm63xx_enet_register(int unit,
98 const struct bcm63xx_enet_platform_data *pd);
99
100int bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd);
101
102enum bcm63xx_regs_enetdmac {
103 ENETDMAC_CHANCFG,
104 ENETDMAC_IR,
105 ENETDMAC_IRMASK,
106 ENETDMAC_MAXBURST,
107 ENETDMAC_BUFALLOC,
108 ENETDMAC_RSTART,
109 ENETDMAC_FC,
110 ENETDMAC_LEN,
111};
112
113static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg)
114{
115#ifdef BCMCPU_RUNTIME_DETECT
116 extern const unsigned long *bcm63xx_regs_enetdmac;
117
118 return bcm63xx_regs_enetdmac[reg];
119#else
120#ifdef CONFIG_BCM63XX_CPU_6345
121 switch (reg) {
122 case ENETDMAC_CHANCFG:
123 return ENETDMA_6345_CHANCFG_REG;
124 case ENETDMAC_IR:
125 return ENETDMA_6345_IR_REG;
126 case ENETDMAC_IRMASK:
127 return ENETDMA_6345_IRMASK_REG;
128 case ENETDMAC_MAXBURST:
129 return ENETDMA_6345_MAXBURST_REG;
130 case ENETDMAC_BUFALLOC:
131 return ENETDMA_6345_BUFALLOC_REG;
132 case ENETDMAC_RSTART:
133 return ENETDMA_6345_RSTART_REG;
134 case ENETDMAC_FC:
135 return ENETDMA_6345_FC_REG;
136 case ENETDMAC_LEN:
137 return ENETDMA_6345_LEN_REG;
138 }
139#endif
140#if defined(CONFIG_BCM63XX_CPU_6328) || \
141 defined(CONFIG_BCM63XX_CPU_6338) || \
142 defined(CONFIG_BCM63XX_CPU_6348) || \
143 defined(CONFIG_BCM63XX_CPU_6358) || \
144 defined(CONFIG_BCM63XX_CPU_6362) || \
145 defined(CONFIG_BCM63XX_CPU_6368)
146 switch (reg) {
147 case ENETDMAC_CHANCFG:
148 return ENETDMAC_CHANCFG_REG;
149 case ENETDMAC_IR:
150 return ENETDMAC_IR_REG;
151 case ENETDMAC_IRMASK:
152 return ENETDMAC_IRMASK_REG;
153 case ENETDMAC_MAXBURST:
154 return ENETDMAC_MAXBURST_REG;
155 case ENETDMAC_BUFALLOC:
156 case ENETDMAC_RSTART:
157 case ENETDMAC_FC:
158 case ENETDMAC_LEN:
159 return 0;
160 }
161#endif
162#endif
163 return 0;
164}
165
166
167#endif
168