1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19#include <linux/cpu.h>
20#include <linux/init.h>
21#include <linux/sched.h>
22#include <linux/ioport.h>
23#include <linux/irq.h>
24#include <linux/pci.h>
25#include <linux/screen_info.h>
26#include <linux/time.h>
27
28#include <asm/fw/fw.h>
29#include <asm/mips-boards/generic.h>
30#include <asm/mips-boards/malta.h>
31#include <asm/mips-boards/maltaint.h>
32#include <asm/dma.h>
33#include <asm/traps.h>
34#include <asm/gcmpregs.h>
35#ifdef CONFIG_VT
36#include <linux/console.h>
37#endif
38
39extern void malta_be_init(void);
40extern int malta_be_handler(struct pt_regs *regs, int is_fixup);
41
42static struct resource standard_io_resources[] = {
43 {
44 .name = "dma1",
45 .start = 0x00,
46 .end = 0x1f,
47 .flags = IORESOURCE_BUSY
48 },
49 {
50 .name = "timer",
51 .start = 0x40,
52 .end = 0x5f,
53 .flags = IORESOURCE_BUSY
54 },
55 {
56 .name = "keyboard",
57 .start = 0x60,
58 .end = 0x6f,
59 .flags = IORESOURCE_BUSY
60 },
61 {
62 .name = "dma page reg",
63 .start = 0x80,
64 .end = 0x8f,
65 .flags = IORESOURCE_BUSY
66 },
67 {
68 .name = "dma2",
69 .start = 0xc0,
70 .end = 0xdf,
71 .flags = IORESOURCE_BUSY
72 },
73};
74
75const char *get_system_type(void)
76{
77 return "MIPS Malta";
78}
79
80#if defined(CONFIG_MIPS_MT_SMTC)
81const char display_string[] = " SMTC LINUX ON MALTA ";
82#else
83const char display_string[] = " LINUX ON MALTA ";
84#endif
85
86#ifdef CONFIG_BLK_DEV_FD
87static void __init fd_activate(void)
88{
89
90
91
92
93
94
95 SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
96
97
98 SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
99 SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
100 SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
101 SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
102
103
104 SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
105}
106#endif
107
108static int __init plat_enable_iocoherency(void)
109{
110 int supported = 0;
111 if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
112 if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
113 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
114 pr_info("Enabled Bonito CPU coherency\n");
115 supported = 1;
116 }
117 if (strstr(fw_getcmdline(), "iobcuncached")) {
118 BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
119 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
120 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
121 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
122 pr_info("Disabled Bonito IOBC coherency\n");
123 } else {
124 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
125 BONITO_PCIMEMBASECFG |=
126 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
127 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
128 pr_info("Enabled Bonito IOBC coherency\n");
129 }
130 } else if (gcmp_niocu() != 0) {
131
132 pr_info("CMP IOCU detected\n");
133 if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) {
134 pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
135 return 0;
136 }
137 supported = 1;
138 }
139 hw_coherentio = supported;
140 return supported;
141}
142
143static void __init plat_setup_iocoherency(void)
144{
145#ifdef CONFIG_DMA_NONCOHERENT
146
147
148
149
150
151 if (plat_enable_iocoherency()) {
152 if (coherentio == 0)
153 pr_info("Hardware DMA cache coherency disabled\n");
154 else
155 pr_info("Hardware DMA cache coherency enabled\n");
156 } else {
157 if (coherentio == 1)
158 pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
159 else
160 pr_info("Software DMA cache coherency enabled\n");
161 }
162#else
163 if (!plat_enable_iocoherency())
164 panic("Hardware DMA cache coherency not supported!");
165#endif
166}
167
168#ifdef CONFIG_BLK_DEV_IDE
169static void __init pci_clock_check(void)
170{
171 unsigned int __iomem *jmpr_p =
172 (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
173 int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
174 static const int pciclocks[] __initconst = {
175 33, 20, 25, 30, 12, 16, 37, 10
176 };
177 int pciclock = pciclocks[jmpr];
178 char *argptr = fw_getcmdline();
179
180 if (pciclock != 33 && !strstr(argptr, "idebus=")) {
181 pr_warn("WARNING: PCI clock is %dMHz, setting idebus\n",
182 pciclock);
183 argptr += strlen(argptr);
184 sprintf(argptr, " idebus=%d", pciclock);
185 if (pciclock < 20 || pciclock > 66)
186 pr_warn("WARNING: IDE timing calculations will be incorrect\n");
187 }
188}
189#endif
190
191#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
192static void __init screen_info_setup(void)
193{
194 screen_info = (struct screen_info) {
195 .orig_x = 0,
196 .orig_y = 25,
197 .ext_mem_k = 0,
198 .orig_video_page = 0,
199 .orig_video_mode = 0,
200 .orig_video_cols = 80,
201 .unused2 = 0,
202 .orig_video_ega_bx = 0,
203 .unused3 = 0,
204 .orig_video_lines = 25,
205 .orig_video_isVGA = VIDEO_TYPE_VGAC,
206 .orig_video_points = 16
207 };
208}
209#endif
210
211static void __init bonito_quirks_setup(void)
212{
213 char *argptr;
214
215 argptr = fw_getcmdline();
216 if (strstr(argptr, "debug")) {
217 BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
218 pr_info("Enabled Bonito debug mode\n");
219 } else
220 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
221
222#ifdef CONFIG_DMA_COHERENT
223 if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
224 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
225 pr_info("Enabled Bonito CPU coherency\n");
226
227 argptr = fw_getcmdline();
228 if (strstr(argptr, "iobcuncached")) {
229 BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
230 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
231 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
232 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
233 pr_info("Disabled Bonito IOBC coherency\n");
234 } else {
235 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
236 BONITO_PCIMEMBASECFG |=
237 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
238 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
239 pr_info("Enabled Bonito IOBC coherency\n");
240 }
241 } else
242 panic("Hardware DMA cache coherency not supported");
243#endif
244}
245
246void __init plat_mem_setup(void)
247{
248 unsigned int i;
249
250 mips_pcibios_init();
251
252
253 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
254 request_resource(&ioport_resource, standard_io_resources+i);
255
256
257
258
259 enable_dma(4);
260
261#ifdef CONFIG_DMA_COHERENT
262 if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO)
263 panic("Hardware DMA cache coherency not supported");
264#endif
265
266 if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO)
267 bonito_quirks_setup();
268
269 plat_setup_iocoherency();
270
271#ifdef CONFIG_BLK_DEV_IDE
272 pci_clock_check();
273#endif
274
275#ifdef CONFIG_BLK_DEV_FD
276 fd_activate();
277#endif
278
279#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
280 screen_info_setup();
281#endif
282
283 board_be_init = malta_be_init;
284 board_be_handler = malta_be_handler;
285}
286
