1/* 2 * GE IMP3A Device Tree Source 3 * 4 * Copyright 2010-2011 GE Intelligent Platforms Embedded Systems, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 * 11 * Based on: P2020 DS Device Tree Source 12 * Copyright 2009 Freescale Semiconductor Inc. 13 */ 14 15/include/ "fsl/p2020si-pre.dtsi" 16 17/ { 18 model = "GE_IMP3A"; 19 compatible = "ge,imp3a"; 20 21 memory { 22 device_type = "memory"; 23 }; 24 25 lbc: localbus@fef05000 { 26 reg = <0 0xfef05000 0 0x1000>; 27 28 ranges = <0x0 0x0 0x0 0xff000000 0x01000000 29 0x1 0x0 0x0 0xe0000000 0x08000000 30 0x2 0x0 0x0 0xe8000000 0x08000000 31 0x3 0x0 0x0 0xfc100000 0x00020000 32 0x4 0x0 0x0 0xfc000000 0x00008000 33 0x5 0x0 0x0 0xfc008000 0x00008000 34 0x6 0x0 0x0 0xfee00000 0x00040000 35 0x7 0x0 0x0 0xfee80000 0x00040000>; 36 37 /* nor@0,0 is a mirror of part of the memory in nor@1,0 38 nor@0,0 { 39 #address-cells = <1>; 40 #size-cells = <1>; 41 compatible = "ge,imp3a-firmware-mirror", "cfi-flash"; 42 reg = <0x0 0x0 0x1000000>; 43 bank-width = <2>; 44 device-width = <1>; 45 46 partition@0 { 47 label = "firmware"; 48 reg = <0x0 0x1000000>; 49 read-only; 50 }; 51 }; 52 */ 53 54 nor@1,0 { 55 #address-cells = <1>; 56 #size-cells = <1>; 57 compatible = "ge,imp3a-paged-flash", "cfi-flash"; 58 reg = <0x1 0x0 0x8000000>; 59 bank-width = <2>; 60 device-width = <1>; 61 62 partition@0 { 63 label = "user"; 64 reg = <0x0 0x7800000>; 65 }; 66 67 partition@7800000 { 68 label = "firmware"; 69 reg = <0x7800000 0x800000>; 70 read-only; 71 }; 72 }; 73 74 nvram@3,0 { 75 device_type = "nvram"; 76 compatible = "simtek,stk14ca8"; 77 reg = <0x3 0x0 0x20000>; 78 }; 79 80 fpga@4,0 { 81 compatible = "ge,imp3a-fpga-regs"; 82 reg = <0x4 0x0 0x20>; 83 }; 84 85 gef_pic: pic@4,20 { 86 #interrupt-cells = <1>; 87 interrupt-controller; 88 device_type = "interrupt-controller"; 89 compatible = "ge,imp3a-fpga-pic", "gef,fpga-pic-1.00"; 90 reg = <0x4 0x20 0x20>; 91 interrupts = <6 7 0 0>; 92 }; 93 94 gef_gpio: gpio@4,400 { 95 #gpio-cells = <2>; 96 compatible = "ge,imp3a-gpio"; 97 reg = <0x4 0x400 0x24>; 98 gpio-controller; 99 }; 100 101 wdt@4,800 { 102 compatible = "ge,imp3a-fpga-wdt", "gef,fpga-wdt-1.00", 103 "gef,fpga-wdt"; 104 reg = <0x4 0x800 0x8>; 105 interrupts = <10 4>; 106 interrupt-parent = <&gef_pic>; 107 }; 108 109 /* Second watchdog available, driver currently supports one. 110 wdt@4,808 { 111 compatible = "gef,imp3a-fpga-wdt", "gef,fpga-wdt-1.00", 112 "gef,fpga-wdt"; 113 reg = <0x4 0x808 0x8>; 114 interrupts = <9 4>; 115 interrupt-parent = <&gef_pic>; 116 }; 117 */ 118 119 nand@6,0 { 120 compatible = "fsl,elbc-fcm-nand"; 121 reg = <0x6 0x0 0x40000>; 122 }; 123 124 nand@7,0 { 125 compatible = "fsl,elbc-fcm-nand"; 126 reg = <0x7 0x0 0x40000>; 127 }; 128 }; 129 130 soc: soc@fef00000 { 131 ranges = <0x0 0 0xfef00000 0x100000>; 132 133 i2c@3000 { 134 hwmon@48 { 135 compatible = "national,lm92"; 136 reg = <0x48>; 137 }; 138 139 hwmon@4c { 140 compatible = "adi,adt7461"; 141 reg = <0x4c>; 142 }; 143 144 rtc@51 { 145 compatible = "epson,rx8581"; 146 reg = <0x51>; 147 }; 148 149 eti@6b { 150 compatible = "dallas,ds1682"; 151 reg = <0x6b>; 152 }; 153 }; 154 155 usb@22000 { 156 phy_type = "ulpi"; 157 dr_mode = "host"; 158 }; 159 160 mdio@24520 { 161 phy0: ethernet-phy@0 { 162 interrupt-parent = <&gef_pic>; 163 interrupts = <0xc 0x4>; 164 reg = <0x1>; 165 }; 166 phy1: ethernet-phy@1 { 167 interrupt-parent = <&gef_pic>; 168 interrupts = <0xb 0x4>; 169 reg = <0x2>; 170 }; 171 tbi0: tbi-phy@11 { 172 reg = <0x11>; 173 device_type = "tbi-phy"; 174 }; 175 }; 176 177 mdio@25520 { 178 tbi1: tbi-phy@11 { 179 reg = <0x11>; 180 device_type = "tbi-phy"; 181 }; 182 }; 183 184 mdio@26520 { 185 status = "disabled"; 186 }; 187 188 enet0: ethernet@24000 { 189 tbi-handle = <&tbi0>; 190 phy-handle = <&phy0>; 191 phy-connection-type = "gmii"; 192 }; 193 194 enet1: ethernet@25000 { 195 tbi-handle = <&tbi1>; 196 phy-handle = <&phy1>; 197 phy-connection-type = "gmii"; 198 }; 199 200 enet2: ethernet@26000 { 201 status = "disabled"; 202 }; 203 }; 204 205 pci0: pcie@fef08000 { 206 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 207 0x1000000 0x0 0x00000000 0 0xfe020000 0x0 0x10000>; 208 reg = <0 0xfef08000 0 0x1000>; 209 210 pcie@0 { 211 ranges = <0x2000000 0x0 0xc0000000 212 0x2000000 0x0 0xc0000000 213 0x0 0x20000000 214 215 0x1000000 0x0 0x0 216 0x1000000 0x0 0x0 217 0x0 0x10000>; 218 }; 219 }; 220 221 pci1: pcie@fef09000 { 222 reg = <0 0xfef09000 0 0x1000>; 223 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 224 0x1000000 0x0 0x00000000 0 0xfe010000 0x0 0x10000>; 225 226 pcie@0 { 227 ranges = <0x2000000 0x0 0xa0000000 228 0x2000000 0x0 0xa0000000 229 0x0 0x20000000 230 231 0x1000000 0x0 0x0 232 0x1000000 0x0 0x0 233 0x0 0x10000>; 234 }; 235 236 }; 237 238 pci2: pcie@fef0a000 { 239 reg = <0 0xfef0a000 0 0x1000>; 240 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 241 0x1000000 0x0 0x00000000 0 0xfe000000 0x0 0x10000>; 242 243 pcie@0 { 244 ranges = <0x2000000 0x0 0x80000000 245 0x2000000 0x0 0x80000000 246 0x0 0x20000000 247 248 0x1000000 0x0 0x0 249 0x1000000 0x0 0x0 250 0x0 0x10000>; 251 }; 252 }; 253}; 254 255/include/ "fsl/p2020si-post.dtsi" 256