1/* 2 * MPC8572 DS Core0 Device Tree Source in CAMP mode. 3 * 4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache 5 * can be shared, all the other devices must be assigned to one core only. 6 * This dts file allows core0 to have memory, l2, i2c, dma1, global-util, eth0, 7 * eth1, crypto, pci0, pci1. 8 * 9 * Copyright 2007-2009 Freescale Semiconductor Inc. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 */ 16 17/include/ "mpc8572ds.dts" 18 19/ { 20 model = "fsl,MPC8572DS"; 21 compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP"; 22 23 cpus { 24 PowerPC,8572@0 { 25 }; 26 PowerPC,8572@1 { 27 status = "disabled"; 28 }; 29 }; 30 31 localbus@ffe05000 { 32 status = "disabled"; 33 }; 34 35 soc8572@ffe00000 { 36 serial@4600 { 37 status = "disabled"; 38 }; 39 dma@c300 { 40 status = "disabled"; 41 }; 42 gpio-controller@f000 { 43 }; 44 l2-cache-controller@20000 { 45 cache-size = <0x80000>; // L2, 512K 46 }; 47 ethernet@26000 { 48 status = "disabled"; 49 }; 50 mdio@26520 { 51 status = "disabled"; 52 }; 53 ethernet@27000 { 54 status = "disabled"; 55 }; 56 mdio@27520 { 57 status = "disabled"; 58 }; 59 pic@40000 { 60 protected-sources = < 61 31 32 33 37 38 39 /* enet2 enet3 */ 62 76 77 78 79 26 42 /* dma2 pci2 serial*/ 63 0xe4 0xe5 0xe6 0xe7 /* msi */ 64 >; 65 }; 66 67 msi@41600 { 68 msi-available-ranges = <0 0x80>; 69 interrupts = < 70 0xe0 0 0 0 71 0xe1 0 0 0 72 0xe2 0 0 0 73 0xe3 0 0 0>; 74 }; 75 timer@42100 { 76 status = "disabled"; 77 }; 78 }; 79 pcie@ffe0a000 { 80 status = "disabled"; 81 }; 82}; 83