LXR linux/arch/powerpc/include/asm/eeh.h

   1/*
   2 * Copyright (C) 2001  Dave Engebretsen & Todd Inglett IBM Corporation.
   3 * Copyright 2001-2012 IBM Corporation.
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License as published by
   7 * the Free Software Foundation; either version 2 of the License, or
   8 * (at your option) any later version.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18 */
  19
  20#ifndef _POWERPC_EEH_H
  21#define _POWERPC_EEH_H
  22#ifdef __KERNEL__
  23
  24#include <linux/init.h>
  25#include <linux/list.h>
  26#include <linux/string.h>
  27#include <linux/time.h>
  28
  29struct pci_dev;
  30struct pci_bus;
  31struct device_node;
  32
  33#ifdef CONFIG_EEH
  34
  35/*
  36 * The struct is used to trace PE related EEH functionality.
  37 * In theory, there will have one instance of the struct to
  38 * be created against particular PE. In nature, PEs corelate
  39 * to each other. the struct has to reflect that hierarchy in
  40 * order to easily pick up those affected PEs when one particular
  41 * PE has EEH errors.
  42 *
  43 * Also, one particular PE might be composed of PCI device, PCI
  44 * bus and its subordinate components. The struct also need ship
  45 * the information. Further more, one particular PE is only meaingful
  46 * in the corresponding PHB. Therefore, the root PEs should be created
  47 * against existing PHBs in on-to-one fashion.
  48 */
  49#define EEH_PE_INVALID  (1 << 0)        /* Invalid   */
  50#define EEH_PE_PHB      (1 << 1)        /* PHB PE    */
  51#define EEH_PE_DEVICE   (1 << 2)        /* Device PE */
  52#define EEH_PE_BUS      (1 << 3)        /* Bus PE    */
  53
  54#define EEH_PE_ISOLATED         (1 << 0)        /* Isolated PE          */
  55#define EEH_PE_RECOVERING       (1 << 1)        /* Recovering PE        */
  56#define EEH_PE_PHB_DEAD         (1 << 2)        /* Dead PHB             */
  57
  58#define EEH_PE_KEEP             (1 << 8)        /* Keep PE on hotplug   */
  59
  60struct eeh_pe {
  61        int type;                       /* PE type: PHB/Bus/Device      */
  62        int state;                      /* PE EEH dependent mode        */
  63        int config_addr;                /* Traditional PCI address      */
  64        int addr;                       /* PE configuration address     */
  65        struct pci_controller *phb;     /* Associated PHB               */
  66        struct pci_bus *bus;            /* Top PCI bus for bus PE       */
  67        int check_count;                /* Times of ignored error       */
  68        int freeze_count;               /* Times of froze up            */
  69        struct timeval tstamp;          /* Time on first-time freeze    */
  70        int false_positives;            /* Times of reported #ff's      */
  71        struct eeh_pe *parent;          /* Parent PE                    */
  72        struct list_head child_list;    /* Link PE to the child list    */
  73        struct list_head edevs;         /* Link list of EEH devices     */
  74        struct list_head child;         /* Child PEs                    */
  75};
  76
  77#define eeh_pe_for_each_dev(pe, edev, tmp) \
  78                list_for_each_entry_safe(edev, tmp, &pe->edevs, list)
  79
  80/*
  81 * The struct is used to trace EEH state for the associated
  82 * PCI device node or PCI device. In future, it might
  83 * represent PE as well so that the EEH device to form
  84 * another tree except the currently existing tree of PCI
  85 * buses and PCI devices
  86 */
  87#define EEH_DEV_BRIDGE          (1 << 0)        /* PCI bridge           */
  88#define EEH_DEV_ROOT_PORT       (1 << 1)        /* PCIe root port       */
  89#define EEH_DEV_DS_PORT         (1 << 2)        /* Downstream port      */
  90#define EEH_DEV_IRQ_DISABLED    (1 << 3)        /* Interrupt disabled   */
  91#define EEH_DEV_DISCONNECTED    (1 << 4)        /* Removing from PE     */
  92
  93#define EEH_DEV_SYSFS           (1 << 8)        /* Sysfs created        */
  94
  95struct eeh_dev {
  96        int mode;                       /* EEH mode                     */
  97        int class_code;                 /* Class code of the device     */
  98        int config_addr;                /* Config address               */
  99        int pe_config_addr;             /* PE config address            */
 100        u32 config_space[16];           /* Saved PCI config space       */
 101        u8 pcie_cap;                    /* Saved PCIe capability        */
 102        struct eeh_pe *pe;              /* Associated PE                */
 103        struct list_head list;          /* Form link list in the PE     */
 104        struct pci_controller *phb;     /* Associated PHB               */
 105        struct device_node *dn;         /* Associated device node       */
 106        struct pci_dev *pdev;           /* Associated PCI device        */
 107        struct pci_bus *bus;            /* PCI bus for partial hotplug  */
 108};
 109
 110static inline struct device_node *eeh_dev_to_of_node(struct eeh_dev *edev)
 111{
 112        return edev ? edev->dn : NULL;
 113}
 114
 115static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
 116{
 117        return edev ? edev->pdev : NULL;
 118}
 119
 120/*
 121 * The struct is used to trace the registered EEH operation
 122 * callback functions. Actually, those operation callback
 123 * functions are heavily platform dependent. That means the
 124 * platform should register its own EEH operation callback
 125 * functions before any EEH further operations.
 126 */
 127#define EEH_OPT_DISABLE         0       /* EEH disable  */
 128#define EEH_OPT_ENABLE          1       /* EEH enable   */
 129#define EEH_OPT_THAW_MMIO       2       /* MMIO enable  */
 130#define EEH_OPT_THAW_DMA        3       /* DMA enable   */
 131#define EEH_STATE_UNAVAILABLE   (1 << 0)        /* State unavailable    */
 132#define EEH_STATE_NOT_SUPPORT   (1 << 1)        /* EEH not supported    */
 133#define EEH_STATE_RESET_ACTIVE  (1 << 2)        /* Active reset         */
 134#define EEH_STATE_MMIO_ACTIVE   (1 << 3)        /* Active MMIO          */
 135#define EEH_STATE_DMA_ACTIVE    (1 << 4)        /* Active DMA           */
 136#define EEH_STATE_MMIO_ENABLED  (1 << 5)        /* MMIO enabled         */
 137#define EEH_STATE_DMA_ENABLED   (1 << 6)        /* DMA enabled          */
 138#define EEH_RESET_DEACTIVATE    0       /* Deactivate the PE reset      */
 139#define EEH_RESET_HOT           1       /* Hot reset                    */
 140#define EEH_RESET_FUNDAMENTAL   3       /* Fundamental reset            */
 141#define EEH_LOG_TEMP            1       /* EEH temporary error log      */
 142#define EEH_LOG_PERM            2       /* EEH permanent error log      */
 143
 144struct eeh_ops {
 145        char *name;
 146        int (*init)(void);
 147        int (*post_init)(void);
 148        void* (*of_probe)(struct device_node *dn, void *flag);
 149        int (*dev_probe)(struct pci_dev *dev, void *flag);
 150        int (*set_option)(struct eeh_pe *pe, int option);
 151        int (*get_pe_addr)(struct eeh_pe *pe);
 152        int (*get_state)(struct eeh_pe *pe, int *state);
 153        int (*reset)(struct eeh_pe *pe, int option);
 154        int (*wait_state)(struct eeh_pe *pe, int max_wait);
 155        int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len);
 156        int (*configure_bridge)(struct eeh_pe *pe);
 157        int (*read_config)(struct device_node *dn, int where, int size, u32 *val);
 158        int (*write_config)(struct device_node *dn, int where, int size, u32 val);
 159        int (*next_error)(struct eeh_pe **pe);
 160};
 161
 162extern struct eeh_ops *eeh_ops;
 163extern int eeh_subsystem_enabled;
 164extern raw_spinlock_t confirm_error_lock;
 165extern int eeh_probe_mode;
 166
 167#define EEH_PROBE_MODE_DEV      (1<<0)  /* From PCI device      */
 168#define EEH_PROBE_MODE_DEVTREE  (1<<1)  /* From device tree     */
 169
 170static inline void eeh_probe_mode_set(int flag)
 171{
 172        eeh_probe_mode = flag;
 173}
 174
 175static inline int eeh_probe_mode_devtree(void)
 176{
 177        return (eeh_probe_mode == EEH_PROBE_MODE_DEVTREE);
 178}
 179
 180static inline int eeh_probe_mode_dev(void)
 181{
 182        return (eeh_probe_mode == EEH_PROBE_MODE_DEV);
 183}
 184
 185static inline void eeh_serialize_lock(unsigned long *flags)
 186{
 187        raw_spin_lock_irqsave(&confirm_error_lock, *flags);
 188}
 189
 190static inline void eeh_serialize_unlock(unsigned long flags)
 191{
 192        raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
 193}
 194
 195/*
 196 * Max number of EEH freezes allowed before we consider the device
 197 * to be permanently disabled.
 198 */
 199#define EEH_MAX_ALLOWED_FREEZES 5
 200
 201typedef void *(*eeh_traverse_func)(void *data, void *flag);
 202int eeh_phb_pe_create(struct pci_controller *phb);
 203struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb);
 204struct eeh_pe *eeh_pe_get(struct eeh_dev *edev);
 205int eeh_add_to_parent_pe(struct eeh_dev *edev);
 206int eeh_rmv_from_parent_pe(struct eeh_dev *edev);
 207void eeh_pe_update_time_stamp(struct eeh_pe *pe);
 208void *eeh_pe_traverse(struct eeh_pe *root,
 209                eeh_traverse_func fn, void *flag);
 210void *eeh_pe_dev_traverse(struct eeh_pe *root,
 211                eeh_traverse_func fn, void *flag);
 212void eeh_pe_restore_bars(struct eeh_pe *pe);
 213struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
 214
 215void *eeh_dev_init(struct device_node *dn, void *data);
 216void eeh_dev_phb_init_dynamic(struct pci_controller *phb);
 217int eeh_init(void);
 218int __init eeh_ops_register(struct eeh_ops *ops);
 219int __exit eeh_ops_unregister(const char *name);
 220unsigned long eeh_check_failure(const volatile void __iomem *token,
 221                                unsigned long val);
 222int eeh_dev_check_failure(struct eeh_dev *edev);
 223void eeh_addr_cache_build(void);
 224void eeh_add_device_early(struct device_node *);
 225void eeh_add_device_tree_early(struct device_node *);
 226void eeh_add_device_late(struct pci_dev *);
 227void eeh_add_device_tree_late(struct pci_bus *);
 228void eeh_add_sysfs_files(struct pci_bus *);
 229void eeh_remove_device(struct pci_dev *);
 230
 231/**
 232 * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
 233 *
 234 * If this macro yields TRUE, the caller relays to eeh_check_failure()
 235 * which does further tests out of line.
 236 */
 237#define EEH_POSSIBLE_ERROR(val, type)   ((val) == (type)~0 && eeh_subsystem_enabled)
 238
 239/*
 240 * Reads from a device which has been isolated by EEH will return
 241 * all 1s.  This macro gives an all-1s value of the given size (in
 242 * bytes: 1, 2, or 4) for comparing with the result of a read.
 243 */
 244#define EEH_IO_ERROR_VALUE(size)        (~0U >> ((4 - (size)) * 8))
 245
 246#else /* !CONFIG_EEH */
 247
 248static inline int eeh_init(void)
 249{
 250        return 0;
 251}
 252
 253static inline void *eeh_dev_init(struct device_node *dn, void *data)
 254{
 255        return NULL;
 256}
 257
 258static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { }
 259
 260static inline unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val)
 261{
 262        return val;
 263}
 264
 265#define eeh_dev_check_failure(x) (0)
 266
 267static inline void eeh_addr_cache_build(void) { }
 268
 269static inline void eeh_add_device_early(struct device_node *dn) { }
 270
 271static inline void eeh_add_device_tree_early(struct device_node *dn) { }
 272
 273static inline void eeh_add_device_late(struct pci_dev *dev) { }
 274
 275static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }
 276
 277static inline void eeh_add_sysfs_files(struct pci_bus *bus) { }
 278
 279static inline void eeh_remove_device(struct pci_dev *dev) { }
 280
 281#define EEH_POSSIBLE_ERROR(val, type) (0)
 282#define EEH_IO_ERROR_VALUE(size) (-1UL)
 283#endif /* CONFIG_EEH */
 284
 285#ifdef CONFIG_PPC64
 286/*
 287 * MMIO read/write operations with EEH support.
 288 */
 289static inline u8 eeh_readb(const volatile void __iomem *addr)
 290{
 291        u8 val = in_8(addr);
 292        if (EEH_POSSIBLE_ERROR(val, u8))
 293                return eeh_check_failure(addr, val);
 294        return val;
 295}
 296
 297static inline u16 eeh_readw(const volatile void __iomem *addr)
 298{
 299        u16 val = in_le16(addr);
 300        if (EEH_POSSIBLE_ERROR(val, u16))
 301                return eeh_check_failure(addr, val);
 302        return val;
 303}
 304
 305static inline u32 eeh_readl(const volatile void __iomem *addr)
 306{
 307        u32 val = in_le32(addr);
 308        if (EEH_POSSIBLE_ERROR(val, u32))
 309                return eeh_check_failure(addr, val);
 310        return val;
 311}
 312
 313static inline u64 eeh_readq(const volatile void __iomem *addr)
 314{
 315        u64 val = in_le64(addr);
 316        if (EEH_POSSIBLE_ERROR(val, u64))
 317                return eeh_check_failure(addr, val);
 318        return val;
 319}
 320
 321static inline u16 eeh_readw_be(const volatile void __iomem *addr)
 322{
 323        u16 val = in_be16(addr);
 324        if (EEH_POSSIBLE_ERROR(val, u16))
 325                return eeh_check_failure(addr, val);
 326        return val;
 327}
 328
 329static inline u32 eeh_readl_be(const volatile void __iomem *addr)
 330{
 331        u32 val = in_be32(addr);
 332        if (EEH_POSSIBLE_ERROR(val, u32))
 333                return eeh_check_failure(addr, val);
 334        return val;
 335}
 336
 337static inline u64 eeh_readq_be(const volatile void __iomem *addr)
 338{
 339        u64 val = in_be64(addr);
 340        if (EEH_POSSIBLE_ERROR(val, u64))
 341                return eeh_check_failure(addr, val);
 342        return val;
 343}
 344
 345static inline void eeh_memcpy_fromio(void *dest, const
 346                                     volatile void __iomem *src,
 347                                     unsigned long n)
 348{
 349        _memcpy_fromio(dest, src, n);
 350
 351        /* Look for ffff's here at dest[n].  Assume that at least 4 bytes
 352         * were copied. Check all four bytes.
 353         */
 354        if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
 355                eeh_check_failure(src, *((u32 *)(dest + n - 4)));
 356}
 357
 358/* in-string eeh macros */
 359static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
 360                              int ns)
 361{
 362        _insb(addr, buf, ns);
 363        if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
 364                eeh_check_failure(addr, *(u8*)buf);
 365}
 366
 367static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
 368                              int ns)
 369{
 370        _insw(addr, buf, ns);
 371        if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
 372                eeh_check_failure(addr, *(u16*)buf);
 373}
 374
 375static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
 376                              int nl)
 377{
 378        _insl(addr, buf, nl);
 379        if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
 380                eeh_check_failure(addr, *(u32*)buf);
 381}
 382
 383#endif /* CONFIG_PPC64 */
 384#endif /* __KERNEL__ */
 385#endif /* _POWERPC_EEH_H */
 386