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15#undef DEBUG
16
17#include <linux/sched.h>
18#include <linux/kernel.h>
19#include <linux/mm.h>
20#include <linux/stddef.h>
21#include <linux/export.h>
22#include <linux/unistd.h>
23#include <linux/user.h>
24#include <linux/reboot.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/irq.h>
28#include <linux/seq_file.h>
29#include <linux/root_dev.h>
30#include <linux/console.h>
31#include <linux/mutex.h>
32#include <linux/memory_hotplug.h>
33#include <linux/of_platform.h>
34
35#include <asm/mmu.h>
36#include <asm/processor.h>
37#include <asm/io.h>
38#include <asm/pgtable.h>
39#include <asm/prom.h>
40#include <asm/rtas.h>
41#include <asm/pci-bridge.h>
42#include <asm/iommu.h>
43#include <asm/dma.h>
44#include <asm/machdep.h>
45#include <asm/time.h>
46#include <asm/nvram.h>
47#include <asm/cputable.h>
48#include <asm/ppc-pci.h>
49#include <asm/irq.h>
50#include <asm/spu.h>
51#include <asm/spu_priv1.h>
52#include <asm/udbg.h>
53#include <asm/mpic.h>
54#include <asm/cell-regs.h>
55#include <asm/io-workarounds.h>
56
57#include "interrupt.h"
58#include "pervasive.h"
59#include "ras.h"
60
61#ifdef DEBUG
62#define DBG(fmt...) udbg_printf(fmt)
63#else
64#define DBG(fmt...)
65#endif
66
67static void cell_show_cpuinfo(struct seq_file *m)
68{
69 struct device_node *root;
70 const char *model = "";
71
72 root = of_find_node_by_path("/");
73 if (root)
74 model = of_get_property(root, "model", NULL);
75 seq_printf(m, "machine\t\t: CHRP %s\n", model);
76 of_node_put(root);
77}
78
79static void cell_progress(char *s, unsigned short hex)
80{
81 printk("*** %04x : %s\n", hex, s ? s : "");
82}
83
84static void cell_fixup_pcie_rootcomplex(struct pci_dev *dev)
85{
86 struct pci_controller *hose;
87 const char *s;
88 int i;
89
90 if (!machine_is(cell))
91 return;
92
93
94 if (dev->bus->self != NULL || dev->devfn != 0)
95 return;
96
97 hose = pci_bus_to_host(dev->bus);
98 if (hose == NULL)
99 return;
100
101
102 if (!of_device_is_compatible(hose->dn, "pciex"))
103 return;
104
105
106 s = of_get_property(hose->dn, "model", NULL);
107 if (!s || strcmp(s, "Axon") != 0)
108 return;
109
110 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
111 dev->resource[i].start = dev->resource[i].end = 0;
112 dev->resource[i].flags = 0;
113 }
114
115 printk(KERN_DEBUG "PCI: Hiding resources on Axon PCIE RC %s\n",
116 pci_name(dev));
117}
118DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, cell_fixup_pcie_rootcomplex);
119
120static int cell_setup_phb(struct pci_controller *phb)
121{
122 const char *model;
123 struct device_node *np;
124
125 int rc = rtas_setup_phb(phb);
126 if (rc)
127 return rc;
128
129 np = phb->dn;
130 model = of_get_property(np, "model", NULL);
131 if (model == NULL || strcmp(np->name, "pci"))
132 return 0;
133
134
135 if (strcmp(model, "Spider"))
136 return 0;
137
138 iowa_register_bus(phb, &spiderpci_ops, &spiderpci_iowa_init,
139 (void *)SPIDER_PCI_REG_BASE);
140 return 0;
141}
142
143static const struct of_device_id cell_bus_ids[] __initconst = {
144 { .type = "soc", },
145 { .compatible = "soc", },
146 { .type = "spider", },
147 { .type = "axon", },
148 { .type = "plb5", },
149 { .type = "plb4", },
150 { .type = "opb", },
151 { .type = "ebc", },
152 {},
153};
154
155static int __init cell_publish_devices(void)
156{
157 struct device_node *root = of_find_node_by_path("/");
158 struct device_node *np;
159 int node;
160
161
162 of_platform_bus_probe(NULL, cell_bus_ids, NULL);
163
164
165
166
167 for_each_child_of_node(root, np) {
168 if (np->type == NULL || (strcmp(np->type, "pci") != 0 &&
169 strcmp(np->type, "pciex") != 0))
170 continue;
171 of_platform_device_create(np, NULL, NULL);
172 }
173
174
175
176
177 for_each_online_node(node) {
178 if (cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(node)) == NULL)
179 continue;
180 platform_device_register_simple("cbe-mic", node, NULL, 0);
181 }
182
183 return 0;
184}
185machine_subsys_initcall(cell, cell_publish_devices);
186
187static void __init mpic_init_IRQ(void)
188{
189 struct device_node *dn;
190 struct mpic *mpic;
191
192 for (dn = NULL;
193 (dn = of_find_node_by_name(dn, "interrupt-controller"));) {
194 if (!of_device_is_compatible(dn, "CBEA,platform-open-pic"))
195 continue;
196
197
198
199
200 mpic = mpic_alloc(dn, 0, MPIC_SECONDARY | MPIC_NO_RESET,
201 0, 0, " MPIC ");
202 if (mpic == NULL)
203 continue;
204 mpic_init(mpic);
205 }
206}
207
208
209static void __init cell_init_irq(void)
210{
211 iic_init_IRQ();
212 spider_init_IRQ();
213 mpic_init_IRQ();
214}
215
216static void __init cell_set_dabrx(void)
217{
218 mtspr(SPRN_DABRX, DABRX_KERNEL | DABRX_USER);
219}
220
221static void __init cell_setup_arch(void)
222{
223#ifdef CONFIG_SPU_BASE
224 spu_priv1_ops = &spu_priv1_mmio_ops;
225 spu_management_ops = &spu_management_of_ops;
226#endif
227
228 cbe_regs_init();
229
230 cell_set_dabrx();
231
232#ifdef CONFIG_CBE_RAS
233 cbe_ras_init();
234#endif
235
236#ifdef CONFIG_SMP
237 smp_init_cell();
238#endif
239
240 loops_per_jiffy = 50000000;
241
242
243 init_pci_config_tokens();
244
245 cbe_pervasive_init();
246#ifdef CONFIG_DUMMY_CONSOLE
247 conswitchp = &dummy_con;
248#endif
249
250 mmio_nvram_init();
251}
252
253static int __init cell_probe(void)
254{
255 unsigned long root = of_get_flat_dt_root();
256
257 if (!of_flat_dt_is_compatible(root, "IBM,CBEA") &&
258 !of_flat_dt_is_compatible(root, "IBM,CPBW-1.0"))
259 return 0;
260
261 hpte_init_native();
262
263 return 1;
264}
265
266define_machine(cell) {
267 .name = "Cell",
268 .probe = cell_probe,
269 .setup_arch = cell_setup_arch,
270 .show_cpuinfo = cell_show_cpuinfo,
271 .restart = rtas_restart,
272 .power_off = rtas_power_off,
273 .halt = rtas_halt,
274 .get_boot_time = rtas_get_boot_time,
275 .get_rtc_time = rtas_get_rtc_time,
276 .set_rtc_time = rtas_set_rtc_time,
277 .calibrate_decr = generic_calibrate_decr,
278 .progress = cell_progress,
279 .init_IRQ = cell_init_irq,
280 .pci_setup_phb = cell_setup_phb,
281};
282
