linux/arch/sh/boards/mach-migor/setup.c
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   1/*
   2 * Renesas System Solutions Asia Pte. Ltd - Migo-R
   3 *
   4 * Copyright (C) 2008 Magnus Damm
   5 *
   6 * This file is subject to the terms and conditions of the GNU General Public
   7 * License.  See the file "COPYING" in the main directory of this archive
   8 * for more details.
   9 */
  10#include <linux/init.h>
  11#include <linux/platform_device.h>
  12#include <linux/interrupt.h>
  13#include <linux/input.h>
  14#include <linux/input/sh_keysc.h>
  15#include <linux/mmc/host.h>
  16#include <linux/mmc/sh_mobile_sdhi.h>
  17#include <linux/mtd/physmap.h>
  18#include <linux/mtd/nand.h>
  19#include <linux/i2c.h>
  20#include <linux/regulator/fixed.h>
  21#include <linux/regulator/machine.h>
  22#include <linux/smc91x.h>
  23#include <linux/delay.h>
  24#include <linux/clk.h>
  25#include <linux/gpio.h>
  26#include <linux/videodev2.h>
  27#include <linux/sh_intc.h>
  28#include <video/sh_mobile_lcdc.h>
  29#include <media/sh_mobile_ceu.h>
  30#include <media/ov772x.h>
  31#include <media/soc_camera.h>
  32#include <media/tw9910.h>
  33#include <asm/clock.h>
  34#include <asm/machvec.h>
  35#include <asm/io.h>
  36#include <asm/suspend.h>
  37#include <mach/migor.h>
  38#include <cpu/sh7722.h>
  39
  40/* Address     IRQ  Size  Bus  Description
  41 * 0x00000000       64MB  16   NOR Flash (SP29PL256N)
  42 * 0x0c000000       64MB  64   SDRAM (2xK4M563233G)
  43 * 0x10000000  IRQ0       16   Ethernet (SMC91C111)
  44 * 0x14000000  IRQ4       16   USB 2.0 Host Controller (M66596)
  45 * 0x18000000       8GB    8   NAND Flash (K9K8G08U0A)
  46 */
  47
  48static struct smc91x_platdata smc91x_info = {
  49        .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
  50};
  51
  52static struct resource smc91x_eth_resources[] = {
  53        [0] = {
  54                .name   = "SMC91C111" ,
  55                .start  = 0x10000300,
  56                .end    = 0x1000030f,
  57                .flags  = IORESOURCE_MEM,
  58        },
  59        [1] = {
  60                .start  = evt2irq(0x600), /* IRQ0 */
  61                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  62        },
  63};
  64
  65static struct platform_device smc91x_eth_device = {
  66        .name           = "smc91x",
  67        .num_resources  = ARRAY_SIZE(smc91x_eth_resources),
  68        .resource       = smc91x_eth_resources,
  69        .dev    = {
  70                .platform_data  = &smc91x_info,
  71        },
  72};
  73
  74static struct sh_keysc_info sh_keysc_info = {
  75        .mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
  76        .scan_timing = 3,
  77        .delay = 5,
  78        .keycodes = {
  79                0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
  80                0, KEY_F, KEY_C, KEY_D, KEY_H, KEY_1,
  81                0, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6,
  82                0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
  83                0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
  84        },
  85};
  86
  87static struct resource sh_keysc_resources[] = {
  88        [0] = {
  89                .start  = 0x044b0000,
  90                .end    = 0x044b000f,
  91                .flags  = IORESOURCE_MEM,
  92        },
  93        [1] = {
  94                .start  = evt2irq(0xbe0),
  95                .flags  = IORESOURCE_IRQ,
  96        },
  97};
  98
  99static struct platform_device sh_keysc_device = {
 100        .name           = "sh_keysc",
 101        .id             = 0, /* "keysc0" clock */
 102        .num_resources  = ARRAY_SIZE(sh_keysc_resources),
 103        .resource       = sh_keysc_resources,
 104        .dev    = {
 105                .platform_data  = &sh_keysc_info,
 106        },
 107};
 108
 109static struct mtd_partition migor_nor_flash_partitions[] =
 110{
 111        {
 112                .name = "uboot",
 113                .offset = 0,
 114                .size = (1 * 1024 * 1024),
 115                .mask_flags = MTD_WRITEABLE,    /* Read-only */
 116        },
 117        {
 118                .name = "rootfs",
 119                .offset = MTDPART_OFS_APPEND,
 120                .size = (15 * 1024 * 1024),
 121        },
 122        {
 123                .name = "other",
 124                .offset = MTDPART_OFS_APPEND,
 125                .size = MTDPART_SIZ_FULL,
 126        },
 127};
 128
 129static struct physmap_flash_data migor_nor_flash_data = {
 130        .width          = 2,
 131        .parts          = migor_nor_flash_partitions,
 132        .nr_parts       = ARRAY_SIZE(migor_nor_flash_partitions),
 133};
 134
 135static struct resource migor_nor_flash_resources[] = {
 136        [0] = {
 137                .name           = "NOR Flash",
 138                .start          = 0x00000000,
 139                .end            = 0x03ffffff,
 140                .flags          = IORESOURCE_MEM,
 141        }
 142};
 143
 144static struct platform_device migor_nor_flash_device = {
 145        .name           = "physmap-flash",
 146        .resource       = migor_nor_flash_resources,
 147        .num_resources  = ARRAY_SIZE(migor_nor_flash_resources),
 148        .dev            = {
 149                .platform_data = &migor_nor_flash_data,
 150        },
 151};
 152
 153static struct mtd_partition migor_nand_flash_partitions[] = {
 154        {
 155                .name           = "nanddata1",
 156                .offset         = 0x0,
 157                .size           = 512 * 1024 * 1024,
 158        },
 159        {
 160                .name           = "nanddata2",
 161                .offset         = MTDPART_OFS_APPEND,
 162                .size           = 512 * 1024 * 1024,
 163        },
 164};
 165
 166static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd,
 167                                     unsigned int ctrl)
 168{
 169        struct nand_chip *chip = mtd->priv;
 170
 171        if (cmd == NAND_CMD_NONE)
 172                return;
 173
 174        if (ctrl & NAND_CLE)
 175                writeb(cmd, chip->IO_ADDR_W + 0x00400000);
 176        else if (ctrl & NAND_ALE)
 177                writeb(cmd, chip->IO_ADDR_W + 0x00800000);
 178        else
 179                writeb(cmd, chip->IO_ADDR_W);
 180}
 181
 182static int migor_nand_flash_ready(struct mtd_info *mtd)
 183{
 184        return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
 185}
 186
 187static struct platform_nand_data migor_nand_flash_data = {
 188        .chip = {
 189                .nr_chips = 1,
 190                .partitions = migor_nand_flash_partitions,
 191                .nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
 192                .chip_delay = 20,
 193        },
 194        .ctrl = {
 195                .dev_ready = migor_nand_flash_ready,
 196                .cmd_ctrl = migor_nand_flash_cmd_ctl,
 197        },
 198};
 199
 200static struct resource migor_nand_flash_resources[] = {
 201        [0] = {
 202                .name           = "NAND Flash",
 203                .start          = 0x18000000,
 204                .end            = 0x18ffffff,
 205                .flags          = IORESOURCE_MEM,
 206        },
 207};
 208
 209static struct platform_device migor_nand_flash_device = {
 210        .name           = "gen_nand",
 211        .resource       = migor_nand_flash_resources,
 212        .num_resources  = ARRAY_SIZE(migor_nand_flash_resources),
 213        .dev            = {
 214                .platform_data = &migor_nand_flash_data,
 215        }
 216};
 217
 218static const struct fb_videomode migor_lcd_modes[] = {
 219        {
 220#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
 221                .name = "LB070WV1",
 222                .xres = 800,
 223                .yres = 480,
 224                .left_margin = 64,
 225                .right_margin = 16,
 226                .hsync_len = 120,
 227                .sync = 0,
 228#elif defined(CONFIG_SH_MIGOR_QVGA)
 229                .name = "PH240320T",
 230                .xres = 320,
 231                .yres = 240,
 232                .left_margin = 0,
 233                .right_margin = 16,
 234                .hsync_len = 8,
 235                .sync = FB_SYNC_HOR_HIGH_ACT,
 236#endif
 237                .upper_margin = 1,
 238                .lower_margin = 17,
 239                .vsync_len = 2,
 240        },
 241};
 242
 243static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
 244#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
 245        .clock_source = LCDC_CLK_BUS,
 246        .ch[0] = {
 247                .chan = LCDC_CHAN_MAINLCD,
 248                .fourcc = V4L2_PIX_FMT_RGB565,
 249                .interface_type = RGB16,
 250                .clock_divider = 2,
 251                .lcd_modes = migor_lcd_modes,
 252                .num_modes = ARRAY_SIZE(migor_lcd_modes),
 253                .panel_cfg = { /* 7.0 inch */
 254                        .width = 152,
 255                        .height = 91,
 256                },
 257        }
 258#elif defined(CONFIG_SH_MIGOR_QVGA)
 259        .clock_source = LCDC_CLK_PERIPHERAL,
 260        .ch[0] = {
 261                .chan = LCDC_CHAN_MAINLCD,
 262                .fourcc = V4L2_PIX_FMT_RGB565,
 263                .interface_type = SYS16A,
 264                .clock_divider = 10,
 265                .lcd_modes = migor_lcd_modes,
 266                .num_modes = ARRAY_SIZE(migor_lcd_modes),
 267                .panel_cfg = {
 268                        .width = 49,    /* 2.4 inch */
 269                        .height = 37,
 270                        .setup_sys = migor_lcd_qvga_setup,
 271                },
 272                .sys_bus_cfg = {
 273                        .ldmt2r = 0x06000a09,
 274                        .ldmt3r = 0x180e3418,
 275                        /* set 1s delay to encourage fsync() */
 276                        .deferred_io_msec = 1000,
 277                },
 278        }
 279#endif
 280};
 281
 282static struct resource migor_lcdc_resources[] = {
 283        [0] = {
 284                .name   = "LCDC",
 285                .start  = 0xfe940000, /* P4-only space */
 286                .end    = 0xfe942fff,
 287                .flags  = IORESOURCE_MEM,
 288        },
 289        [1] = {
 290                .start  = evt2irq(0x580),
 291                .flags  = IORESOURCE_IRQ,
 292        },
 293};
 294
 295static struct platform_device migor_lcdc_device = {
 296        .name           = "sh_mobile_lcdc_fb",
 297        .num_resources  = ARRAY_SIZE(migor_lcdc_resources),
 298        .resource       = migor_lcdc_resources,
 299        .dev    = {
 300                .platform_data  = &sh_mobile_lcdc_info,
 301        },
 302};
 303
 304static struct clk *camera_clk;
 305static DEFINE_MUTEX(camera_lock);
 306
 307static void camera_power_on(int is_tw)
 308{
 309        mutex_lock(&camera_lock);
 310
 311        /* Use 10 MHz VIO_CKO instead of 24 MHz to work
 312         * around signal quality issues on Panel Board V2.1.
 313         */
 314        camera_clk = clk_get(NULL, "video_clk");
 315        clk_set_rate(camera_clk, 10000000);
 316        clk_enable(camera_clk); /* start VIO_CKO */
 317
 318        /* use VIO_RST to take camera out of reset */
 319        mdelay(10);
 320        if (is_tw) {
 321                gpio_set_value(GPIO_PTT2, 0);
 322                gpio_set_value(GPIO_PTT0, 0);
 323        } else {
 324                gpio_set_value(GPIO_PTT0, 1);
 325        }
 326        gpio_set_value(GPIO_PTT3, 0);
 327        mdelay(10);
 328        gpio_set_value(GPIO_PTT3, 1);
 329        mdelay(10); /* wait to let chip come out of reset */
 330}
 331
 332static void camera_power_off(void)
 333{
 334        clk_disable(camera_clk); /* stop VIO_CKO */
 335        clk_put(camera_clk);
 336
 337        gpio_set_value(GPIO_PTT3, 0);
 338        mutex_unlock(&camera_lock);
 339}
 340
 341static int ov7725_power(struct device *dev, int mode)
 342{
 343        if (mode)
 344                camera_power_on(0);
 345        else
 346                camera_power_off();
 347
 348        return 0;
 349}
 350
 351static int tw9910_power(struct device *dev, int mode)
 352{
 353        if (mode)
 354                camera_power_on(1);
 355        else
 356                camera_power_off();
 357
 358        return 0;
 359}
 360
 361static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
 362        .flags = SH_CEU_FLAG_USE_8BIT_BUS,
 363};
 364
 365static struct resource migor_ceu_resources[] = {
 366        [0] = {
 367                .name   = "CEU",
 368                .start  = 0xfe910000,
 369                .end    = 0xfe91009f,
 370                .flags  = IORESOURCE_MEM,
 371        },
 372        [1] = {
 373                .start  = evt2irq(0x880),
 374                .flags  = IORESOURCE_IRQ,
 375        },
 376        [2] = {
 377                /* place holder for contiguous memory */
 378        },
 379};
 380
 381static struct platform_device migor_ceu_device = {
 382        .name           = "sh_mobile_ceu",
 383        .id             = 0, /* "ceu0" clock */
 384        .num_resources  = ARRAY_SIZE(migor_ceu_resources),
 385        .resource       = migor_ceu_resources,
 386        .dev    = {
 387                .platform_data  = &sh_mobile_ceu_info,
 388        },
 389};
 390
 391/* Fixed 3.3V regulator to be used by SDHI0 */
 392static struct regulator_consumer_supply fixed3v3_power_consumers[] =
 393{
 394        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
 395        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
 396};
 397
 398static struct resource sdhi_cn9_resources[] = {
 399        [0] = {
 400                .name   = "SDHI",
 401                .start  = 0x04ce0000,
 402                .end    = 0x04ce00ff,
 403                .flags  = IORESOURCE_MEM,
 404        },
 405        [1] = {
 406                .start  = evt2irq(0xe80),
 407                .flags  = IORESOURCE_IRQ,
 408        },
 409};
 410
 411static struct sh_mobile_sdhi_info sh7724_sdhi_data = {
 412        .dma_slave_tx   = SHDMA_SLAVE_SDHI0_TX,
 413        .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
 414        .tmio_caps      = MMC_CAP_SDIO_IRQ,
 415};
 416
 417static struct platform_device sdhi_cn9_device = {
 418        .name           = "sh_mobile_sdhi",
 419        .num_resources  = ARRAY_SIZE(sdhi_cn9_resources),
 420        .resource       = sdhi_cn9_resources,
 421        .dev = {
 422                .platform_data  = &sh7724_sdhi_data,
 423        },
 424};
 425
 426static struct i2c_board_info migor_i2c_devices[] = {
 427        {
 428                I2C_BOARD_INFO("rs5c372b", 0x32),
 429        },
 430        {
 431                I2C_BOARD_INFO("migor_ts", 0x51),
 432                .irq = evt2irq(0x6c0), /* IRQ6 */
 433        },
 434        {
 435                I2C_BOARD_INFO("wm8978", 0x1a),
 436        },
 437};
 438
 439static struct i2c_board_info migor_i2c_camera[] = {
 440        {
 441                I2C_BOARD_INFO("ov772x", 0x21),
 442        },
 443        {
 444                I2C_BOARD_INFO("tw9910", 0x45),
 445        },
 446};
 447
 448static struct ov772x_camera_info ov7725_info;
 449
 450static struct soc_camera_link ov7725_link = {
 451        .power          = ov7725_power,
 452        .board_info     = &migor_i2c_camera[0],
 453        .i2c_adapter_id = 0,
 454        .priv           = &ov7725_info,
 455};
 456
 457static struct tw9910_video_info tw9910_info = {
 458        .buswidth       = SOCAM_DATAWIDTH_8,
 459        .mpout          = TW9910_MPO_FIELD,
 460};
 461
 462static struct soc_camera_link tw9910_link = {
 463        .power          = tw9910_power,
 464        .board_info     = &migor_i2c_camera[1],
 465        .i2c_adapter_id = 0,
 466        .priv           = &tw9910_info,
 467};
 468
 469static struct platform_device migor_camera[] = {
 470        {
 471                .name   = "soc-camera-pdrv",
 472                .id     = 0,
 473                .dev    = {
 474                        .platform_data = &ov7725_link,
 475                },
 476        }, {
 477                .name   = "soc-camera-pdrv",
 478                .id     = 1,
 479                .dev    = {
 480                        .platform_data = &tw9910_link,
 481                },
 482        },
 483};
 484
 485static struct platform_device *migor_devices[] __initdata = {
 486        &smc91x_eth_device,
 487        &sh_keysc_device,
 488        &migor_lcdc_device,
 489        &migor_ceu_device,
 490        &migor_nor_flash_device,
 491        &migor_nand_flash_device,
 492        &sdhi_cn9_device,
 493        &migor_camera[0],
 494        &migor_camera[1],
 495};
 496
 497extern char migor_sdram_enter_start;
 498extern char migor_sdram_enter_end;
 499extern char migor_sdram_leave_start;
 500extern char migor_sdram_leave_end;
 501
 502static int __init migor_devices_setup(void)
 503{
 504        /* register board specific self-refresh code */
 505        sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
 506                                        &migor_sdram_enter_start,
 507                                        &migor_sdram_enter_end,
 508                                        &migor_sdram_leave_start,
 509                                        &migor_sdram_leave_end);
 510
 511        regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
 512                                     ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
 513
 514        /* Let D11 LED show STATUS0 */
 515        gpio_request(GPIO_FN_STATUS0, NULL);
 516
 517        /* Lit D12 LED show PDSTATUS */
 518        gpio_request(GPIO_FN_PDSTATUS, NULL);
 519
 520        /* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
 521        gpio_request(GPIO_FN_IRQ0, NULL);
 522        __raw_writel(0x00003400, BSC_CS4BCR);
 523        __raw_writel(0x00110080, BSC_CS4WCR);
 524
 525        /* KEYSC */
 526        gpio_request(GPIO_FN_KEYOUT0, NULL);
 527        gpio_request(GPIO_FN_KEYOUT1, NULL);
 528        gpio_request(GPIO_FN_KEYOUT2, NULL);
 529        gpio_request(GPIO_FN_KEYOUT3, NULL);
 530        gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
 531        gpio_request(GPIO_FN_KEYIN1, NULL);
 532        gpio_request(GPIO_FN_KEYIN2, NULL);
 533        gpio_request(GPIO_FN_KEYIN3, NULL);
 534        gpio_request(GPIO_FN_KEYIN4, NULL);
 535        gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
 536
 537        /* NAND Flash */
 538        gpio_request(GPIO_FN_CS6A_CE2B, NULL);
 539        __raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
 540        gpio_request(GPIO_PTA1, NULL);
 541        gpio_direction_input(GPIO_PTA1);
 542
 543        /* SDHI */
 544        gpio_request(GPIO_FN_SDHICD, NULL);
 545        gpio_request(GPIO_FN_SDHIWP, NULL);
 546        gpio_request(GPIO_FN_SDHID3, NULL);
 547        gpio_request(GPIO_FN_SDHID2, NULL);
 548        gpio_request(GPIO_FN_SDHID1, NULL);
 549        gpio_request(GPIO_FN_SDHID0, NULL);
 550        gpio_request(GPIO_FN_SDHICMD, NULL);
 551        gpio_request(GPIO_FN_SDHICLK, NULL);
 552
 553        /* Touch Panel */
 554        gpio_request(GPIO_FN_IRQ6, NULL);
 555
 556        /* LCD Panel */
 557#ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */
 558        gpio_request(GPIO_FN_LCDD17, NULL);
 559        gpio_request(GPIO_FN_LCDD16, NULL);
 560        gpio_request(GPIO_FN_LCDD15, NULL);
 561        gpio_request(GPIO_FN_LCDD14, NULL);
 562        gpio_request(GPIO_FN_LCDD13, NULL);
 563        gpio_request(GPIO_FN_LCDD12, NULL);
 564        gpio_request(GPIO_FN_LCDD11, NULL);
 565        gpio_request(GPIO_FN_LCDD10, NULL);
 566        gpio_request(GPIO_FN_LCDD8, NULL);
 567        gpio_request(GPIO_FN_LCDD7, NULL);
 568        gpio_request(GPIO_FN_LCDD6, NULL);
 569        gpio_request(GPIO_FN_LCDD5, NULL);
 570        gpio_request(GPIO_FN_LCDD4, NULL);
 571        gpio_request(GPIO_FN_LCDD3, NULL);
 572        gpio_request(GPIO_FN_LCDD2, NULL);
 573        gpio_request(GPIO_FN_LCDD1, NULL);
 574        gpio_request(GPIO_FN_LCDRS, NULL);
 575        gpio_request(GPIO_FN_LCDCS, NULL);
 576        gpio_request(GPIO_FN_LCDRD, NULL);
 577        gpio_request(GPIO_FN_LCDWR, NULL);
 578        gpio_request(GPIO_PTH2, NULL); /* LCD_DON */
 579        gpio_direction_output(GPIO_PTH2, 1);
 580#endif
 581#ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */
 582        gpio_request(GPIO_FN_LCDD15, NULL);
 583        gpio_request(GPIO_FN_LCDD14, NULL);
 584        gpio_request(GPIO_FN_LCDD13, NULL);
 585        gpio_request(GPIO_FN_LCDD12, NULL);
 586        gpio_request(GPIO_FN_LCDD11, NULL);
 587        gpio_request(GPIO_FN_LCDD10, NULL);
 588        gpio_request(GPIO_FN_LCDD9, NULL);
 589        gpio_request(GPIO_FN_LCDD8, NULL);
 590        gpio_request(GPIO_FN_LCDD7, NULL);
 591        gpio_request(GPIO_FN_LCDD6, NULL);
 592        gpio_request(GPIO_FN_LCDD5, NULL);
 593        gpio_request(GPIO_FN_LCDD4, NULL);
 594        gpio_request(GPIO_FN_LCDD3, NULL);
 595        gpio_request(GPIO_FN_LCDD2, NULL);
 596        gpio_request(GPIO_FN_LCDD1, NULL);
 597        gpio_request(GPIO_FN_LCDD0, NULL);
 598        gpio_request(GPIO_FN_LCDLCLK, NULL);
 599        gpio_request(GPIO_FN_LCDDCK, NULL);
 600        gpio_request(GPIO_FN_LCDVEPWC, NULL);
 601        gpio_request(GPIO_FN_LCDVCPWC, NULL);
 602        gpio_request(GPIO_FN_LCDVSYN, NULL);
 603        gpio_request(GPIO_FN_LCDHSYN, NULL);
 604        gpio_request(GPIO_FN_LCDDISP, NULL);
 605        gpio_request(GPIO_FN_LCDDON, NULL);
 606#endif
 607
 608        /* CEU */
 609        gpio_request(GPIO_FN_VIO_CLK2, NULL);
 610        gpio_request(GPIO_FN_VIO_VD2, NULL);
 611        gpio_request(GPIO_FN_VIO_HD2, NULL);
 612        gpio_request(GPIO_FN_VIO_FLD, NULL);
 613        gpio_request(GPIO_FN_VIO_CKO, NULL);
 614        gpio_request(GPIO_FN_VIO_D15, NULL);
 615        gpio_request(GPIO_FN_VIO_D14, NULL);
 616        gpio_request(GPIO_FN_VIO_D13, NULL);
 617        gpio_request(GPIO_FN_VIO_D12, NULL);
 618        gpio_request(GPIO_FN_VIO_D11, NULL);
 619        gpio_request(GPIO_FN_VIO_D10, NULL);
 620        gpio_request(GPIO_FN_VIO_D9, NULL);
 621        gpio_request(GPIO_FN_VIO_D8, NULL);
 622
 623        gpio_request(GPIO_PTT3, NULL); /* VIO_RST */
 624        gpio_direction_output(GPIO_PTT3, 0);
 625        gpio_request(GPIO_PTT2, NULL); /* TV_IN_EN */
 626        gpio_direction_output(GPIO_PTT2, 1);
 627        gpio_request(GPIO_PTT0, NULL); /* CAM_EN */
 628#ifdef CONFIG_SH_MIGOR_RTA_WVGA
 629        gpio_direction_output(GPIO_PTT0, 0);
 630#else
 631        gpio_direction_output(GPIO_PTT0, 1);
 632#endif
 633        __raw_writew(__raw_readw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */
 634
 635        platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20);
 636
 637        /* SIU: Port B */
 638        gpio_request(GPIO_FN_SIUBOLR, NULL);
 639        gpio_request(GPIO_FN_SIUBOBT, NULL);
 640        gpio_request(GPIO_FN_SIUBISLD, NULL);
 641        gpio_request(GPIO_FN_SIUBOSLD, NULL);
 642        gpio_request(GPIO_FN_SIUMCKB, NULL);
 643
 644        /*
 645         * The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to
 646         * output. Need only SIUB, set to output for master mode (table 34.2)
 647         */
 648        __raw_writew(__raw_readw(PORT_MSELCRA) | 1, PORT_MSELCRA);
 649
 650        i2c_register_board_info(0, migor_i2c_devices,
 651                                ARRAY_SIZE(migor_i2c_devices));
 652
 653        return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
 654}
 655arch_initcall(migor_devices_setup);
 656
 657/* Return the board specific boot mode pin configuration */
 658static int migor_mode_pins(void)
 659{
 660        /* MD0=1, MD1=1, MD2=0: Clock Mode 3
 661         * MD3=0: 16-bit Area0 Bus Width
 662         * MD5=1: Little Endian
 663         * TSTMD=1, MD8=0: Test Mode Disabled
 664         */
 665        return MODE_PIN0 | MODE_PIN1 | MODE_PIN5;
 666}
 667
 668/*
 669 * The Machine Vector
 670 */
 671static struct sh_machine_vector mv_migor __initmv = {
 672        .mv_name                = "Migo-R",
 673        .mv_mode_pins           = migor_mode_pins,
 674};
 675