LXR linux/arch/sh/boards/mach-se/7343/irq.c

   1/*
   2 * Hitachi UL SolutionEngine 7343 FPGA IRQ Support.
   3 *
   4 * Copyright (C) 2008  Yoshihiro Shimoda
   5 * Copyright (C) 2012  Paul Mundt
   6 *
   7 * Based on linux/arch/sh/boards/se/7343/irq.c
   8 * Copyright (C) 2007  Nobuhiro Iwamatsu
   9 *
  10 * This file is subject to the terms and conditions of the GNU General Public
  11 * License.  See the file "COPYING" in the main directory of this archive
  12 * for more details.
  13 */
  14#define DRV_NAME "SE7343-FPGA"
  15#define pr_fmt(fmt) DRV_NAME ": " fmt
  16
  17#define irq_reg_readl   ioread16
  18#define irq_reg_writel  iowrite16
  19
  20#include <linux/init.h>
  21#include <linux/irq.h>
  22#include <linux/interrupt.h>
  23#include <linux/irqdomain.h>
  24#include <linux/io.h>
  25#include <asm/sizes.h>
  26#include <mach-se/mach/se7343.h>
  27
  28#define PA_CPLD_BASE_ADDR       0x11400000
  29#define PA_CPLD_ST_REG          0x08    /* CPLD Interrupt status register */
  30#define PA_CPLD_IMSK_REG        0x0a    /* CPLD Interrupt mask register */
  31
  32static void __iomem *se7343_irq_regs;
  33struct irq_domain *se7343_irq_domain;
  34
  35static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
  36{
  37        struct irq_data *data = irq_get_irq_data(irq);
  38        struct irq_chip *chip = irq_data_get_irq_chip(data);
  39        unsigned long mask;
  40        int bit;
  41
  42        chip->irq_mask_ack(data);
  43
  44        mask = ioread16(se7343_irq_regs + PA_CPLD_ST_REG);
  45
  46        for_each_set_bit(bit, &mask, SE7343_FPGA_IRQ_NR)
  47                generic_handle_irq(irq_linear_revmap(se7343_irq_domain, bit));
  48
  49        chip->irq_unmask(data);
  50}
  51
  52static void __init se7343_domain_init(void)
  53{
  54        int i;
  55
  56        se7343_irq_domain = irq_domain_add_linear(NULL, SE7343_FPGA_IRQ_NR,
  57                                                  &irq_domain_simple_ops, NULL);
  58        if (unlikely(!se7343_irq_domain)) {
  59                printk("Failed to get IRQ domain\n");
  60                return;
  61        }
  62
  63        for (i = 0; i < SE7343_FPGA_IRQ_NR; i++) {
  64                int irq = irq_create_mapping(se7343_irq_domain, i);
  65
  66                if (unlikely(irq == 0)) {
  67                        printk("Failed to allocate IRQ %d\n", i);
  68                        return;
  69                }
  70        }
  71}
  72
  73static void __init se7343_gc_init(void)
  74{
  75        struct irq_chip_generic *gc;
  76        struct irq_chip_type *ct;
  77        unsigned int irq_base;
  78
  79        irq_base = irq_linear_revmap(se7343_irq_domain, 0);
  80
  81        gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7343_irq_regs,
  82                                    handle_level_irq);
  83        if (unlikely(!gc))
  84                return;
  85
  86        ct = gc->chip_types;
  87        ct->chip.irq_mask = irq_gc_mask_set_bit;
  88        ct->chip.irq_unmask = irq_gc_mask_clr_bit;
  89
  90        ct->regs.mask = PA_CPLD_IMSK_REG;
  91
  92        irq_setup_generic_chip(gc, IRQ_MSK(SE7343_FPGA_IRQ_NR),
  93                               IRQ_GC_INIT_MASK_CACHE,
  94                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
  95
  96        irq_set_chained_handler(IRQ0_IRQ, se7343_irq_demux);
  97        irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
  98
  99        irq_set_chained_handler(IRQ1_IRQ, se7343_irq_demux);
 100        irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
 101
 102        irq_set_chained_handler(IRQ4_IRQ, se7343_irq_demux);
 103        irq_set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
 104
 105        irq_set_chained_handler(IRQ5_IRQ, se7343_irq_demux);
 106        irq_set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
 107}
 108
 109/*
 110 * Initialize IRQ setting
 111 */
 112void __init init_7343se_IRQ(void)
 113{
 114        se7343_irq_regs = ioremap(PA_CPLD_BASE_ADDR, SZ_16);
 115        if (unlikely(!se7343_irq_regs)) {
 116                pr_err("Failed to remap CPLD\n");
 117                return;
 118        }
 119
 120        /*
 121         * All FPGA IRQs disabled by default
 122         */
 123        iowrite16(0, se7343_irq_regs + PA_CPLD_IMSK_REG);
 124
 125        __raw_writew(0x2000, 0xb03fffec);       /* mrshpc irq enable */
 126
 127        se7343_domain_init();
 128        se7343_gc_init();
 129}
 130