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15#include <linux/platform_device.h>
16#include <linux/init.h>
17#include <linux/serial.h>
18#include <linux/mm.h>
19#include <linux/serial_sci.h>
20#include <linux/uio_driver.h>
21#include <linux/sh_dma.h>
22#include <linux/sh_timer.h>
23#include <linux/sh_intc.h>
24#include <linux/io.h>
25#include <linux/notifier.h>
26
27#include <asm/suspend.h>
28#include <asm/clock.h>
29#include <asm/mmzone.h>
30
31#include <cpu/dma-register.h>
32#include <cpu/sh7724.h>
33
34
35static const struct sh_dmae_slave_config sh7724_dmae_slaves[] = {
36 {
37 .slave_id = SHDMA_SLAVE_SCIF0_TX,
38 .addr = 0xffe0000c,
39 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
40 .mid_rid = 0x21,
41 }, {
42 .slave_id = SHDMA_SLAVE_SCIF0_RX,
43 .addr = 0xffe00014,
44 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
45 .mid_rid = 0x22,
46 }, {
47 .slave_id = SHDMA_SLAVE_SCIF1_TX,
48 .addr = 0xffe1000c,
49 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
50 .mid_rid = 0x25,
51 }, {
52 .slave_id = SHDMA_SLAVE_SCIF1_RX,
53 .addr = 0xffe10014,
54 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
55 .mid_rid = 0x26,
56 }, {
57 .slave_id = SHDMA_SLAVE_SCIF2_TX,
58 .addr = 0xffe2000c,
59 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
60 .mid_rid = 0x29,
61 }, {
62 .slave_id = SHDMA_SLAVE_SCIF2_RX,
63 .addr = 0xffe20014,
64 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
65 .mid_rid = 0x2a,
66 }, {
67 .slave_id = SHDMA_SLAVE_SCIF3_TX,
68 .addr = 0xa4e30020,
69 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
70 .mid_rid = 0x2d,
71 }, {
72 .slave_id = SHDMA_SLAVE_SCIF3_RX,
73 .addr = 0xa4e30024,
74 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
75 .mid_rid = 0x2e,
76 }, {
77 .slave_id = SHDMA_SLAVE_SCIF4_TX,
78 .addr = 0xa4e40020,
79 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
80 .mid_rid = 0x31,
81 }, {
82 .slave_id = SHDMA_SLAVE_SCIF4_RX,
83 .addr = 0xa4e40024,
84 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
85 .mid_rid = 0x32,
86 }, {
87 .slave_id = SHDMA_SLAVE_SCIF5_TX,
88 .addr = 0xa4e50020,
89 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
90 .mid_rid = 0x35,
91 }, {
92 .slave_id = SHDMA_SLAVE_SCIF5_RX,
93 .addr = 0xa4e50024,
94 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
95 .mid_rid = 0x36,
96 }, {
97 .slave_id = SHDMA_SLAVE_USB0D0_TX,
98 .addr = 0xA4D80100,
99 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
100 .mid_rid = 0x73,
101 }, {
102 .slave_id = SHDMA_SLAVE_USB0D0_RX,
103 .addr = 0xA4D80100,
104 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
105 .mid_rid = 0x73,
106 }, {
107 .slave_id = SHDMA_SLAVE_USB0D1_TX,
108 .addr = 0xA4D80120,
109 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
110 .mid_rid = 0x77,
111 }, {
112 .slave_id = SHDMA_SLAVE_USB0D1_RX,
113 .addr = 0xA4D80120,
114 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
115 .mid_rid = 0x77,
116 }, {
117 .slave_id = SHDMA_SLAVE_USB1D0_TX,
118 .addr = 0xA4D90100,
119 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
120 .mid_rid = 0xab,
121 }, {
122 .slave_id = SHDMA_SLAVE_USB1D0_RX,
123 .addr = 0xA4D90100,
124 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
125 .mid_rid = 0xab,
126 }, {
127 .slave_id = SHDMA_SLAVE_USB1D1_TX,
128 .addr = 0xA4D90120,
129 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
130 .mid_rid = 0xaf,
131 }, {
132 .slave_id = SHDMA_SLAVE_USB1D1_RX,
133 .addr = 0xA4D90120,
134 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
135 .mid_rid = 0xaf,
136 }, {
137 .slave_id = SHDMA_SLAVE_SDHI0_TX,
138 .addr = 0x04ce0030,
139 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
140 .mid_rid = 0xc1,
141 }, {
142 .slave_id = SHDMA_SLAVE_SDHI0_RX,
143 .addr = 0x04ce0030,
144 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
145 .mid_rid = 0xc2,
146 }, {
147 .slave_id = SHDMA_SLAVE_SDHI1_TX,
148 .addr = 0x04cf0030,
149 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
150 .mid_rid = 0xc9,
151 }, {
152 .slave_id = SHDMA_SLAVE_SDHI1_RX,
153 .addr = 0x04cf0030,
154 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
155 .mid_rid = 0xca,
156 },
157};
158
159static const struct sh_dmae_channel sh7724_dmae_channels[] = {
160 {
161 .offset = 0,
162 .dmars = 0,
163 .dmars_bit = 0,
164 }, {
165 .offset = 0x10,
166 .dmars = 0,
167 .dmars_bit = 8,
168 }, {
169 .offset = 0x20,
170 .dmars = 4,
171 .dmars_bit = 0,
172 }, {
173 .offset = 0x30,
174 .dmars = 4,
175 .dmars_bit = 8,
176 }, {
177 .offset = 0x50,
178 .dmars = 8,
179 .dmars_bit = 0,
180 }, {
181 .offset = 0x60,
182 .dmars = 8,
183 .dmars_bit = 8,
184 }
185};
186
187static const unsigned int ts_shift[] = TS_SHIFT;
188
189static struct sh_dmae_pdata dma_platform_data = {
190 .slave = sh7724_dmae_slaves,
191 .slave_num = ARRAY_SIZE(sh7724_dmae_slaves),
192 .channel = sh7724_dmae_channels,
193 .channel_num = ARRAY_SIZE(sh7724_dmae_channels),
194 .ts_low_shift = CHCR_TS_LOW_SHIFT,
195 .ts_low_mask = CHCR_TS_LOW_MASK,
196 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
197 .ts_high_mask = CHCR_TS_HIGH_MASK,
198 .ts_shift = ts_shift,
199 .ts_shift_num = ARRAY_SIZE(ts_shift),
200 .dmaor_init = DMAOR_INIT,
201};
202
203
204static struct resource sh7724_dmae0_resources[] = {
205 {
206
207 .start = 0xfe008020,
208 .end = 0xfe00808f,
209 .flags = IORESOURCE_MEM,
210 },
211 {
212
213 .start = 0xfe009000,
214 .end = 0xfe00900b,
215 .flags = IORESOURCE_MEM,
216 },
217 {
218 .name = "error_irq",
219 .start = evt2irq(0xbc0),
220 .end = evt2irq(0xbc0),
221 .flags = IORESOURCE_IRQ,
222 },
223 {
224
225 .start = evt2irq(0x800),
226 .end = evt2irq(0x860),
227 .flags = IORESOURCE_IRQ,
228 },
229 {
230
231 .start = evt2irq(0xb80),
232 .end = evt2irq(0xba0),
233 .flags = IORESOURCE_IRQ,
234 },
235};
236
237
238static struct resource sh7724_dmae1_resources[] = {
239 {
240
241 .start = 0xfdc08020,
242 .end = 0xfdc0808f,
243 .flags = IORESOURCE_MEM,
244 },
245 {
246
247 .start = 0xfdc09000,
248 .end = 0xfdc0900b,
249 .flags = IORESOURCE_MEM,
250 },
251 {
252 .name = "error_irq",
253 .start = evt2irq(0xb40),
254 .end = evt2irq(0xb40),
255 .flags = IORESOURCE_IRQ,
256 },
257 {
258
259 .start = evt2irq(0x700),
260 .end = evt2irq(0x760),
261 .flags = IORESOURCE_IRQ,
262 },
263 {
264
265 .start = evt2irq(0xb00),
266 .end = evt2irq(0xb20),
267 .flags = IORESOURCE_IRQ,
268 },
269};
270
271static struct platform_device dma0_device = {
272 .name = "sh-dma-engine",
273 .id = 0,
274 .resource = sh7724_dmae0_resources,
275 .num_resources = ARRAY_SIZE(sh7724_dmae0_resources),
276 .dev = {
277 .platform_data = &dma_platform_data,
278 },
279};
280
281static struct platform_device dma1_device = {
282 .name = "sh-dma-engine",
283 .id = 1,
284 .resource = sh7724_dmae1_resources,
285 .num_resources = ARRAY_SIZE(sh7724_dmae1_resources),
286 .dev = {
287 .platform_data = &dma_platform_data,
288 },
289};
290
291
292static struct plat_sci_port scif0_platform_data = {
293 .mapbase = 0xffe00000,
294 .port_reg = SCIx_NOT_SUPPORTED,
295 .flags = UPF_BOOT_AUTOCONF,
296 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
297 .scbrr_algo_id = SCBRR_ALGO_2,
298 .type = PORT_SCIF,
299 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)),
300 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
301};
302
303static struct platform_device scif0_device = {
304 .name = "sh-sci",
305 .id = 0,
306 .dev = {
307 .platform_data = &scif0_platform_data,
308 },
309};
310
311static struct plat_sci_port scif1_platform_data = {
312 .mapbase = 0xffe10000,
313 .port_reg = SCIx_NOT_SUPPORTED,
314 .flags = UPF_BOOT_AUTOCONF,
315 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
316 .scbrr_algo_id = SCBRR_ALGO_2,
317 .type = PORT_SCIF,
318 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)),
319 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
320};
321
322static struct platform_device scif1_device = {
323 .name = "sh-sci",
324 .id = 1,
325 .dev = {
326 .platform_data = &scif1_platform_data,
327 },
328};
329
330static struct plat_sci_port scif2_platform_data = {
331 .mapbase = 0xffe20000,
332 .port_reg = SCIx_NOT_SUPPORTED,
333 .flags = UPF_BOOT_AUTOCONF,
334 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
335 .scbrr_algo_id = SCBRR_ALGO_2,
336 .type = PORT_SCIF,
337 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)),
338 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
339};
340
341static struct platform_device scif2_device = {
342 .name = "sh-sci",
343 .id = 2,
344 .dev = {
345 .platform_data = &scif2_platform_data,
346 },
347};
348
349static struct plat_sci_port scif3_platform_data = {
350 .mapbase = 0xa4e30000,
351 .port_reg = SCIx_NOT_SUPPORTED,
352 .flags = UPF_BOOT_AUTOCONF,
353 .scscr = SCSCR_RE | SCSCR_TE,
354 .scbrr_algo_id = SCBRR_ALGO_3,
355 .type = PORT_SCIFA,
356 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)),
357};
358
359static struct platform_device scif3_device = {
360 .name = "sh-sci",
361 .id = 3,
362 .dev = {
363 .platform_data = &scif3_platform_data,
364 },
365};
366
367static struct plat_sci_port scif4_platform_data = {
368 .mapbase = 0xa4e40000,
369 .port_reg = SCIx_NOT_SUPPORTED,
370 .flags = UPF_BOOT_AUTOCONF,
371 .scscr = SCSCR_RE | SCSCR_TE,
372 .scbrr_algo_id = SCBRR_ALGO_3,
373 .type = PORT_SCIFA,
374 .irqs = SCIx_IRQ_MUXED(evt2irq(0xd00)),
375};
376
377static struct platform_device scif4_device = {
378 .name = "sh-sci",
379 .id = 4,
380 .dev = {
381 .platform_data = &scif4_platform_data,
382 },
383};
384
385static struct plat_sci_port scif5_platform_data = {
386 .mapbase = 0xa4e50000,
387 .port_reg = SCIx_NOT_SUPPORTED,
388 .flags = UPF_BOOT_AUTOCONF,
389 .scscr = SCSCR_RE | SCSCR_TE,
390 .scbrr_algo_id = SCBRR_ALGO_3,
391 .type = PORT_SCIFA,
392 .irqs = SCIx_IRQ_MUXED(evt2irq(0xfa0)),
393};
394
395static struct platform_device scif5_device = {
396 .name = "sh-sci",
397 .id = 5,
398 .dev = {
399 .platform_data = &scif5_platform_data,
400 },
401};
402
403
404static struct resource rtc_resources[] = {
405 [0] = {
406 .start = 0xa465fec0,
407 .end = 0xa465fec0 + 0x58 - 1,
408 .flags = IORESOURCE_IO,
409 },
410 [1] = {
411
412 .start = evt2irq(0xaa0),
413 .flags = IORESOURCE_IRQ,
414 },
415 [2] = {
416
417 .start = evt2irq(0xac0),
418 .flags = IORESOURCE_IRQ,
419 },
420 [3] = {
421
422 .start = evt2irq(0xa80),
423 .flags = IORESOURCE_IRQ,
424 },
425};
426
427static struct platform_device rtc_device = {
428 .name = "sh-rtc",
429 .id = -1,
430 .num_resources = ARRAY_SIZE(rtc_resources),
431 .resource = rtc_resources,
432};
433
434
435static struct resource iic0_resources[] = {
436 [0] = {
437 .name = "IIC0",
438 .start = 0x04470000,
439 .end = 0x04470018 - 1,
440 .flags = IORESOURCE_MEM,
441 },
442 [1] = {
443 .start = evt2irq(0xe00),
444 .end = evt2irq(0xe60),
445 .flags = IORESOURCE_IRQ,
446 },
447};
448
449static struct platform_device iic0_device = {
450 .name = "i2c-sh_mobile",
451 .id = 0,
452 .num_resources = ARRAY_SIZE(iic0_resources),
453 .resource = iic0_resources,
454};
455
456
457static struct resource iic1_resources[] = {
458 [0] = {
459 .name = "IIC1",
460 .start = 0x04750000,
461 .end = 0x04750018 - 1,
462 .flags = IORESOURCE_MEM,
463 },
464 [1] = {
465 .start = evt2irq(0xd80),
466 .end = evt2irq(0xde0),
467 .flags = IORESOURCE_IRQ,
468 },
469};
470
471static struct platform_device iic1_device = {
472 .name = "i2c-sh_mobile",
473 .id = 1,
474 .num_resources = ARRAY_SIZE(iic1_resources),
475 .resource = iic1_resources,
476};
477
478
479static struct uio_info vpu_platform_data = {
480 .name = "VPU5F",
481 .version = "0",
482 .irq = evt2irq(0x980),
483};
484
485static struct resource vpu_resources[] = {
486 [0] = {
487 .name = "VPU",
488 .start = 0xfe900000,
489 .end = 0xfe902807,
490 .flags = IORESOURCE_MEM,
491 },
492 [1] = {
493
494 },
495};
496
497static struct platform_device vpu_device = {
498 .name = "uio_pdrv_genirq",
499 .id = 0,
500 .dev = {
501 .platform_data = &vpu_platform_data,
502 },
503 .resource = vpu_resources,
504 .num_resources = ARRAY_SIZE(vpu_resources),
505};
506
507
508static struct uio_info veu0_platform_data = {
509 .name = "VEU3F0",
510 .version = "0",
511 .irq = evt2irq(0xc60),
512};
513
514static struct resource veu0_resources[] = {
515 [0] = {
516 .name = "VEU3F0",
517 .start = 0xfe920000,
518 .end = 0xfe9200cb,
519 .flags = IORESOURCE_MEM,
520 },
521 [1] = {
522
523 },
524};
525
526static struct platform_device veu0_device = {
527 .name = "uio_pdrv_genirq",
528 .id = 1,
529 .dev = {
530 .platform_data = &veu0_platform_data,
531 },
532 .resource = veu0_resources,
533 .num_resources = ARRAY_SIZE(veu0_resources),
534};
535
536
537static struct uio_info veu1_platform_data = {
538 .name = "VEU3F1",
539 .version = "0",
540 .irq = evt2irq(0x8c0),
541};
542
543static struct resource veu1_resources[] = {
544 [0] = {
545 .name = "VEU3F1",
546 .start = 0xfe924000,
547 .end = 0xfe9240cb,
548 .flags = IORESOURCE_MEM,
549 },
550 [1] = {
551
552 },
553};
554
555static struct platform_device veu1_device = {
556 .name = "uio_pdrv_genirq",
557 .id = 2,
558 .dev = {
559 .platform_data = &veu1_platform_data,
560 },
561 .resource = veu1_resources,
562 .num_resources = ARRAY_SIZE(veu1_resources),
563};
564
565
566static struct uio_info beu0_platform_data = {
567 .name = "BEU0",
568 .version = "0",
569 .irq = evt2irq(0x8A0),
570};
571
572static struct resource beu0_resources[] = {
573 [0] = {
574 .name = "BEU0",
575 .start = 0xfe930000,
576 .end = 0xfe933400,
577 .flags = IORESOURCE_MEM,
578 },
579 [1] = {
580
581 },
582};
583
584static struct platform_device beu0_device = {
585 .name = "uio_pdrv_genirq",
586 .id = 6,
587 .dev = {
588 .platform_data = &beu0_platform_data,
589 },
590 .resource = beu0_resources,
591 .num_resources = ARRAY_SIZE(beu0_resources),
592};
593
594
595static struct uio_info beu1_platform_data = {
596 .name = "BEU1",
597 .version = "0",
598 .irq = evt2irq(0xA00),
599};
600
601static struct resource beu1_resources[] = {
602 [0] = {
603 .name = "BEU1",
604 .start = 0xfe940000,
605 .end = 0xfe943400,
606 .flags = IORESOURCE_MEM,
607 },
608 [1] = {
609
610 },
611};
612
613static struct platform_device beu1_device = {
614 .name = "uio_pdrv_genirq",
615 .id = 7,
616 .dev = {
617 .platform_data = &beu1_platform_data,
618 },
619 .resource = beu1_resources,
620 .num_resources = ARRAY_SIZE(beu1_resources),
621};
622
623static struct sh_timer_config cmt_platform_data = {
624 .channel_offset = 0x60,
625 .timer_bit = 5,
626 .clockevent_rating = 125,
627 .clocksource_rating = 200,
628};
629
630static struct resource cmt_resources[] = {
631 [0] = {
632 .start = 0x044a0060,
633 .end = 0x044a006b,
634 .flags = IORESOURCE_MEM,
635 },
636 [1] = {
637 .start = evt2irq(0xf00),
638 .flags = IORESOURCE_IRQ,
639 },
640};
641
642static struct platform_device cmt_device = {
643 .name = "sh_cmt",
644 .id = 0,
645 .dev = {
646 .platform_data = &cmt_platform_data,
647 },
648 .resource = cmt_resources,
649 .num_resources = ARRAY_SIZE(cmt_resources),
650};
651
652static struct sh_timer_config tmu0_platform_data = {
653 .channel_offset = 0x04,
654 .timer_bit = 0,
655 .clockevent_rating = 200,
656};
657
658static struct resource tmu0_resources[] = {
659 [0] = {
660 .start = 0xffd80008,
661 .end = 0xffd80013,
662 .flags = IORESOURCE_MEM,
663 },
664 [1] = {
665 .start = evt2irq(0x400),
666 .flags = IORESOURCE_IRQ,
667 },
668};
669
670static struct platform_device tmu0_device = {
671 .name = "sh_tmu",
672 .id = 0,
673 .dev = {
674 .platform_data = &tmu0_platform_data,
675 },
676 .resource = tmu0_resources,
677 .num_resources = ARRAY_SIZE(tmu0_resources),
678};
679
680static struct sh_timer_config tmu1_platform_data = {
681 .channel_offset = 0x10,
682 .timer_bit = 1,
683 .clocksource_rating = 200,
684};
685
686static struct resource tmu1_resources[] = {
687 [0] = {
688 .start = 0xffd80014,
689 .end = 0xffd8001f,
690 .flags = IORESOURCE_MEM,
691 },
692 [1] = {
693 .start = evt2irq(0x420),
694 .flags = IORESOURCE_IRQ,
695 },
696};
697
698static struct platform_device tmu1_device = {
699 .name = "sh_tmu",
700 .id = 1,
701 .dev = {
702 .platform_data = &tmu1_platform_data,
703 },
704 .resource = tmu1_resources,
705 .num_resources = ARRAY_SIZE(tmu1_resources),
706};
707
708static struct sh_timer_config tmu2_platform_data = {
709 .channel_offset = 0x1c,
710 .timer_bit = 2,
711};
712
713static struct resource tmu2_resources[] = {
714 [0] = {
715 .start = 0xffd80020,
716 .end = 0xffd8002b,
717 .flags = IORESOURCE_MEM,
718 },
719 [1] = {
720 .start = evt2irq(0x440),
721 .flags = IORESOURCE_IRQ,
722 },
723};
724
725static struct platform_device tmu2_device = {
726 .name = "sh_tmu",
727 .id = 2,
728 .dev = {
729 .platform_data = &tmu2_platform_data,
730 },
731 .resource = tmu2_resources,
732 .num_resources = ARRAY_SIZE(tmu2_resources),
733};
734
735
736static struct sh_timer_config tmu3_platform_data = {
737 .channel_offset = 0x04,
738 .timer_bit = 0,
739};
740
741static struct resource tmu3_resources[] = {
742 [0] = {
743 .start = 0xffd90008,
744 .end = 0xffd90013,
745 .flags = IORESOURCE_MEM,
746 },
747 [1] = {
748 .start = evt2irq(0x920),
749 .flags = IORESOURCE_IRQ,
750 },
751};
752
753static struct platform_device tmu3_device = {
754 .name = "sh_tmu",
755 .id = 3,
756 .dev = {
757 .platform_data = &tmu3_platform_data,
758 },
759 .resource = tmu3_resources,
760 .num_resources = ARRAY_SIZE(tmu3_resources),
761};
762
763static struct sh_timer_config tmu4_platform_data = {
764 .channel_offset = 0x10,
765 .timer_bit = 1,
766};
767
768static struct resource tmu4_resources[] = {
769 [0] = {
770 .start = 0xffd90014,
771 .end = 0xffd9001f,
772 .flags = IORESOURCE_MEM,
773 },
774 [1] = {
775 .start = evt2irq(0x940),
776 .flags = IORESOURCE_IRQ,
777 },
778};
779
780static struct platform_device tmu4_device = {
781 .name = "sh_tmu",
782 .id = 4,
783 .dev = {
784 .platform_data = &tmu4_platform_data,
785 },
786 .resource = tmu4_resources,
787 .num_resources = ARRAY_SIZE(tmu4_resources),
788};
789
790static struct sh_timer_config tmu5_platform_data = {
791 .channel_offset = 0x1c,
792 .timer_bit = 2,
793};
794
795static struct resource tmu5_resources[] = {
796 [0] = {
797 .start = 0xffd90020,
798 .end = 0xffd9002b,
799 .flags = IORESOURCE_MEM,
800 },
801 [1] = {
802 .start = evt2irq(0x920),
803 .flags = IORESOURCE_IRQ,
804 },
805};
806
807static struct platform_device tmu5_device = {
808 .name = "sh_tmu",
809 .id = 5,
810 .dev = {
811 .platform_data = &tmu5_platform_data,
812 },
813 .resource = tmu5_resources,
814 .num_resources = ARRAY_SIZE(tmu5_resources),
815};
816
817
818static struct uio_info jpu_platform_data = {
819 .name = "JPU",
820 .version = "0",
821 .irq = evt2irq(0x560),
822};
823
824static struct resource jpu_resources[] = {
825 [0] = {
826 .name = "JPU",
827 .start = 0xfe980000,
828 .end = 0xfe9902d3,
829 .flags = IORESOURCE_MEM,
830 },
831 [1] = {
832
833 },
834};
835
836static struct platform_device jpu_device = {
837 .name = "uio_pdrv_genirq",
838 .id = 3,
839 .dev = {
840 .platform_data = &jpu_platform_data,
841 },
842 .resource = jpu_resources,
843 .num_resources = ARRAY_SIZE(jpu_resources),
844};
845
846
847static struct uio_info spu0_platform_data = {
848 .name = "SPU2DSP0",
849 .version = "0",
850 .irq = evt2irq(0xcc0),
851};
852
853static struct resource spu0_resources[] = {
854 [0] = {
855 .name = "SPU2DSP0",
856 .start = 0xFE200000,
857 .end = 0xFE2FFFFF,
858 .flags = IORESOURCE_MEM,
859 },
860 [1] = {
861
862 },
863};
864
865static struct platform_device spu0_device = {
866 .name = "uio_pdrv_genirq",
867 .id = 4,
868 .dev = {
869 .platform_data = &spu0_platform_data,
870 },
871 .resource = spu0_resources,
872 .num_resources = ARRAY_SIZE(spu0_resources),
873};
874
875
876static struct uio_info spu1_platform_data = {
877 .name = "SPU2DSP1",
878 .version = "0",
879 .irq = evt2irq(0xce0),
880};
881
882static struct resource spu1_resources[] = {
883 [0] = {
884 .name = "SPU2DSP1",
885 .start = 0xFE300000,
886 .end = 0xFE3FFFFF,
887 .flags = IORESOURCE_MEM,
888 },
889 [1] = {
890
891 },
892};
893
894static struct platform_device spu1_device = {
895 .name = "uio_pdrv_genirq",
896 .id = 5,
897 .dev = {
898 .platform_data = &spu1_platform_data,
899 },
900 .resource = spu1_resources,
901 .num_resources = ARRAY_SIZE(spu1_resources),
902};
903
904static struct platform_device *sh7724_devices[] __initdata = {
905 &scif0_device,
906 &scif1_device,
907 &scif2_device,
908 &scif3_device,
909 &scif4_device,
910 &scif5_device,
911 &cmt_device,
912 &tmu0_device,
913 &tmu1_device,
914 &tmu2_device,
915 &tmu3_device,
916 &tmu4_device,
917 &tmu5_device,
918 &dma0_device,
919 &dma1_device,
920 &rtc_device,
921 &iic0_device,
922 &iic1_device,
923 &vpu_device,
924 &veu0_device,
925 &veu1_device,
926 &beu0_device,
927 &beu1_device,
928 &jpu_device,
929 &spu0_device,
930 &spu1_device,
931};
932
933static int __init sh7724_devices_setup(void)
934{
935 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
936 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
937 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
938 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
939 platform_resource_setup_memory(&spu0_device, "spu0", 2 << 20);
940 platform_resource_setup_memory(&spu1_device, "spu1", 2 << 20);
941
942 return platform_add_devices(sh7724_devices,
943 ARRAY_SIZE(sh7724_devices));
944}
945arch_initcall(sh7724_devices_setup);
946
947static struct platform_device *sh7724_early_devices[] __initdata = {
948 &scif0_device,
949 &scif1_device,
950 &scif2_device,
951 &scif3_device,
952 &scif4_device,
953 &scif5_device,
954 &cmt_device,
955 &tmu0_device,
956 &tmu1_device,
957 &tmu2_device,
958 &tmu3_device,
959 &tmu4_device,
960 &tmu5_device,
961};
962
963void __init plat_early_device_setup(void)
964{
965 early_platform_add_devices(sh7724_early_devices,
966 ARRAY_SIZE(sh7724_early_devices));
967}
968
969#define RAMCR_CACHE_L2FC 0x0002
970#define RAMCR_CACHE_L2E 0x0001
971#define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
972
973void l2_cache_init(void)
974{
975
976 __raw_writel(L2_CACHE_ENABLE, RAMCR);
977}
978
979enum {
980 UNUSED = 0,
981 ENABLED,
982 DISABLED,
983
984
985 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
986 HUDI,
987 DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3,
988 _2DG_TRI, _2DG_INI, _2DG_CEI,
989 DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3,
990 VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU,
991 SCIFA3,
992 VPU,
993 TPU,
994 CEU1,
995 BEU1,
996 USB0, USB1,
997 ATAPI,
998 RTC_ATI, RTC_PRI, RTC_CUI,
999 DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR,
1000 DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR,
1001 KEYSC,
1002 SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,
1003 VEU0,
1004 MSIOF_MSIOFI0, MSIOF_MSIOFI1,
1005 SPU_SPUI0, SPU_SPUI1,
1006 SCIFA4,
1007 ICB,
1008 ETHI,
1009 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
1010 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
1011 CMT,
1012 TSIF,
1013 FSI,
1014 SCIFA5,
1015 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
1016 IRDA,
1017 JPU,
1018 _2DDMAC,
1019 MMC_MMC2I, MMC_MMC3I,
1020 LCDC,
1021 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
1022
1023
1024 DMAC1A, _2DG, DMAC0A, VIO, USB, RTC,
1025 DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF,
1026};
1027
1028static struct intc_vect vectors[] __initdata = {
1029 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
1030 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
1031 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
1032 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
1033
1034 INTC_VECT(DMAC1A_DEI0, 0x700),
1035 INTC_VECT(DMAC1A_DEI1, 0x720),
1036 INTC_VECT(DMAC1A_DEI2, 0x740),
1037 INTC_VECT(DMAC1A_DEI3, 0x760),
1038
1039 INTC_VECT(_2DG_TRI, 0x780),
1040 INTC_VECT(_2DG_INI, 0x7A0),
1041 INTC_VECT(_2DG_CEI, 0x7C0),
1042
1043 INTC_VECT(DMAC0A_DEI0, 0x800),
1044 INTC_VECT(DMAC0A_DEI1, 0x820),
1045 INTC_VECT(DMAC0A_DEI2, 0x840),
1046 INTC_VECT(DMAC0A_DEI3, 0x860),
1047
1048 INTC_VECT(VIO_CEU0, 0x880),
1049 INTC_VECT(VIO_BEU0, 0x8A0),
1050 INTC_VECT(VIO_VEU1, 0x8C0),
1051 INTC_VECT(VIO_VOU, 0x8E0),
1052
1053 INTC_VECT(SCIFA3, 0x900),
1054 INTC_VECT(VPU, 0x980),
1055 INTC_VECT(TPU, 0x9A0),
1056 INTC_VECT(CEU1, 0x9E0),
1057 INTC_VECT(BEU1, 0xA00),
1058 INTC_VECT(USB0, 0xA20),
1059 INTC_VECT(USB1, 0xA40),
1060 INTC_VECT(ATAPI, 0xA60),
1061
1062 INTC_VECT(RTC_ATI, 0xA80),
1063 INTC_VECT(RTC_PRI, 0xAA0),
1064 INTC_VECT(RTC_CUI, 0xAC0),
1065
1066 INTC_VECT(DMAC1B_DEI4, 0xB00),
1067 INTC_VECT(DMAC1B_DEI5, 0xB20),
1068 INTC_VECT(DMAC1B_DADERR, 0xB40),
1069
1070 INTC_VECT(DMAC0B_DEI4, 0xB80),
1071 INTC_VECT(DMAC0B_DEI5, 0xBA0),
1072 INTC_VECT(DMAC0B_DADERR, 0xBC0),
1073
1074 INTC_VECT(KEYSC, 0xBE0),
1075 INTC_VECT(SCIF_SCIF0, 0xC00),
1076 INTC_VECT(SCIF_SCIF1, 0xC20),
1077 INTC_VECT(SCIF_SCIF2, 0xC40),
1078 INTC_VECT(VEU0, 0xC60),
1079 INTC_VECT(MSIOF_MSIOFI0, 0xC80),
1080 INTC_VECT(MSIOF_MSIOFI1, 0xCA0),
1081 INTC_VECT(SPU_SPUI0, 0xCC0),
1082 INTC_VECT(SPU_SPUI1, 0xCE0),
1083 INTC_VECT(SCIFA4, 0xD00),
1084
1085 INTC_VECT(ICB, 0xD20),
1086 INTC_VECT(ETHI, 0xD60),
1087
1088 INTC_VECT(I2C1_ALI, 0xD80),
1089 INTC_VECT(I2C1_TACKI, 0xDA0),
1090 INTC_VECT(I2C1_WAITI, 0xDC0),
1091 INTC_VECT(I2C1_DTEI, 0xDE0),
1092
1093 INTC_VECT(I2C0_ALI, 0xE00),
1094 INTC_VECT(I2C0_TACKI, 0xE20),
1095 INTC_VECT(I2C0_WAITI, 0xE40),
1096 INTC_VECT(I2C0_DTEI, 0xE60),
1097
1098 INTC_VECT(SDHI0, 0xE80),
1099 INTC_VECT(SDHI0, 0xEA0),
1100 INTC_VECT(SDHI0, 0xEC0),
1101 INTC_VECT(SDHI0, 0xEE0),
1102
1103 INTC_VECT(CMT, 0xF00),
1104 INTC_VECT(TSIF, 0xF20),
1105 INTC_VECT(FSI, 0xF80),
1106 INTC_VECT(SCIFA5, 0xFA0),
1107
1108 INTC_VECT(TMU0_TUNI0, 0x400),
1109 INTC_VECT(TMU0_TUNI1, 0x420),
1110 INTC_VECT(TMU0_TUNI2, 0x440),
1111
1112 INTC_VECT(IRDA, 0x480),
1113
1114 INTC_VECT(SDHI1, 0x4E0),
1115 INTC_VECT(SDHI1, 0x500),
1116 INTC_VECT(SDHI1, 0x520),
1117
1118 INTC_VECT(JPU, 0x560),
1119 INTC_VECT(_2DDMAC, 0x4A0),
1120
1121 INTC_VECT(MMC_MMC2I, 0x5A0),
1122 INTC_VECT(MMC_MMC3I, 0x5C0),
1123
1124 INTC_VECT(LCDC, 0xF40),
1125
1126 INTC_VECT(TMU1_TUNI0, 0x920),
1127 INTC_VECT(TMU1_TUNI1, 0x940),
1128 INTC_VECT(TMU1_TUNI2, 0x960),
1129};
1130
1131static struct intc_group groups[] __initdata = {
1132 INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3),
1133 INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI),
1134 INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3),
1135 INTC_GROUP(VIO, VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU),
1136 INTC_GROUP(USB, USB0, USB1),
1137 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
1138 INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR),
1139 INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
1140 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
1141 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
1142 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
1143 INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I),
1144};
1145
1146static struct intc_mask_reg mask_registers[] __initdata = {
1147 { 0xa4080080, 0xa40800c0, 8,
1148 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
1149 0, ENABLED, ENABLED, ENABLED } },
1150 { 0xa4080084, 0xa40800c4, 8,
1151 { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0,
1152 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
1153 { 0xa4080088, 0xa40800c8, 8,
1154 { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } },
1155 { 0xa408008c, 0xa40800cc, 8,
1156 { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0,
1157 SPU_SPUI1, SPU_SPUI0, BEU1, IRDA } },
1158 { 0xa4080090, 0xa40800d0, 8,
1159 { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0,
1160 JPU, 0, 0, LCDC } },
1161 { 0xa4080094, 0xa40800d4, 8,
1162 { KEYSC, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4,
1163 VEU0, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } },
1164 { 0xa4080098, 0xa40800d8, 8,
1165 { 0, 0, ICB, SCIFA4,
1166 CEU1, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } },
1167 { 0xa408009c, 0xa40800dc, 8,
1168 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
1169 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
1170 { 0xa40800a0, 0xa40800e0, 8,
1171 { DISABLED, ENABLED, ENABLED, ENABLED,
1172 0, 0, SCIFA5, FSI } },
1173 { 0xa40800a4, 0xa40800e4, 8,
1174 { 0, 0, 0, CMT, 0, USB1, USB0, 0 } },
1175 { 0xa40800a8, 0xa40800e8, 8,
1176 { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4,
1177 0, RTC_CUI, RTC_PRI, RTC_ATI } },
1178 { 0xa40800ac, 0xa40800ec, 8,
1179 { 0, _2DG_CEI, _2DG_INI, _2DG_TRI,
1180 0, TPU, 0, TSIF } },
1181 { 0xa40800b0, 0xa40800f0, 8,
1182 { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } },
1183 { 0xa4140044, 0xa4140064, 8,
1184 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1185};
1186
1187static struct intc_prio_reg prio_registers[] __initdata = {
1188 { 0xa4080000, 0, 16, 4, { TMU0_TUNI0, TMU0_TUNI1,
1189 TMU0_TUNI2, IRDA } },
1190 { 0xa4080004, 0, 16, 4, { JPU, LCDC, DMAC1A, BEU1 } },
1191 { 0xa4080008, 0, 16, 4, { TMU1_TUNI0, TMU1_TUNI1,
1192 TMU1_TUNI2, SPU } },
1193 { 0xa408000c, 0, 16, 4, { 0, MMCIF, 0, ATAPI } },
1194 { 0xa4080010, 0, 16, 4, { DMAC0A, VIO, SCIFA3, VPU } },
1195 { 0xa4080014, 0, 16, 4, { KEYSC, DMAC0B, USB, CMT } },
1196 { 0xa4080018, 0, 16, 4, { SCIF_SCIF0, SCIF_SCIF1,
1197 SCIF_SCIF2, VEU0 } },
1198 { 0xa408001c, 0, 16, 4, { MSIOF_MSIOFI0, MSIOF_MSIOFI1,
1199 I2C1, I2C0 } },
1200 { 0xa4080020, 0, 16, 4, { SCIFA4, ICB, TSIF, _2DG } },
1201 { 0xa4080024, 0, 16, 4, { CEU1, ETHI, FSI, SDHI1 } },
1202 { 0xa4080028, 0, 16, 4, { RTC, DMAC1B, 0, SDHI0 } },
1203 { 0xa408002c, 0, 16, 4, { SCIFA5, 0, TPU, _2DDMAC } },
1204 { 0xa4140010, 0, 32, 4,
1205 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1206};
1207
1208static struct intc_sense_reg sense_registers[] __initdata = {
1209 { 0xa414001c, 16, 2,
1210 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1211};
1212
1213static struct intc_mask_reg ack_registers[] __initdata = {
1214 { 0xa4140024, 0, 8,
1215 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1216};
1217
1218static struct intc_desc intc_desc __initdata = {
1219 .name = "sh7724",
1220 .force_enable = ENABLED,
1221 .force_disable = DISABLED,
1222 .hw = INTC_HW_DESC(vectors, groups, mask_registers,
1223 prio_registers, sense_registers, ack_registers),
1224};
1225
1226void __init plat_irq_setup(void)
1227{
1228 register_intc_controller(&intc_desc);
1229}
1230
1231static struct {
1232
1233 unsigned long mmselr;
1234 unsigned long cs0bcr;
1235 unsigned long cs4bcr;
1236 unsigned long cs5abcr;
1237 unsigned long cs5bbcr;
1238 unsigned long cs6abcr;
1239 unsigned long cs6bbcr;
1240 unsigned long cs4wcr;
1241 unsigned long cs5awcr;
1242 unsigned long cs5bwcr;
1243 unsigned long cs6awcr;
1244 unsigned long cs6bwcr;
1245
1246 unsigned short ipra;
1247 unsigned short iprb;
1248 unsigned short iprc;
1249 unsigned short iprd;
1250 unsigned short ipre;
1251 unsigned short iprf;
1252 unsigned short iprg;
1253 unsigned short iprh;
1254 unsigned short ipri;
1255 unsigned short iprj;
1256 unsigned short iprk;
1257 unsigned short iprl;
1258 unsigned char imr0;
1259 unsigned char imr1;
1260 unsigned char imr2;
1261 unsigned char imr3;
1262 unsigned char imr4;
1263 unsigned char imr5;
1264 unsigned char imr6;
1265 unsigned char imr7;
1266 unsigned char imr8;
1267 unsigned char imr9;
1268 unsigned char imr10;
1269 unsigned char imr11;
1270 unsigned char imr12;
1271
1272 unsigned short rwtcnt;
1273 unsigned short rwtcsr;
1274
1275 unsigned long irdaclk;
1276 unsigned long spuclk;
1277} sh7724_rstandby_state;
1278
1279static int sh7724_pre_sleep_notifier_call(struct notifier_block *nb,
1280 unsigned long flags, void *unused)
1281{
1282 if (!(flags & SUSP_SH_RSTANDBY))
1283 return NOTIFY_DONE;
1284
1285
1286 sh7724_rstandby_state.mmselr = __raw_readl(0xff800020);
1287 sh7724_rstandby_state.mmselr |= 0xa5a50000;
1288 sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004);
1289 sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010);
1290 sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014);
1291 sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018);
1292 sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c);
1293 sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020);
1294 sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030);
1295 sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034);
1296 sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038);
1297 sh7724_rstandby_state.cs6awcr = __raw_readl(0xfec1003c);
1298 sh7724_rstandby_state.cs6bwcr = __raw_readl(0xfec10040);
1299
1300
1301 sh7724_rstandby_state.ipra = __raw_readw(0xa4080000);
1302 sh7724_rstandby_state.iprb = __raw_readw(0xa4080004);
1303 sh7724_rstandby_state.iprc = __raw_readw(0xa4080008);
1304 sh7724_rstandby_state.iprd = __raw_readw(0xa408000c);
1305 sh7724_rstandby_state.ipre = __raw_readw(0xa4080010);
1306 sh7724_rstandby_state.iprf = __raw_readw(0xa4080014);
1307 sh7724_rstandby_state.iprg = __raw_readw(0xa4080018);
1308 sh7724_rstandby_state.iprh = __raw_readw(0xa408001c);
1309 sh7724_rstandby_state.ipri = __raw_readw(0xa4080020);
1310 sh7724_rstandby_state.iprj = __raw_readw(0xa4080024);
1311 sh7724_rstandby_state.iprk = __raw_readw(0xa4080028);
1312 sh7724_rstandby_state.iprl = __raw_readw(0xa408002c);
1313 sh7724_rstandby_state.imr0 = __raw_readb(0xa4080080);
1314 sh7724_rstandby_state.imr1 = __raw_readb(0xa4080084);
1315 sh7724_rstandby_state.imr2 = __raw_readb(0xa4080088);
1316 sh7724_rstandby_state.imr3 = __raw_readb(0xa408008c);
1317 sh7724_rstandby_state.imr4 = __raw_readb(0xa4080090);
1318 sh7724_rstandby_state.imr5 = __raw_readb(0xa4080094);
1319 sh7724_rstandby_state.imr6 = __raw_readb(0xa4080098);
1320 sh7724_rstandby_state.imr7 = __raw_readb(0xa408009c);
1321 sh7724_rstandby_state.imr8 = __raw_readb(0xa40800a0);
1322 sh7724_rstandby_state.imr9 = __raw_readb(0xa40800a4);
1323 sh7724_rstandby_state.imr10 = __raw_readb(0xa40800a8);
1324 sh7724_rstandby_state.imr11 = __raw_readb(0xa40800ac);
1325 sh7724_rstandby_state.imr12 = __raw_readb(0xa40800b0);
1326
1327
1328 sh7724_rstandby_state.rwtcnt = __raw_readb(0xa4520000);
1329 sh7724_rstandby_state.rwtcnt |= 0x5a00;
1330 sh7724_rstandby_state.rwtcsr = __raw_readb(0xa4520004);
1331 sh7724_rstandby_state.rwtcsr |= 0xa500;
1332 __raw_writew(sh7724_rstandby_state.rwtcsr & 0x07, 0xa4520004);
1333
1334
1335 sh7724_rstandby_state.irdaclk = __raw_readl(0xa4150018);
1336 sh7724_rstandby_state.spuclk = __raw_readl(0xa415003c);
1337
1338 return NOTIFY_DONE;
1339}
1340
1341static int sh7724_post_sleep_notifier_call(struct notifier_block *nb,
1342 unsigned long flags, void *unused)
1343{
1344 if (!(flags & SUSP_SH_RSTANDBY))
1345 return NOTIFY_DONE;
1346
1347
1348 __raw_writel(sh7724_rstandby_state.mmselr, 0xff800020);
1349 __raw_writel(sh7724_rstandby_state.cs0bcr, 0xfec10004);
1350 __raw_writel(sh7724_rstandby_state.cs4bcr, 0xfec10010);
1351 __raw_writel(sh7724_rstandby_state.cs5abcr, 0xfec10014);
1352 __raw_writel(sh7724_rstandby_state.cs5bbcr, 0xfec10018);
1353 __raw_writel(sh7724_rstandby_state.cs6abcr, 0xfec1001c);
1354 __raw_writel(sh7724_rstandby_state.cs6bbcr, 0xfec10020);
1355 __raw_writel(sh7724_rstandby_state.cs4wcr, 0xfec10030);
1356 __raw_writel(sh7724_rstandby_state.cs5awcr, 0xfec10034);
1357 __raw_writel(sh7724_rstandby_state.cs5bwcr, 0xfec10038);
1358 __raw_writel(sh7724_rstandby_state.cs6awcr, 0xfec1003c);
1359 __raw_writel(sh7724_rstandby_state.cs6bwcr, 0xfec10040);
1360
1361
1362 __raw_writew(sh7724_rstandby_state.ipra, 0xa4080000);
1363 __raw_writew(sh7724_rstandby_state.iprb, 0xa4080004);
1364 __raw_writew(sh7724_rstandby_state.iprc, 0xa4080008);
1365 __raw_writew(sh7724_rstandby_state.iprd, 0xa408000c);
1366 __raw_writew(sh7724_rstandby_state.ipre, 0xa4080010);
1367 __raw_writew(sh7724_rstandby_state.iprf, 0xa4080014);
1368 __raw_writew(sh7724_rstandby_state.iprg, 0xa4080018);
1369 __raw_writew(sh7724_rstandby_state.iprh, 0xa408001c);
1370 __raw_writew(sh7724_rstandby_state.ipri, 0xa4080020);
1371 __raw_writew(sh7724_rstandby_state.iprj, 0xa4080024);
1372 __raw_writew(sh7724_rstandby_state.iprk, 0xa4080028);
1373 __raw_writew(sh7724_rstandby_state.iprl, 0xa408002c);
1374 __raw_writeb(sh7724_rstandby_state.imr0, 0xa4080080);
1375 __raw_writeb(sh7724_rstandby_state.imr1, 0xa4080084);
1376 __raw_writeb(sh7724_rstandby_state.imr2, 0xa4080088);
1377 __raw_writeb(sh7724_rstandby_state.imr3, 0xa408008c);
1378 __raw_writeb(sh7724_rstandby_state.imr4, 0xa4080090);
1379 __raw_writeb(sh7724_rstandby_state.imr5, 0xa4080094);
1380 __raw_writeb(sh7724_rstandby_state.imr6, 0xa4080098);
1381 __raw_writeb(sh7724_rstandby_state.imr7, 0xa408009c);
1382 __raw_writeb(sh7724_rstandby_state.imr8, 0xa40800a0);
1383 __raw_writeb(sh7724_rstandby_state.imr9, 0xa40800a4);
1384 __raw_writeb(sh7724_rstandby_state.imr10, 0xa40800a8);
1385 __raw_writeb(sh7724_rstandby_state.imr11, 0xa40800ac);
1386 __raw_writeb(sh7724_rstandby_state.imr12, 0xa40800b0);
1387
1388
1389 __raw_writew(sh7724_rstandby_state.rwtcnt, 0xa4520000);
1390 __raw_writew(sh7724_rstandby_state.rwtcsr, 0xa4520004);
1391
1392
1393 __raw_writel(sh7724_rstandby_state.irdaclk, 0xa4150018);
1394 __raw_writel(sh7724_rstandby_state.spuclk, 0xa415003c);
1395
1396 return NOTIFY_DONE;
1397}
1398
1399static struct notifier_block sh7724_pre_sleep_notifier = {
1400 .notifier_call = sh7724_pre_sleep_notifier_call,
1401 .priority = SH_MOBILE_PRE(SH_MOBILE_SLEEP_CPU),
1402};
1403
1404static struct notifier_block sh7724_post_sleep_notifier = {
1405 .notifier_call = sh7724_post_sleep_notifier_call,
1406 .priority = SH_MOBILE_POST(SH_MOBILE_SLEEP_CPU),
1407};
1408
1409static int __init sh7724_sleep_setup(void)
1410{
1411 atomic_notifier_chain_register(&sh_mobile_pre_sleep_notifier_list,
1412 &sh7724_pre_sleep_notifier);
1413
1414 atomic_notifier_chain_register(&sh_mobile_post_sleep_notifier_list,
1415 &sh7724_post_sleep_notifier);
1416 return 0;
1417}
1418arch_initcall(sh7724_sleep_setup);
1419
1420
