1/* 2 * Copyright 2010 Tilera Corporation. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation, version 2. 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 11 * NON INFRINGEMENT. See the GNU General Public License for 12 * more details. 13 */ 14 15#ifndef _ASM_TILE_PROCESSOR_H 16#define _ASM_TILE_PROCESSOR_H 17 18#ifndef __ASSEMBLY__ 19 20/* 21 * NOTE: we don't include <linux/ptrace.h> or <linux/percpu.h> as one 22 * normally would, due to #include dependencies. 23 */ 24#include <linux/types.h> 25#include <asm/ptrace.h> 26#include <asm/percpu.h> 27 28#include <arch/chip.h> 29#include <arch/spr_def.h> 30 31struct task_struct; 32struct thread_struct; 33 34typedef struct { 35 unsigned long seg; 36} mm_segment_t; 37 38/* 39 * Default implementation of macro that returns current 40 * instruction pointer ("program counter"). 41 */ 42void *current_text_addr(void); 43 44#if CHIP_HAS_TILE_DMA() 45/* Capture the state of a suspended DMA. */ 46struct tile_dma_state { 47 int enabled; 48 unsigned long src; 49 unsigned long dest; 50 unsigned long strides; 51 unsigned long chunk_size; 52 unsigned long src_chunk; 53 unsigned long dest_chunk; 54 unsigned long byte; 55 unsigned long status; 56}; 57 58/* 59 * A mask of the DMA status register for selecting only the 'running' 60 * and 'done' bits. 61 */ 62#define DMA_STATUS_MASK \ 63 (SPR_DMA_STATUS__RUNNING_MASK | SPR_DMA_STATUS__DONE_MASK) 64#endif 65 66/* 67 * Track asynchronous TLB events (faults and access violations) 68 * that occur while we are in kernel mode from DMA or the SN processor. 69 */ 70struct async_tlb { 71 short fault_num; /* original fault number; 0 if none */ 72 char is_fault; /* was it a fault (vs an access violation) */ 73 char is_write; /* for fault: was it caused by a write? */ 74 unsigned long address; /* what address faulted? */ 75}; 76 77#ifdef CONFIG_HARDWALL 78struct hardwall_info; 79struct hardwall_task { 80 /* Which hardwall is this task tied to? (or NULL if none) */ 81 struct hardwall_info *info; 82 /* Chains this task into the list at info->task_head. */ 83 struct list_head list; 84}; 85#ifdef __tilepro__ 86#define HARDWALL_TYPES 1 /* udn */ 87#else 88#define HARDWALL_TYPES 3 /* udn, idn, and ipi */ 89#endif 90#endif 91 92struct thread_struct { 93 /* kernel stack pointer */ 94 unsigned long ksp; 95 /* kernel PC */ 96 unsigned long pc; 97 /* starting user stack pointer (for page migration) */ 98 unsigned long usp0; 99 /* pid of process that created this one */ 100 pid_t creator_pid; 101#if CHIP_HAS_TILE_DMA() 102 /* DMA info for suspended threads (byte == 0 means no DMA state) */ 103 struct tile_dma_state tile_dma_state; 104#endif 105 /* User EX_CONTEXT registers */ 106 unsigned long ex_context[2]; 107 /* User SYSTEM_SAVE registers */ 108 unsigned long system_save[4]; 109 /* User interrupt mask */ 110 unsigned long long interrupt_mask; 111 /* User interrupt-control 0 state */ 112 unsigned long intctrl_0; 113#if CHIP_HAS_PROC_STATUS_SPR() 114 /* Any other miscellaneous processor state bits */ 115 unsigned long proc_status; 116#endif 117#if !CHIP_HAS_FIXED_INTVEC_BASE() 118 /* Interrupt base for PL0 interrupts */ 119 unsigned long interrupt_vector_base; 120#endif 121#if CHIP_HAS_TILE_RTF_HWM() 122 /* Tile cache retry fifo high-water mark */ 123 unsigned long tile_rtf_hwm; 124#endif 125#if CHIP_HAS_DSTREAM_PF() 126 /* Data stream prefetch control */ 127 unsigned long dstream_pf; 128#endif 129#ifdef CONFIG_HARDWALL 130 /* Hardwall information for various resources. */ 131 struct hardwall_task hardwall[HARDWALL_TYPES]; 132#endif 133#if CHIP_HAS_TILE_DMA() 134 /* Async DMA TLB fault information */ 135 struct async_tlb dma_async_tlb; 136#endif 137#if CHIP_HAS_SN_PROC() 138 /* Was static network processor when we were switched out? */ 139 int sn_proc_running; 140 /* Async SNI TLB fault information */ 141 struct async_tlb sn_async_tlb; 142#endif 143}; 144 145#endif /* !__ASSEMBLY__ */ 146 147/* 148 * Start with "sp" this many bytes below the top of the kernel stack. 149 * This preserves the invariant that a called function may write to *sp. 150 */ 151#define STACK_TOP_DELTA 8 152 153/* 154 * When entering the kernel via a fault, start with the top of the 155 * pt_regs structure this many bytes below the top of the page. 156 * This aligns the pt_regs structure optimally for cache-line access. 157 */ 158#ifdef __tilegx__ 159#define KSTK_PTREGS_GAP 48 160#else 161#define KSTK_PTREGS_GAP 56 162#endif 163 164#ifndef __ASSEMBLY__ 165 166#ifdef __tilegx__ 167#define TASK_SIZE_MAX (MEM_LOW_END + 1) 168#else 169#define TASK_SIZE_MAX PAGE_OFFSET 170#endif 171 172/* TASK_SIZE and related variables are always checked in "current" context. */ 173#ifdef CONFIG_COMPAT 174#define COMPAT_TASK_SIZE (1UL << 31) 175#define TASK_SIZE ((current_thread_info()->status & TS_COMPAT) ?\ 176 COMPAT_TASK_SIZE : TASK_SIZE_MAX) 177#else 178#define TASK_SIZE TASK_SIZE_MAX 179#endif 180 181/* We provide a minimal "vdso" a la x86; just the sigreturn code for now. */ 182#define VDSO_BASE (TASK_SIZE - PAGE_SIZE) 183 184#define STACK_TOP VDSO_BASE 185 186/* STACK_TOP_MAX is used temporarily in execve and should not check COMPAT. */ 187#define STACK_TOP_MAX TASK_SIZE_MAX 188 189/* 190 * This decides where the kernel will search for a free chunk of vm 191 * space during mmap's, if it is using bottom-up mapping. 192 */ 193#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) 194 195#define HAVE_ARCH_PICK_MMAP_LAYOUT 196 197#define INIT_THREAD { \ 198 .ksp = (unsigned long)init_stack + THREAD_SIZE - STACK_TOP_DELTA, \ 199 .interrupt_mask = -1ULL \ 200} 201 202/* Kernel stack top for the task that first boots on this cpu. */ 203DECLARE_PER_CPU(unsigned long, boot_sp); 204 205/* PC to boot from on this cpu. */ 206DECLARE_PER_CPU(unsigned long, boot_pc); 207 208/* Do necessary setup to start up a newly executed thread. */ 209static inline void start_thread(struct pt_regs *regs, 210 unsigned long pc, unsigned long usp) 211{ 212 regs->pc = pc; 213 regs->sp = usp; 214 single_step_execve(); 215} 216 217/* Free all resources held by a thread. */ 218static inline void release_thread(struct task_struct *dead_task) 219{ 220 /* Nothing for now */ 221} 222 223extern int do_work_pending(struct pt_regs *regs, u32 flags); 224 225 226/* 227 * Return saved (kernel) PC of a blocked thread. 228 * Only used in a printk() in kernel/sched/core.c, so don't work too hard. 229 */ 230#define thread_saved_pc(t) ((t)->thread.pc) 231 232unsigned long get_wchan(struct task_struct *p); 233 234/* Return initial ksp value for given task. */ 235#define task_ksp0(task) ((unsigned long)(task)->stack + THREAD_SIZE) 236 237/* Return some info about the user process TASK. */ 238#define KSTK_TOP(task) (task_ksp0(task) - STACK_TOP_DELTA) 239#define task_pt_regs(task) \ 240 ((struct pt_regs *)(task_ksp0(task) - KSTK_PTREGS_GAP) - 1) 241#define current_pt_regs() \ 242 ((struct pt_regs *)((stack_pointer | (THREAD_SIZE - 1)) - \ 243 (KSTK_PTREGS_GAP - 1)) - 1) 244#define task_sp(task) (task_pt_regs(task)->sp) 245#define task_pc(task) (task_pt_regs(task)->pc) 246/* Aliases for pc and sp (used in fs/proc/array.c) */ 247#define KSTK_EIP(task) task_pc(task) 248#define KSTK_ESP(task) task_sp(task) 249 250/* Standard format for printing registers and other word-size data. */ 251#ifdef __tilegx__ 252# define REGFMT "0x%016lx" 253#else 254# define REGFMT "0x%08lx" 255#endif 256 257/* 258 * Do some slow action (e.g. read a slow SPR). 259 * Note that this must also have compiler-barrier semantics since 260 * it may be used in a busy loop reading memory. 261 */ 262static inline void cpu_relax(void) 263{ 264 __insn_mfspr(SPR_PASS); 265 barrier(); 266} 267 268/* Info on this processor (see fs/proc/cpuinfo.c) */ 269struct seq_operations; 270extern const struct seq_operations cpuinfo_op; 271 272/* Provide information about the chip model. */ 273extern char chip_model[64]; 274 275/* Data on which physical memory controller corresponds to which NUMA node. */ 276extern int node_controller[]; 277 278#if CHIP_HAS_CBOX_HOME_MAP() 279/* Does the heap allocator return hash-for-home pages by default? */ 280extern int hash_default; 281 282/* Should kernel stack pages be hash-for-home? */ 283extern int kstack_hash; 284 285/* Does MAP_ANONYMOUS return hash-for-home pages by default? */ 286#define uheap_hash hash_default 287 288#else 289#define hash_default 0 290#define kstack_hash 0 291#define uheap_hash 0 292#endif 293 294/* Are we using huge pages in the TLB for kernel data? */ 295extern int kdata_huge; 296 297/* Support standard Linux prefetching. */ 298#define ARCH_HAS_PREFETCH 299#define prefetch(x) __builtin_prefetch(x) 300#define PREFETCH_STRIDE CHIP_L2_LINE_SIZE() 301 302/* Bring a value into the L1D, faulting the TLB if necessary. */ 303#ifdef __tilegx__ 304#define prefetch_L1(x) __insn_prefetch_l1_fault((void *)(x)) 305#else 306#define prefetch_L1(x) __insn_prefetch_L1((void *)(x)) 307#endif 308 309#else /* __ASSEMBLY__ */ 310 311/* Do some slow action (e.g. read a slow SPR). */ 312#define CPU_RELAX mfspr zero, SPR_PASS 313 314#endif /* !__ASSEMBLY__ */ 315 316/* Assembly code assumes that the PL is in the low bits. */ 317#if SPR_EX_CONTEXT_1_1__PL_SHIFT != 0 318# error Fix assembly assumptions about PL 319#endif 320 321/* We sometimes use these macros for EX_CONTEXT_0_1 as well. */ 322#if SPR_EX_CONTEXT_1_1__PL_SHIFT != SPR_EX_CONTEXT_0_1__PL_SHIFT || \ 323 SPR_EX_CONTEXT_1_1__PL_RMASK != SPR_EX_CONTEXT_0_1__PL_RMASK || \ 324 SPR_EX_CONTEXT_1_1__ICS_SHIFT != SPR_EX_CONTEXT_0_1__ICS_SHIFT || \ 325 SPR_EX_CONTEXT_1_1__ICS_RMASK != SPR_EX_CONTEXT_0_1__ICS_RMASK 326# error Fix assumptions that EX1 macros work for both PL0 and PL1 327#endif 328 329/* Allow pulling apart and recombining the PL and ICS bits in EX_CONTEXT. */ 330#define EX1_PL(ex1) \ 331 (((ex1) >> SPR_EX_CONTEXT_1_1__PL_SHIFT) & SPR_EX_CONTEXT_1_1__PL_RMASK) 332#define EX1_ICS(ex1) \ 333 (((ex1) >> SPR_EX_CONTEXT_1_1__ICS_SHIFT) & SPR_EX_CONTEXT_1_1__ICS_RMASK) 334#define PL_ICS_EX1(pl, ics) \ 335 (((pl) << SPR_EX_CONTEXT_1_1__PL_SHIFT) | \ 336 ((ics) << SPR_EX_CONTEXT_1_1__ICS_SHIFT)) 337 338/* 339 * Provide symbolic constants for PLs. 340 * Note that assembly code assumes that USER_PL is zero. 341 */ 342#define USER_PL 0 343#if CONFIG_KERNEL_PL == 2 344#define GUEST_PL 1 345#endif 346#define KERNEL_PL CONFIG_KERNEL_PL 347 348/* SYSTEM_SAVE_K_0 holds the current cpu number ORed with ksp0. */ 349#define CPU_LOG_MASK_VALUE 12 350#define CPU_MASK_VALUE ((1 << CPU_LOG_MASK_VALUE) - 1) 351#if CONFIG_NR_CPUS > CPU_MASK_VALUE 352# error Too many cpus! 353#endif 354#define raw_smp_processor_id() \ 355 ((int)__insn_mfspr(SPR_SYSTEM_SAVE_K_0) & CPU_MASK_VALUE) 356#define get_current_ksp0() \ 357 (__insn_mfspr(SPR_SYSTEM_SAVE_K_0) & ~CPU_MASK_VALUE) 358#define next_current_ksp0(task) ({ \ 359 unsigned long __ksp0 = task_ksp0(task); \ 360 int __cpu = raw_smp_processor_id(); \ 361 BUG_ON(__ksp0 & CPU_MASK_VALUE); \ 362 __ksp0 | __cpu; \ 363}) 364 365#endif /* _ASM_TILE_PROCESSOR_H */ 366