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15#include <linux/sched.h>
16#include <linux/preempt.h>
17#include <linux/module.h>
18#include <linux/fs.h>
19#include <linux/kprobes.h>
20#include <linux/elfcore.h>
21#include <linux/tick.h>
22#include <linux/init.h>
23#include <linux/mm.h>
24#include <linux/compat.h>
25#include <linux/hardirq.h>
26#include <linux/syscalls.h>
27#include <linux/kernel.h>
28#include <linux/tracehook.h>
29#include <linux/signal.h>
30#include <asm/stack.h>
31#include <asm/switch_to.h>
32#include <asm/homecache.h>
33#include <asm/syscalls.h>
34#include <asm/traps.h>
35#include <asm/setup.h>
36#ifdef CONFIG_HARDWALL
37#include <asm/hardwall.h>
38#endif
39#include <arch/chip.h>
40#include <arch/abi.h>
41#include <arch/sim_def.h>
42
43
44
45
46
47
48static int __init idle_setup(char *str)
49{
50 if (!str)
51 return -EINVAL;
52
53 if (!strcmp(str, "poll")) {
54 pr_info("using polling idle threads.\n");
55 cpu_idle_poll_ctrl(true);
56 return 0;
57 } else if (!strcmp(str, "halt")) {
58 return 0;
59 }
60 return -1;
61}
62early_param("idle", idle_setup);
63
64void arch_cpu_idle(void)
65{
66 __get_cpu_var(irq_stat).idle_timestamp = jiffies;
67 _cpu_idle();
68}
69
70
71
72
73void arch_release_thread_info(struct thread_info *info)
74{
75 struct single_step_state *step_state = info->step_state;
76
77#ifdef CONFIG_HARDWALL
78
79
80
81
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83
84
85
86
87 hardwall_deactivate_all(info->task);
88#endif
89
90 if (step_state) {
91
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103
104
105
106 kfree(step_state);
107 }
108}
109
110static void save_arch_state(struct thread_struct *t);
111
112int copy_thread(unsigned long clone_flags, unsigned long sp,
113 unsigned long arg, struct task_struct *p)
114{
115 struct pt_regs *childregs = task_pt_regs(p);
116 unsigned long ksp;
117 unsigned long *callee_regs;
118
119
120
121
122
123
124
125
126
127 ksp = (unsigned long) childregs;
128 ksp -= C_ABI_SAVE_AREA_SIZE;
129 ((long *)ksp)[0] = ((long *)ksp)[1] = 0;
130 ksp -= CALLEE_SAVED_REGS_COUNT * sizeof(unsigned long);
131 callee_regs = (unsigned long *)ksp;
132 ksp -= C_ABI_SAVE_AREA_SIZE;
133 ((long *)ksp)[0] = ((long *)ksp)[1] = 0;
134 p->thread.ksp = ksp;
135
136
137 p->thread.creator_pid = current->pid;
138
139 if (unlikely(p->flags & PF_KTHREAD)) {
140
141 memset(childregs, 0, sizeof(struct pt_regs));
142 memset(&callee_regs[2], 0,
143 (CALLEE_SAVED_REGS_COUNT - 2) * sizeof(unsigned long));
144 callee_regs[0] = sp;
145 callee_regs[1] = arg;
146 childregs->ex1 = PL_ICS_EX1(KERNEL_PL, 0);
147 p->thread.pc = (unsigned long) ret_from_kernel_thread;
148 return 0;
149 }
150
151
152
153
154
155 p->thread.pc = (unsigned long) ret_from_fork;
156
157
158
159
160
161 task_thread_info(p)->step_state = NULL;
162
163
164
165
166
167 *childregs = *current_pt_regs();
168 childregs->regs[0] = 0;
169 if (sp)
170 childregs->sp = sp;
171 memcpy(callee_regs, &childregs->regs[CALLEE_SAVED_FIRST_REG],
172 CALLEE_SAVED_REGS_COUNT * sizeof(unsigned long));
173
174
175 p->thread.usp0 = childregs->sp;
176
177
178
179
180
181 if (clone_flags & CLONE_SETTLS)
182 childregs->tp = childregs->regs[4];
183
184
185#if CHIP_HAS_TILE_DMA()
186
187
188
189
190 memset(&p->thread.tile_dma_state, 0, sizeof(struct tile_dma_state));
191 memset(&p->thread.dma_async_tlb, 0, sizeof(struct async_tlb));
192#endif
193
194#if CHIP_HAS_SN_PROC()
195
196 p->thread.sn_proc_running = 0;
197 memset(&p->thread.sn_async_tlb, 0, sizeof(struct async_tlb));
198#endif
199
200#if CHIP_HAS_PROC_STATUS_SPR()
201
202 p->thread.proc_status = 0;
203#endif
204
205#ifdef CONFIG_HARDWALL
206
207 memset(&p->thread.hardwall[0], 0,
208 sizeof(struct hardwall_task) * HARDWALL_TYPES);
209#endif
210
211
212
213
214
215
216 save_arch_state(&p->thread);
217
218 return 0;
219}
220
221
222
223
224
225struct task_struct *validate_current(void)
226{
227 static struct task_struct corrupt = { .comm = "<corrupt>" };
228 struct task_struct *tsk = current;
229 if (unlikely((unsigned long)tsk < PAGE_OFFSET ||
230 (high_memory && (void *)tsk > high_memory) ||
231 ((unsigned long)tsk & (__alignof__(*tsk) - 1)) != 0)) {
232 pr_err("Corrupt 'current' %p (sp %#lx)\n", tsk, stack_pointer);
233 tsk = &corrupt;
234 }
235 return tsk;
236}
237
238
239struct task_struct *sim_notify_fork(struct task_struct *prev)
240{
241 struct task_struct *tsk = current;
242 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_OS_FORK_PARENT |
243 (tsk->thread.creator_pid << _SIM_CONTROL_OPERATOR_BITS));
244 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_OS_FORK |
245 (tsk->pid << _SIM_CONTROL_OPERATOR_BITS));
246 return prev;
247}
248
249int dump_task_regs(struct task_struct *tsk, elf_gregset_t *regs)
250{
251 struct pt_regs *ptregs = task_pt_regs(tsk);
252 elf_core_copy_regs(regs, ptregs);
253 return 1;
254}
255
256#if CHIP_HAS_TILE_DMA()
257
258
259void grant_dma_mpls(void)
260{
261#if CONFIG_KERNEL_PL == 2
262 __insn_mtspr(SPR_MPL_DMA_CPL_SET_1, 1);
263 __insn_mtspr(SPR_MPL_DMA_NOTIFY_SET_1, 1);
264#else
265 __insn_mtspr(SPR_MPL_DMA_CPL_SET_0, 1);
266 __insn_mtspr(SPR_MPL_DMA_NOTIFY_SET_0, 1);
267#endif
268}
269
270
271void restrict_dma_mpls(void)
272{
273#if CONFIG_KERNEL_PL == 2
274 __insn_mtspr(SPR_MPL_DMA_CPL_SET_2, 1);
275 __insn_mtspr(SPR_MPL_DMA_NOTIFY_SET_2, 1);
276#else
277 __insn_mtspr(SPR_MPL_DMA_CPL_SET_1, 1);
278 __insn_mtspr(SPR_MPL_DMA_NOTIFY_SET_1, 1);
279#endif
280}
281
282
283static void save_tile_dma_state(struct tile_dma_state *dma)
284{
285 unsigned long state = __insn_mfspr(SPR_DMA_USER_STATUS);
286 unsigned long post_suspend_state;
287
288
289 if ((state & DMA_STATUS_MASK) == SPR_DMA_STATUS__RUNNING_MASK)
290 __insn_mtspr(SPR_DMA_CTR, SPR_DMA_CTR__SUSPEND_MASK);
291
292
293
294
295
296
297
298
299
300 do {
301 post_suspend_state = __insn_mfspr(SPR_DMA_USER_STATUS);
302 } while (post_suspend_state & SPR_DMA_STATUS__BUSY_MASK);
303
304 dma->src = __insn_mfspr(SPR_DMA_SRC_ADDR);
305 dma->src_chunk = __insn_mfspr(SPR_DMA_SRC_CHUNK_ADDR);
306 dma->dest = __insn_mfspr(SPR_DMA_DST_ADDR);
307 dma->dest_chunk = __insn_mfspr(SPR_DMA_DST_CHUNK_ADDR);
308 dma->strides = __insn_mfspr(SPR_DMA_STRIDE);
309 dma->chunk_size = __insn_mfspr(SPR_DMA_CHUNK_SIZE);
310 dma->byte = __insn_mfspr(SPR_DMA_BYTE);
311 dma->status = (state & SPR_DMA_STATUS__RUNNING_MASK) |
312 (post_suspend_state & SPR_DMA_STATUS__DONE_MASK);
313}
314
315
316static void restore_tile_dma_state(struct thread_struct *t)
317{
318 const struct tile_dma_state *dma = &t->tile_dma_state;
319
320
321
322
323
324 if ((dma->status & SPR_DMA_STATUS__DONE_MASK) &&
325 !(__insn_mfspr(SPR_DMA_USER_STATUS) & SPR_DMA_STATUS__DONE_MASK)) {
326 __insn_mtspr(SPR_DMA_BYTE, 0);
327 __insn_mtspr(SPR_DMA_CTR, SPR_DMA_CTR__REQUEST_MASK);
328 while (__insn_mfspr(SPR_DMA_USER_STATUS) &
329 SPR_DMA_STATUS__BUSY_MASK)
330 ;
331 }
332
333 __insn_mtspr(SPR_DMA_SRC_ADDR, dma->src);
334 __insn_mtspr(SPR_DMA_SRC_CHUNK_ADDR, dma->src_chunk);
335 __insn_mtspr(SPR_DMA_DST_ADDR, dma->dest);
336 __insn_mtspr(SPR_DMA_DST_CHUNK_ADDR, dma->dest_chunk);
337 __insn_mtspr(SPR_DMA_STRIDE, dma->strides);
338 __insn_mtspr(SPR_DMA_CHUNK_SIZE, dma->chunk_size);
339 __insn_mtspr(SPR_DMA_BYTE, dma->byte);
340
341
342
343
344
345
346
347
348
349 if ((dma->status & DMA_STATUS_MASK) == SPR_DMA_STATUS__RUNNING_MASK) {
350 t->dma_async_tlb.fault_num = 0;
351 __insn_mtspr(SPR_DMA_CTR, SPR_DMA_CTR__REQUEST_MASK);
352 }
353}
354
355#endif
356
357static void save_arch_state(struct thread_struct *t)
358{
359#if CHIP_HAS_SPLIT_INTR_MASK()
360 t->interrupt_mask = __insn_mfspr(SPR_INTERRUPT_MASK_0_0) |
361 ((u64)__insn_mfspr(SPR_INTERRUPT_MASK_0_1) << 32);
362#else
363 t->interrupt_mask = __insn_mfspr(SPR_INTERRUPT_MASK_0);
364#endif
365 t->ex_context[0] = __insn_mfspr(SPR_EX_CONTEXT_0_0);
366 t->ex_context[1] = __insn_mfspr(SPR_EX_CONTEXT_0_1);
367 t->system_save[0] = __insn_mfspr(SPR_SYSTEM_SAVE_0_0);
368 t->system_save[1] = __insn_mfspr(SPR_SYSTEM_SAVE_0_1);
369 t->system_save[2] = __insn_mfspr(SPR_SYSTEM_SAVE_0_2);
370 t->system_save[3] = __insn_mfspr(SPR_SYSTEM_SAVE_0_3);
371 t->intctrl_0 = __insn_mfspr(SPR_INTCTRL_0_STATUS);
372#if CHIP_HAS_PROC_STATUS_SPR()
373 t->proc_status = __insn_mfspr(SPR_PROC_STATUS);
374#endif
375#if !CHIP_HAS_FIXED_INTVEC_BASE()
376 t->interrupt_vector_base = __insn_mfspr(SPR_INTERRUPT_VECTOR_BASE_0);
377#endif
378#if CHIP_HAS_TILE_RTF_HWM()
379 t->tile_rtf_hwm = __insn_mfspr(SPR_TILE_RTF_HWM);
380#endif
381#if CHIP_HAS_DSTREAM_PF()
382 t->dstream_pf = __insn_mfspr(SPR_DSTREAM_PF);
383#endif
384}
385
386static void restore_arch_state(const struct thread_struct *t)
387{
388#if CHIP_HAS_SPLIT_INTR_MASK()
389 __insn_mtspr(SPR_INTERRUPT_MASK_0_0, (u32) t->interrupt_mask);
390 __insn_mtspr(SPR_INTERRUPT_MASK_0_1, t->interrupt_mask >> 32);
391#else
392 __insn_mtspr(SPR_INTERRUPT_MASK_0, t->interrupt_mask);
393#endif
394 __insn_mtspr(SPR_EX_CONTEXT_0_0, t->ex_context[0]);
395 __insn_mtspr(SPR_EX_CONTEXT_0_1, t->ex_context[1]);
396 __insn_mtspr(SPR_SYSTEM_SAVE_0_0, t->system_save[0]);
397 __insn_mtspr(SPR_SYSTEM_SAVE_0_1, t->system_save[1]);
398 __insn_mtspr(SPR_SYSTEM_SAVE_0_2, t->system_save[2]);
399 __insn_mtspr(SPR_SYSTEM_SAVE_0_3, t->system_save[3]);
400 __insn_mtspr(SPR_INTCTRL_0_STATUS, t->intctrl_0);
401#if CHIP_HAS_PROC_STATUS_SPR()
402 __insn_mtspr(SPR_PROC_STATUS, t->proc_status);
403#endif
404#if !CHIP_HAS_FIXED_INTVEC_BASE()
405 __insn_mtspr(SPR_INTERRUPT_VECTOR_BASE_0, t->interrupt_vector_base);
406#endif
407#if CHIP_HAS_TILE_RTF_HWM()
408 __insn_mtspr(SPR_TILE_RTF_HWM, t->tile_rtf_hwm);
409#endif
410#if CHIP_HAS_DSTREAM_PF()
411 __insn_mtspr(SPR_DSTREAM_PF, t->dstream_pf);
412#endif
413}
414
415
416void _prepare_arch_switch(struct task_struct *next)
417{
418#if CHIP_HAS_SN_PROC()
419 int snctl;
420#endif
421#if CHIP_HAS_TILE_DMA()
422 struct tile_dma_state *dma = ¤t->thread.tile_dma_state;
423 if (dma->enabled)
424 save_tile_dma_state(dma);
425#endif
426#if CHIP_HAS_SN_PROC()
427
428
429
430
431
432 snctl = __insn_mfspr(SPR_SNCTL);
433 current->thread.sn_proc_running =
434 (snctl & SPR_SNCTL__FRZPROC_MASK) == 0;
435 if (current->thread.sn_proc_running)
436 __insn_mtspr(SPR_SNCTL, snctl | SPR_SNCTL__FRZPROC_MASK);
437#endif
438}
439
440
441struct task_struct *__sched _switch_to(struct task_struct *prev,
442 struct task_struct *next)
443{
444
445 save_arch_state(&prev->thread);
446
447#if CHIP_HAS_TILE_DMA()
448
449
450
451
452
453
454 if (next->thread.tile_dma_state.enabled) {
455 restore_tile_dma_state(&next->thread);
456 grant_dma_mpls();
457 } else {
458 restrict_dma_mpls();
459 }
460#endif
461
462
463 restore_arch_state(&next->thread);
464
465#if CHIP_HAS_SN_PROC()
466
467
468
469
470 if (next->thread.sn_proc_running) {
471 int snctl = __insn_mfspr(SPR_SNCTL);
472 __insn_mtspr(SPR_SNCTL, snctl & ~SPR_SNCTL__FRZPROC_MASK);
473 }
474#endif
475
476#ifdef CONFIG_HARDWALL
477
478 hardwall_switch_tasks(prev, next);
479#endif
480
481
482
483
484
485
486
487 return __switch_to(prev, next, next_current_ksp0(next));
488}
489
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503
504int do_work_pending(struct pt_regs *regs, u32 thread_info_flags)
505{
506
507 if (!user_mode(regs))
508 return 0;
509
510
511 local_irq_enable();
512
513 if (thread_info_flags & _TIF_NEED_RESCHED) {
514 schedule();
515 return 1;
516 }
517#if CHIP_HAS_TILE_DMA() || CHIP_HAS_SN_PROC()
518 if (thread_info_flags & _TIF_ASYNC_TLB) {
519 do_async_page_fault(regs);
520 return 1;
521 }
522#endif
523 if (thread_info_flags & _TIF_SIGPENDING) {
524 do_signal(regs);
525 return 1;
526 }
527 if (thread_info_flags & _TIF_NOTIFY_RESUME) {
528 clear_thread_flag(TIF_NOTIFY_RESUME);
529 tracehook_notify_resume(regs);
530 return 1;
531 }
532 if (thread_info_flags & _TIF_SINGLESTEP) {
533 single_step_once(regs);
534 return 0;
535 }
536 panic("work_pending: bad flags %#x\n", thread_info_flags);
537}
538
539unsigned long get_wchan(struct task_struct *p)
540{
541 struct KBacktraceIterator kbt;
542
543 if (!p || p == current || p->state == TASK_RUNNING)
544 return 0;
545
546 for (KBacktraceIterator_init(&kbt, p, NULL);
547 !KBacktraceIterator_end(&kbt);
548 KBacktraceIterator_next(&kbt)) {
549 if (!in_sched_functions(kbt.it.pc))
550 return kbt.it.pc;
551 }
552
553 return 0;
554}
555
556
557void flush_thread(void)
558{
559
560}
561
562
563
564
565void exit_thread(void)
566{
567
568}
569
570void show_regs(struct pt_regs *regs)
571{
572 struct task_struct *tsk = validate_current();
573 int i;
574
575 pr_err("\n");
576 show_regs_print_info(KERN_ERR);
577#ifdef __tilegx__
578 for (i = 0; i < 51; i += 3)
579 pr_err(" r%-2d: "REGFMT" r%-2d: "REGFMT" r%-2d: "REGFMT"\n",
580 i, regs->regs[i], i+1, regs->regs[i+1],
581 i+2, regs->regs[i+2]);
582 pr_err(" r51: "REGFMT" r52: "REGFMT" tp : "REGFMT"\n",
583 regs->regs[51], regs->regs[52], regs->tp);
584 pr_err(" sp : "REGFMT" lr : "REGFMT"\n", regs->sp, regs->lr);
585#else
586 for (i = 0; i < 52; i += 4)
587 pr_err(" r%-2d: "REGFMT" r%-2d: "REGFMT
588 " r%-2d: "REGFMT" r%-2d: "REGFMT"\n",
589 i, regs->regs[i], i+1, regs->regs[i+1],
590 i+2, regs->regs[i+2], i+3, regs->regs[i+3]);
591 pr_err(" r52: "REGFMT" tp : "REGFMT" sp : "REGFMT" lr : "REGFMT"\n",
592 regs->regs[52], regs->tp, regs->sp, regs->lr);
593#endif
594 pr_err(" pc : "REGFMT" ex1: %ld faultnum: %ld\n",
595 regs->pc, regs->ex1, regs->faultnum);
596
597 dump_stack_regs(regs);
598}
599