LXR linux/arch/x86/include/asm/dma.h

   1/*
   2 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
   3 * Written by Hennus Bergman, 1992.
   4 * High DMA channel support & info by Hannu Savolainen
   5 * and John Boyd, Nov. 1992.
   6 */
   7
   8#ifndef _ASM_X86_DMA_H
   9#define _ASM_X86_DMA_H
  10
  11#include <linux/spinlock.h>     /* And spinlocks */
  12#include <asm/io.h>             /* need byte IO */
  13
  14#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
  15#define dma_outb        outb_p
  16#else
  17#define dma_outb        outb
  18#endif
  19
  20#define dma_inb         inb
  21
  22/*
  23 * NOTES about DMA transfers:
  24 *
  25 *  controller 1: channels 0-3, byte operations, ports 00-1F
  26 *  controller 2: channels 4-7, word operations, ports C0-DF
  27 *
  28 *  - ALL registers are 8 bits only, regardless of transfer size
  29 *  - channel 4 is not used - cascades 1 into 2.
  30 *  - channels 0-3 are byte - addresses/counts are for physical bytes
  31 *  - channels 5-7 are word - addresses/counts are for physical words
  32 *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
  33 *  - transfer count loaded to registers is 1 less than actual count
  34 *  - controller 2 offsets are all even (2x offsets for controller 1)
  35 *  - page registers for 5-7 don't use data bit 0, represent 128K pages
  36 *  - page registers for 0-3 use bit 0, represent 64K pages
  37 *
  38 * DMA transfers are limited to the lower 16MB of _physical_ memory.
  39 * Note that addresses loaded into registers must be _physical_ addresses,
  40 * not logical addresses (which may differ if paging is active).
  41 *
  42 *  Address mapping for channels 0-3:
  43 *
  44 *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
  45 *    |  ...  |   |  ... |   |  ... |
  46 *    |  ...  |   |  ... |   |  ... |
  47 *    |  ...  |   |  ... |   |  ... |
  48 *   P7  ...  P0  A7 ... A0  A7 ... A0
  49 * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
  50 *
  51 *  Address mapping for channels 5-7:
  52 *
  53 *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
  54 *    |  ...  |   \   \   ... \  \  \  ... \  \
  55 *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
  56 *    |  ...  |     \   \   ... \  \  \  ... \
  57 *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
  58 * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
  59 *
  60 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
  61 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
  62 * the hardware level, so odd-byte transfers aren't possible).
  63 *
  64 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
  65 * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
  66 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
  67 *
  68 */
  69
  70#define MAX_DMA_CHANNELS        8
  71
  72/* 16MB ISA DMA zone */
  73#define MAX_DMA_PFN   ((16 * 1024 * 1024) >> PAGE_SHIFT)
  74
  75/* 4GB broken PCI/AGP hardware bus master zone */
  76#define MAX_DMA32_PFN ((4UL * 1024 * 1024 * 1024) >> PAGE_SHIFT)
  77
  78#ifdef CONFIG_X86_32
  79/* The maximum address that we can perform a DMA transfer to on this platform */
  80#define MAX_DMA_ADDRESS      (PAGE_OFFSET + 0x1000000)
  81#else
  82/* Compat define for old dma zone */
  83#define MAX_DMA_ADDRESS ((unsigned long)__va(MAX_DMA_PFN << PAGE_SHIFT))
  84#endif
  85
  86/* 8237 DMA controllers */
  87#define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
  88#define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
  89
  90/* DMA controller registers */
  91#define DMA1_CMD_REG            0x08    /* command register (w) */
  92#define DMA1_STAT_REG           0x08    /* status register (r) */
  93#define DMA1_REQ_REG            0x09    /* request register (w) */
  94#define DMA1_MASK_REG           0x0A    /* single-channel mask (w) */
  95#define DMA1_MODE_REG           0x0B    /* mode register (w) */
  96#define DMA1_CLEAR_FF_REG       0x0C    /* clear pointer flip-flop (w) */
  97#define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
  98#define DMA1_RESET_REG          0x0D    /* Master Clear (w) */
  99#define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
 100#define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
 101
 102#define DMA2_CMD_REG            0xD0    /* command register (w) */
 103#define DMA2_STAT_REG           0xD0    /* status register (r) */
 104#define DMA2_REQ_REG            0xD2    /* request register (w) */
 105#define DMA2_MASK_REG           0xD4    /* single-channel mask (w) */
 106#define DMA2_MODE_REG           0xD6    /* mode register (w) */
 107#define DMA2_CLEAR_FF_REG       0xD8    /* clear pointer flip-flop (w) */
 108#define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
 109#define DMA2_RESET_REG          0xDA    /* Master Clear (w) */
 110#define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
 111#define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
 112
 113#define DMA_ADDR_0              0x00    /* DMA address registers */
 114#define DMA_ADDR_1              0x02
 115#define DMA_ADDR_2              0x04
 116#define DMA_ADDR_3              0x06
 117#define DMA_ADDR_4              0xC0
 118#define DMA_ADDR_5              0xC4
 119#define DMA_ADDR_6              0xC8
 120#define DMA_ADDR_7              0xCC
 121
 122#define DMA_CNT_0               0x01    /* DMA count registers */
 123#define DMA_CNT_1               0x03
 124#define DMA_CNT_2               0x05
 125#define DMA_CNT_3               0x07
 126#define DMA_CNT_4               0xC2
 127#define DMA_CNT_5               0xC6
 128#define DMA_CNT_6               0xCA
 129#define DMA_CNT_7               0xCE
 130
 131#define DMA_PAGE_0              0x87    /* DMA page registers */
 132#define DMA_PAGE_1              0x83
 133#define DMA_PAGE_2              0x81
 134#define DMA_PAGE_3              0x82
 135#define DMA_PAGE_5              0x8B
 136#define DMA_PAGE_6              0x89
 137#define DMA_PAGE_7              0x8A
 138
 139/* I/O to memory, no autoinit, increment, single mode */
 140#define DMA_MODE_READ           0x44
 141/* memory to I/O, no autoinit, increment, single mode */
 142#define DMA_MODE_WRITE          0x48
 143/* pass thru DREQ->HRQ, DACK<-HLDA only */
 144#define DMA_MODE_CASCADE        0xC0
 145
 146#define DMA_AUTOINIT            0x10
 147
 148
 149#ifdef CONFIG_ISA_DMA_API
 150extern spinlock_t  dma_spin_lock;
 151
 152static inline unsigned long claim_dma_lock(void)
 153{
 154        unsigned long flags;
 155        spin_lock_irqsave(&dma_spin_lock, flags);
 156        return flags;
 157}
 158
 159static inline void release_dma_lock(unsigned long flags)
 160{
 161        spin_unlock_irqrestore(&dma_spin_lock, flags);
 162}
 163#endif /* CONFIG_ISA_DMA_API */
 164
 165/* enable/disable a specific DMA channel */
 166static inline void enable_dma(unsigned int dmanr)
 167{
 168        if (dmanr <= 3)
 169                dma_outb(dmanr, DMA1_MASK_REG);
 170        else
 171                dma_outb(dmanr & 3, DMA2_MASK_REG);
 172}
 173
 174static inline void disable_dma(unsigned int dmanr)
 175{
 176        if (dmanr <= 3)
 177                dma_outb(dmanr | 4, DMA1_MASK_REG);
 178        else
 179                dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
 180}
 181
 182/* Clear the 'DMA Pointer Flip Flop'.
 183 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
 184 * Use this once to initialize the FF to a known state.
 185 * After that, keep track of it. :-)
 186 * --- In order to do that, the DMA routines below should ---
 187 * --- only be used while holding the DMA lock ! ---
 188 */
 189static inline void clear_dma_ff(unsigned int dmanr)
 190{
 191        if (dmanr <= 3)
 192                dma_outb(0, DMA1_CLEAR_FF_REG);
 193        else
 194                dma_outb(0, DMA2_CLEAR_FF_REG);
 195}
 196
 197/* set mode (above) for a specific DMA channel */
 198static inline void set_dma_mode(unsigned int dmanr, char mode)
 199{
 200        if (dmanr <= 3)
 201                dma_outb(mode | dmanr, DMA1_MODE_REG);
 202        else
 203                dma_outb(mode | (dmanr & 3), DMA2_MODE_REG);
 204}
 205
 206/* Set only the page register bits of the transfer address.
 207 * This is used for successive transfers when we know the contents of
 208 * the lower 16 bits of the DMA current address register, but a 64k boundary
 209 * may have been crossed.
 210 */
 211static inline void set_dma_page(unsigned int dmanr, char pagenr)
 212{
 213        switch (dmanr) {
 214        case 0:
 215                dma_outb(pagenr, DMA_PAGE_0);
 216                break;
 217        case 1:
 218                dma_outb(pagenr, DMA_PAGE_1);
 219                break;
 220        case 2:
 221                dma_outb(pagenr, DMA_PAGE_2);
 222                break;
 223        case 3:
 224                dma_outb(pagenr, DMA_PAGE_3);
 225                break;
 226        case 5:
 227                dma_outb(pagenr & 0xfe, DMA_PAGE_5);
 228                break;
 229        case 6:
 230                dma_outb(pagenr & 0xfe, DMA_PAGE_6);
 231                break;
 232        case 7:
 233                dma_outb(pagenr & 0xfe, DMA_PAGE_7);
 234                break;
 235        }
 236}
 237
 238
 239/* Set transfer address & page bits for specific DMA channel.
 240 * Assumes dma flipflop is clear.
 241 */
 242static inline void set_dma_addr(unsigned int dmanr, unsigned int a)
 243{
 244        set_dma_page(dmanr, a>>16);
 245        if (dmanr <= 3)  {
 246                dma_outb(a & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
 247                dma_outb((a >> 8) & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
 248        }  else  {
 249                dma_outb((a >> 1) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
 250                dma_outb((a >> 9) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
 251        }
 252}
 253
 254
 255/* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for
 256 * a specific DMA channel.
 257 * You must ensure the parameters are valid.
 258 * NOTE: from a manual: "the number of transfers is one more
 259 * than the initial word count"! This is taken into account.
 260 * Assumes dma flip-flop is clear.
 261 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
 262 */
 263static inline void set_dma_count(unsigned int dmanr, unsigned int count)
 264{
 265        count--;
 266        if (dmanr <= 3)  {
 267                dma_outb(count & 0xff, ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
 268                dma_outb((count >> 8) & 0xff,
 269                         ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
 270        } else {
 271                dma_outb((count >> 1) & 0xff,
 272                         ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
 273                dma_outb((count >> 9) & 0xff,
 274                         ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
 275        }
 276}
 277
 278
 279/* Get DMA residue count. After a DMA transfer, this
 280 * should return zero. Reading this while a DMA transfer is
 281 * still in progress will return unpredictable results.
 282 * If called before the channel has been used, it may return 1.
 283 * Otherwise, it returns the number of _bytes_ left to transfer.
 284 *
 285 * Assumes DMA flip-flop is clear.
 286 */
 287static inline int get_dma_residue(unsigned int dmanr)
 288{
 289        unsigned int io_port;
 290        /* using short to get 16-bit wrap around */
 291        unsigned short count;
 292
 293        io_port = (dmanr <= 3) ? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
 294                : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
 295
 296        count = 1 + dma_inb(io_port);
 297        count += dma_inb(io_port) << 8;
 298
 299        return (dmanr <= 3) ? count : (count << 1);
 300}
 301
 302
 303/* These are in kernel/dma.c because x86 uses CONFIG_GENERIC_ISA_DMA */
 304#ifdef CONFIG_ISA_DMA_API
 305extern int request_dma(unsigned int dmanr, const char *device_id);
 306extern void free_dma(unsigned int dmanr);
 307#endif
 308
 309/* From PCI */
 310
 311#ifdef CONFIG_PCI
 312extern int isa_dma_bridge_buggy;
 313#else
 314#define isa_dma_bridge_buggy    (0)
 315#endif
 316
 317#endif /* _ASM_X86_DMA_H */
 318