LXR linux/arch/x86/include/asm/xen/interface.h

   1/******************************************************************************
   2 * arch-x86_32.h
   3 *
   4 * Guest OS interface to x86 Xen.
   5 *
   6 * Copyright (c) 2004, K A Fraser
   7 */
   8
   9#ifndef _ASM_X86_XEN_INTERFACE_H
  10#define _ASM_X86_XEN_INTERFACE_H
  11
  12#ifdef __XEN__
  13#define __DEFINE_GUEST_HANDLE(name, type) \
  14    typedef struct { type *p; } __guest_handle_ ## name
  15#else
  16#define __DEFINE_GUEST_HANDLE(name, type) \
  17    typedef type * __guest_handle_ ## name
  18#endif
  19
  20#define DEFINE_GUEST_HANDLE_STRUCT(name) \
  21        __DEFINE_GUEST_HANDLE(name, struct name)
  22#define DEFINE_GUEST_HANDLE(name) __DEFINE_GUEST_HANDLE(name, name)
  23#define GUEST_HANDLE(name)        __guest_handle_ ## name
  24
  25#ifdef __XEN__
  26#if defined(__i386__)
  27#define set_xen_guest_handle(hnd, val)                  \
  28        do {                                            \
  29                if (sizeof(hnd) == 8)                   \
  30                        *(uint64_t *)&(hnd) = 0;        \
  31                (hnd).p = val;                          \
  32        } while (0)
  33#elif defined(__x86_64__)
  34#define set_xen_guest_handle(hnd, val)  do { (hnd).p = val; } while (0)
  35#endif
  36#else
  37#if defined(__i386__)
  38#define set_xen_guest_handle(hnd, val)                  \
  39        do {                                            \
  40                if (sizeof(hnd) == 8)                   \
  41                        *(uint64_t *)&(hnd) = 0;        \
  42                (hnd) = val;                            \
  43        } while (0)
  44#elif defined(__x86_64__)
  45#define set_xen_guest_handle(hnd, val)  do { (hnd) = val; } while (0)
  46#endif
  47#endif
  48
  49#ifndef __ASSEMBLY__
  50/* Explicitly size integers that represent pfns in the public interface
  51 * with Xen so that on ARM we can have one ABI that works for 32 and 64
  52 * bit guests. */
  53typedef unsigned long xen_pfn_t;
  54#define PRI_xen_pfn "lx"
  55typedef unsigned long xen_ulong_t;
  56#define PRI_xen_ulong "lx"
  57/* Guest handles for primitive C types. */
  58__DEFINE_GUEST_HANDLE(uchar, unsigned char);
  59__DEFINE_GUEST_HANDLE(uint,  unsigned int);
  60DEFINE_GUEST_HANDLE(char);
  61DEFINE_GUEST_HANDLE(int);
  62DEFINE_GUEST_HANDLE(void);
  63DEFINE_GUEST_HANDLE(uint64_t);
  64DEFINE_GUEST_HANDLE(uint32_t);
  65DEFINE_GUEST_HANDLE(xen_pfn_t);
  66DEFINE_GUEST_HANDLE(xen_ulong_t);
  67#endif
  68
  69#ifndef HYPERVISOR_VIRT_START
  70#define HYPERVISOR_VIRT_START mk_unsigned_long(__HYPERVISOR_VIRT_START)
  71#endif
  72
  73#define MACH2PHYS_VIRT_START  mk_unsigned_long(__MACH2PHYS_VIRT_START)
  74#define MACH2PHYS_VIRT_END    mk_unsigned_long(__MACH2PHYS_VIRT_END)
  75#define MACH2PHYS_NR_ENTRIES  ((MACH2PHYS_VIRT_END-MACH2PHYS_VIRT_START)>>__MACH2PHYS_SHIFT)
  76
  77/* Maximum number of virtual CPUs in multi-processor guests. */
  78#define MAX_VIRT_CPUS 32
  79
  80/*
  81 * SEGMENT DESCRIPTOR TABLES
  82 */
  83/*
  84 * A number of GDT entries are reserved by Xen. These are not situated at the
  85 * start of the GDT because some stupid OSes export hard-coded selector values
  86 * in their ABI. These hard-coded values are always near the start of the GDT,
  87 * so Xen places itself out of the way, at the far end of the GDT.
  88 */
  89#define FIRST_RESERVED_GDT_PAGE  14
  90#define FIRST_RESERVED_GDT_BYTE  (FIRST_RESERVED_GDT_PAGE * 4096)
  91#define FIRST_RESERVED_GDT_ENTRY (FIRST_RESERVED_GDT_BYTE / 8)
  92
  93/*
  94 * Send an array of these to HYPERVISOR_set_trap_table()
  95 * The privilege level specifies which modes may enter a trap via a software
  96 * interrupt. On x86/64, since rings 1 and 2 are unavailable, we allocate
  97 * privilege levels as follows:
  98 *  Level == 0: No one may enter
  99 *  Level == 1: Kernel may enter
 100 *  Level == 2: Kernel may enter
 101 *  Level == 3: Everyone may enter
 102 */
 103#define TI_GET_DPL(_ti)         ((_ti)->flags & 3)
 104#define TI_GET_IF(_ti)          ((_ti)->flags & 4)
 105#define TI_SET_DPL(_ti, _dpl)   ((_ti)->flags |= (_dpl))
 106#define TI_SET_IF(_ti, _if)     ((_ti)->flags |= ((!!(_if))<<2))
 107
 108#ifndef __ASSEMBLY__
 109struct trap_info {
 110    uint8_t       vector;  /* exception vector                              */
 111    uint8_t       flags;   /* 0-3: privilege level; 4: clear event enable?  */
 112    uint16_t      cs;      /* code selector                                 */
 113    unsigned long address; /* code offset                                   */
 114};
 115DEFINE_GUEST_HANDLE_STRUCT(trap_info);
 116
 117struct arch_shared_info {
 118    unsigned long max_pfn;                  /* max pfn that appears in table */
 119    /* Frame containing list of mfns containing list of mfns containing p2m. */
 120    unsigned long pfn_to_mfn_frame_list_list;
 121    unsigned long nmi_reason;
 122};
 123#endif  /* !__ASSEMBLY__ */
 124
 125#ifdef CONFIG_X86_32
 126#include <asm/xen/interface_32.h>
 127#else
 128#include <asm/xen/interface_64.h>
 129#endif
 130
 131#include <asm/pvclock-abi.h>
 132
 133#ifndef __ASSEMBLY__
 134/*
 135 * The following is all CPU context. Note that the fpu_ctxt block is filled
 136 * in by FXSAVE if the CPU has feature FXSR; otherwise FSAVE is used.
 137 */
 138struct vcpu_guest_context {
 139    /* FPU registers come first so they can be aligned for FXSAVE/FXRSTOR. */
 140    struct { char x[512]; } fpu_ctxt;       /* User-level FPU registers     */
 141#define VGCF_I387_VALID (1<<0)
 142#define VGCF_HVM_GUEST  (1<<1)
 143#define VGCF_IN_KERNEL  (1<<2)
 144    unsigned long flags;                    /* VGCF_* flags                 */
 145    struct cpu_user_regs user_regs;         /* User-level CPU registers     */
 146    struct trap_info trap_ctxt[256];        /* Virtual IDT                  */
 147    unsigned long ldt_base, ldt_ents;       /* LDT (linear address, # ents) */
 148    unsigned long gdt_frames[16], gdt_ents; /* GDT (machine frames, # ents) */
 149    unsigned long kernel_ss, kernel_sp;     /* Virtual TSS (only SS1/SP1)   */
 150    /* NB. User pagetable on x86/64 is placed in ctrlreg[1]. */
 151    unsigned long ctrlreg[8];               /* CR0-CR7 (control registers)  */
 152    unsigned long debugreg[8];              /* DB0-DB7 (debug registers)    */
 153#ifdef __i386__
 154    unsigned long event_callback_cs;        /* CS:EIP of event callback     */
 155    unsigned long event_callback_eip;
 156    unsigned long failsafe_callback_cs;     /* CS:EIP of failsafe callback  */
 157    unsigned long failsafe_callback_eip;
 158#else
 159    unsigned long event_callback_eip;
 160    unsigned long failsafe_callback_eip;
 161    unsigned long syscall_callback_eip;
 162#endif
 163    unsigned long vm_assist;                /* VMASST_TYPE_* bitmap */
 164#ifdef __x86_64__
 165    /* Segment base addresses. */
 166    uint64_t      fs_base;
 167    uint64_t      gs_base_kernel;
 168    uint64_t      gs_base_user;
 169#endif
 170};
 171DEFINE_GUEST_HANDLE_STRUCT(vcpu_guest_context);
 172#endif  /* !__ASSEMBLY__ */
 173
 174/*
 175 * Prefix forces emulation of some non-trapping instructions.
 176 * Currently only CPUID.
 177 */
 178#ifdef __ASSEMBLY__
 179#define XEN_EMULATE_PREFIX .byte 0x0f,0x0b,0x78,0x65,0x6e ;
 180#define XEN_CPUID          XEN_EMULATE_PREFIX cpuid
 181#else
 182#define XEN_EMULATE_PREFIX ".byte 0x0f,0x0b,0x78,0x65,0x6e ; "
 183#define XEN_CPUID          XEN_EMULATE_PREFIX "cpuid"
 184#endif
 185
 186#endif /* _ASM_X86_XEN_INTERFACE_H */
 187