1
2
3
4
5#include <linux/interrupt.h>
6#include <linux/kernel.h>
7#include <linux/types.h>
8#include <linux/init.h>
9#include <linux/smp.h>
10
11#include <asm/processor.h>
12#include <asm/mce.h>
13#include <asm/msr.h>
14
15
16int mce_p5_enabled __read_mostly;
17
18
19static void pentium_machine_check(struct pt_regs *regs, long error_code)
20{
21 u32 loaddr, hi, lotype;
22
23 rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
24 rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
25
26 printk(KERN_EMERG
27 "CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n",
28 smp_processor_id(), loaddr, lotype);
29
30 if (lotype & (1<<5)) {
31 printk(KERN_EMERG
32 "CPU#%d: Possible thermal failure (CPU on fire ?).\n",
33 smp_processor_id());
34 }
35
36 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
37}
38
39
40void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
41{
42 u32 l, h;
43
44
45 if (!mce_p5_enabled)
46 return;
47
48
49 if (!cpu_has(c, X86_FEATURE_MCE))
50 return;
51
52 machine_check_vector = pentium_machine_check;
53
54 wmb();
55
56
57 rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
58 rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
59 printk(KERN_INFO
60 "Intel old style machine check architecture supported.\n");
61
62
63 set_in_cr4(X86_CR4_MCE);
64 printk(KERN_INFO
65 "Intel old style machine check reporting enabled on CPU#%d.\n",
66 smp_processor_id());
67}
68