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15#include <linux/perf_event.h>
16#include <linux/capability.h>
17#include <linux/notifier.h>
18#include <linux/hardirq.h>
19#include <linux/kprobes.h>
20#include <linux/module.h>
21#include <linux/kdebug.h>
22#include <linux/sched.h>
23#include <linux/uaccess.h>
24#include <linux/slab.h>
25#include <linux/cpu.h>
26#include <linux/bitops.h>
27#include <linux/device.h>
28
29#include <asm/apic.h>
30#include <asm/stacktrace.h>
31#include <asm/nmi.h>
32#include <asm/smp.h>
33#include <asm/alternative.h>
34#include <asm/timer.h>
35#include <asm/desc.h>
36#include <asm/ldt.h>
37
38#include "perf_event.h"
39
40struct x86_pmu x86_pmu __read_mostly;
41
42DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
43 .enabled = 1,
44};
45
46u64 __read_mostly hw_cache_event_ids
47 [PERF_COUNT_HW_CACHE_MAX]
48 [PERF_COUNT_HW_CACHE_OP_MAX]
49 [PERF_COUNT_HW_CACHE_RESULT_MAX];
50u64 __read_mostly hw_cache_extra_regs
51 [PERF_COUNT_HW_CACHE_MAX]
52 [PERF_COUNT_HW_CACHE_OP_MAX]
53 [PERF_COUNT_HW_CACHE_RESULT_MAX];
54
55
56
57
58
59
60u64 x86_perf_event_update(struct perf_event *event)
61{
62 struct hw_perf_event *hwc = &event->hw;
63 int shift = 64 - x86_pmu.cntval_bits;
64 u64 prev_raw_count, new_raw_count;
65 int idx = hwc->idx;
66 s64 delta;
67
68 if (idx == INTEL_PMC_IDX_FIXED_BTS)
69 return 0;
70
71
72
73
74
75
76
77
78again:
79 prev_raw_count = local64_read(&hwc->prev_count);
80 rdpmcl(hwc->event_base_rdpmc, new_raw_count);
81
82 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
83 new_raw_count) != prev_raw_count)
84 goto again;
85
86
87
88
89
90
91
92
93
94 delta = (new_raw_count << shift) - (prev_raw_count << shift);
95 delta >>= shift;
96
97 local64_add(delta, &event->count);
98 local64_sub(delta, &hwc->period_left);
99
100 return new_raw_count;
101}
102
103
104
105
106static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
107{
108 struct hw_perf_event_extra *reg;
109 struct extra_reg *er;
110
111 reg = &event->hw.extra_reg;
112
113 if (!x86_pmu.extra_regs)
114 return 0;
115
116 for (er = x86_pmu.extra_regs; er->msr; er++) {
117 if (er->event != (config & er->config_mask))
118 continue;
119 if (event->attr.config1 & ~er->valid_mask)
120 return -EINVAL;
121
122 reg->idx = er->idx;
123 reg->config = event->attr.config1;
124 reg->reg = er->msr;
125 break;
126 }
127 return 0;
128}
129
130static atomic_t active_events;
131static DEFINE_MUTEX(pmc_reserve_mutex);
132
133#ifdef CONFIG_X86_LOCAL_APIC
134
135static bool reserve_pmc_hardware(void)
136{
137 int i;
138
139 for (i = 0; i < x86_pmu.num_counters; i++) {
140 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
141 goto perfctr_fail;
142 }
143
144 for (i = 0; i < x86_pmu.num_counters; i++) {
145 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
146 goto eventsel_fail;
147 }
148
149 return true;
150
151eventsel_fail:
152 for (i--; i >= 0; i--)
153 release_evntsel_nmi(x86_pmu_config_addr(i));
154
155 i = x86_pmu.num_counters;
156
157perfctr_fail:
158 for (i--; i >= 0; i--)
159 release_perfctr_nmi(x86_pmu_event_addr(i));
160
161 return false;
162}
163
164static void release_pmc_hardware(void)
165{
166 int i;
167
168 for (i = 0; i < x86_pmu.num_counters; i++) {
169 release_perfctr_nmi(x86_pmu_event_addr(i));
170 release_evntsel_nmi(x86_pmu_config_addr(i));
171 }
172}
173
174#else
175
176static bool reserve_pmc_hardware(void) { return true; }
177static void release_pmc_hardware(void) {}
178
179#endif
180
181static bool check_hw_exists(void)
182{
183 u64 val, val_fail, val_new= ~0;
184 int i, reg, reg_fail, ret = 0;
185 int bios_fail = 0;
186
187
188
189
190
191 for (i = 0; i < x86_pmu.num_counters; i++) {
192 reg = x86_pmu_config_addr(i);
193 ret = rdmsrl_safe(reg, &val);
194 if (ret)
195 goto msr_fail;
196 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
197 bios_fail = 1;
198 val_fail = val;
199 reg_fail = reg;
200 }
201 }
202
203 if (x86_pmu.num_counters_fixed) {
204 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
205 ret = rdmsrl_safe(reg, &val);
206 if (ret)
207 goto msr_fail;
208 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
209 if (val & (0x03 << i*4)) {
210 bios_fail = 1;
211 val_fail = val;
212 reg_fail = reg;
213 }
214 }
215 }
216
217
218
219
220
221
222 reg = x86_pmu_event_addr(0);
223 if (rdmsrl_safe(reg, &val))
224 goto msr_fail;
225 val ^= 0xffffUL;
226 ret = wrmsrl_safe(reg, val);
227 ret |= rdmsrl_safe(reg, &val_new);
228 if (ret || val != val_new)
229 goto msr_fail;
230
231
232
233
234 if (bios_fail) {
235 printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
236 printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail);
237 }
238
239 return true;
240
241msr_fail:
242 printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
243 printk(KERN_ERR "Failed to access perfctr msr (MSR %x is %Lx)\n", reg, val_new);
244
245 return false;
246}
247
248static void hw_perf_event_destroy(struct perf_event *event)
249{
250 if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
251 release_pmc_hardware();
252 release_ds_buffers();
253 mutex_unlock(&pmc_reserve_mutex);
254 }
255}
256
257static inline int x86_pmu_initialized(void)
258{
259 return x86_pmu.handle_irq != NULL;
260}
261
262static inline int
263set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
264{
265 struct perf_event_attr *attr = &event->attr;
266 unsigned int cache_type, cache_op, cache_result;
267 u64 config, val;
268
269 config = attr->config;
270
271 cache_type = (config >> 0) & 0xff;
272 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
273 return -EINVAL;
274
275 cache_op = (config >> 8) & 0xff;
276 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
277 return -EINVAL;
278
279 cache_result = (config >> 16) & 0xff;
280 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
281 return -EINVAL;
282
283 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
284
285 if (val == 0)
286 return -ENOENT;
287
288 if (val == -1)
289 return -EINVAL;
290
291 hwc->config |= val;
292 attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
293 return x86_pmu_extra_regs(val, event);
294}
295
296int x86_setup_perfctr(struct perf_event *event)
297{
298 struct perf_event_attr *attr = &event->attr;
299 struct hw_perf_event *hwc = &event->hw;
300 u64 config;
301
302 if (!is_sampling_event(event)) {
303 hwc->sample_period = x86_pmu.max_period;
304 hwc->last_period = hwc->sample_period;
305 local64_set(&hwc->period_left, hwc->sample_period);
306 } else {
307
308
309
310
311
312
313 if (!x86_pmu.apic)
314 return -EOPNOTSUPP;
315 }
316
317 if (attr->type == PERF_TYPE_RAW)
318 return x86_pmu_extra_regs(event->attr.config, event);
319
320 if (attr->type == PERF_TYPE_HW_CACHE)
321 return set_ext_hw_attr(hwc, event);
322
323 if (attr->config >= x86_pmu.max_events)
324 return -EINVAL;
325
326
327
328
329 config = x86_pmu.event_map(attr->config);
330
331 if (config == 0)
332 return -ENOENT;
333
334 if (config == -1LL)
335 return -EINVAL;
336
337
338
339
340 if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
341 !attr->freq && hwc->sample_period == 1) {
342
343 if (!x86_pmu.bts_active)
344 return -EOPNOTSUPP;
345
346
347 if (!attr->exclude_kernel)
348 return -EOPNOTSUPP;
349 }
350
351 hwc->config |= config;
352
353 return 0;
354}
355
356
357
358
359
360
361
362static inline int precise_br_compat(struct perf_event *event)
363{
364 u64 m = event->attr.branch_sample_type;
365 u64 b = 0;
366
367
368 if (!(m & PERF_SAMPLE_BRANCH_ANY))
369 return 0;
370
371 m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
372
373 if (!event->attr.exclude_user)
374 b |= PERF_SAMPLE_BRANCH_USER;
375
376 if (!event->attr.exclude_kernel)
377 b |= PERF_SAMPLE_BRANCH_KERNEL;
378
379
380
381
382
383 return m == b;
384}
385
386int x86_pmu_hw_config(struct perf_event *event)
387{
388 if (event->attr.precise_ip) {
389 int precise = 0;
390
391
392 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
393 precise++;
394
395
396 if (x86_pmu.lbr_nr)
397 precise++;
398 }
399
400 if (event->attr.precise_ip > precise)
401 return -EOPNOTSUPP;
402
403
404
405
406 if (event->attr.precise_ip > 1 &&
407 x86_pmu.intel_cap.pebs_format < 2) {
408 u64 *br_type = &event->attr.branch_sample_type;
409
410 if (has_branch_stack(event)) {
411 if (!precise_br_compat(event))
412 return -EOPNOTSUPP;
413
414
415
416 } else {
417
418
419
420
421
422
423
424 *br_type = PERF_SAMPLE_BRANCH_ANY;
425
426 if (!event->attr.exclude_user)
427 *br_type |= PERF_SAMPLE_BRANCH_USER;
428
429 if (!event->attr.exclude_kernel)
430 *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
431 }
432 }
433 }
434
435
436
437
438
439 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
440
441
442
443
444 if (!event->attr.exclude_user)
445 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
446 if (!event->attr.exclude_kernel)
447 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
448
449 if (event->attr.type == PERF_TYPE_RAW)
450 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
451
452 return x86_setup_perfctr(event);
453}
454
455
456
457
458static int __x86_pmu_event_init(struct perf_event *event)
459{
460 int err;
461
462 if (!x86_pmu_initialized())
463 return -ENODEV;
464
465 err = 0;
466 if (!atomic_inc_not_zero(&active_events)) {
467 mutex_lock(&pmc_reserve_mutex);
468 if (atomic_read(&active_events) == 0) {
469 if (!reserve_pmc_hardware())
470 err = -EBUSY;
471 else
472 reserve_ds_buffers();
473 }
474 if (!err)
475 atomic_inc(&active_events);
476 mutex_unlock(&pmc_reserve_mutex);
477 }
478 if (err)
479 return err;
480
481 event->destroy = hw_perf_event_destroy;
482
483 event->hw.idx = -1;
484 event->hw.last_cpu = -1;
485 event->hw.last_tag = ~0ULL;
486
487
488 event->hw.extra_reg.idx = EXTRA_REG_NONE;
489 event->hw.branch_reg.idx = EXTRA_REG_NONE;
490
491 return x86_pmu.hw_config(event);
492}
493
494void x86_pmu_disable_all(void)
495{
496 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
497 int idx;
498
499 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
500 u64 val;
501
502 if (!test_bit(idx, cpuc->active_mask))
503 continue;
504 rdmsrl(x86_pmu_config_addr(idx), val);
505 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
506 continue;
507 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
508 wrmsrl(x86_pmu_config_addr(idx), val);
509 }
510}
511
512static void x86_pmu_disable(struct pmu *pmu)
513{
514 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
515
516 if (!x86_pmu_initialized())
517 return;
518
519 if (!cpuc->enabled)
520 return;
521
522 cpuc->n_added = 0;
523 cpuc->enabled = 0;
524 barrier();
525
526 x86_pmu.disable_all();
527}
528
529void x86_pmu_enable_all(int added)
530{
531 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
532 int idx;
533
534 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
535 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
536
537 if (!test_bit(idx, cpuc->active_mask))
538 continue;
539
540 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
541 }
542}
543
544static struct pmu pmu;
545
546static inline int is_x86_event(struct perf_event *event)
547{
548 return event->pmu == &pmu;
549}
550
551
552
553
554
555
556
557
558struct sched_state {
559 int weight;
560 int event;
561 int counter;
562 int unassigned;
563 unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
564};
565
566
567#define SCHED_STATES_MAX 2
568
569struct perf_sched {
570 int max_weight;
571 int max_events;
572 struct perf_event **events;
573 struct sched_state state;
574 int saved_states;
575 struct sched_state saved[SCHED_STATES_MAX];
576};
577
578
579
580
581static void perf_sched_init(struct perf_sched *sched, struct perf_event **events,
582 int num, int wmin, int wmax)
583{
584 int idx;
585
586 memset(sched, 0, sizeof(*sched));
587 sched->max_events = num;
588 sched->max_weight = wmax;
589 sched->events = events;
590
591 for (idx = 0; idx < num; idx++) {
592 if (events[idx]->hw.constraint->weight == wmin)
593 break;
594 }
595
596 sched->state.event = idx;
597 sched->state.weight = wmin;
598 sched->state.unassigned = num;
599}
600
601static void perf_sched_save_state(struct perf_sched *sched)
602{
603 if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
604 return;
605
606 sched->saved[sched->saved_states] = sched->state;
607 sched->saved_states++;
608}
609
610static bool perf_sched_restore_state(struct perf_sched *sched)
611{
612 if (!sched->saved_states)
613 return false;
614
615 sched->saved_states--;
616 sched->state = sched->saved[sched->saved_states];
617
618
619 clear_bit(sched->state.counter++, sched->state.used);
620
621 return true;
622}
623
624
625
626
627
628static bool __perf_sched_find_counter(struct perf_sched *sched)
629{
630 struct event_constraint *c;
631 int idx;
632
633 if (!sched->state.unassigned)
634 return false;
635
636 if (sched->state.event >= sched->max_events)
637 return false;
638
639 c = sched->events[sched->state.event]->hw.constraint;
640
641 if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
642 idx = INTEL_PMC_IDX_FIXED;
643 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
644 if (!__test_and_set_bit(idx, sched->state.used))
645 goto done;
646 }
647 }
648
649 idx = sched->state.counter;
650 for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
651 if (!__test_and_set_bit(idx, sched->state.used))
652 goto done;
653 }
654
655 return false;
656
657done:
658 sched->state.counter = idx;
659
660 if (c->overlap)
661 perf_sched_save_state(sched);
662
663 return true;
664}
665
666static bool perf_sched_find_counter(struct perf_sched *sched)
667{
668 while (!__perf_sched_find_counter(sched)) {
669 if (!perf_sched_restore_state(sched))
670 return false;
671 }
672
673 return true;
674}
675
676
677
678
679
680static bool perf_sched_next_event(struct perf_sched *sched)
681{
682 struct event_constraint *c;
683
684 if (!sched->state.unassigned || !--sched->state.unassigned)
685 return false;
686
687 do {
688
689 sched->state.event++;
690 if (sched->state.event >= sched->max_events) {
691
692 sched->state.event = 0;
693 sched->state.weight++;
694 if (sched->state.weight > sched->max_weight)
695 return false;
696 }
697 c = sched->events[sched->state.event]->hw.constraint;
698 } while (c->weight != sched->state.weight);
699
700 sched->state.counter = 0;
701
702 return true;
703}
704
705
706
707
708int perf_assign_events(struct perf_event **events, int n,
709 int wmin, int wmax, int *assign)
710{
711 struct perf_sched sched;
712
713 perf_sched_init(&sched, events, n, wmin, wmax);
714
715 do {
716 if (!perf_sched_find_counter(&sched))
717 break;
718 if (assign)
719 assign[sched.state.event] = sched.state.counter;
720 } while (perf_sched_next_event(&sched));
721
722 return sched.state.unassigned;
723}
724
725int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
726{
727 struct event_constraint *c;
728 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
729 struct perf_event *e;
730 int i, wmin, wmax, num = 0;
731 struct hw_perf_event *hwc;
732
733 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
734
735 for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
736 hwc = &cpuc->event_list[i]->hw;
737 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
738 hwc->constraint = c;
739
740 wmin = min(wmin, c->weight);
741 wmax = max(wmax, c->weight);
742 }
743
744
745
746
747 for (i = 0; i < n; i++) {
748 hwc = &cpuc->event_list[i]->hw;
749 c = hwc->constraint;
750
751
752 if (hwc->idx == -1)
753 break;
754
755
756 if (!test_bit(hwc->idx, c->idxmsk))
757 break;
758
759
760 if (test_bit(hwc->idx, used_mask))
761 break;
762
763 __set_bit(hwc->idx, used_mask);
764 if (assign)
765 assign[i] = hwc->idx;
766 }
767
768
769 if (i != n)
770 num = perf_assign_events(cpuc->event_list, n, wmin,
771 wmax, assign);
772
773
774
775
776
777 if (!num && assign) {
778 for (i = 0; i < n; i++) {
779 e = cpuc->event_list[i];
780 e->hw.flags |= PERF_X86_EVENT_COMMITTED;
781 }
782 }
783
784
785
786
787 if (!assign || num) {
788 for (i = 0; i < n; i++) {
789 e = cpuc->event_list[i];
790
791
792
793
794 if ((e->hw.flags & PERF_X86_EVENT_COMMITTED))
795 continue;
796
797 if (x86_pmu.put_event_constraints)
798 x86_pmu.put_event_constraints(cpuc, e);
799 }
800 }
801 return num ? -EINVAL : 0;
802}
803
804
805
806
807
808static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
809{
810 struct perf_event *event;
811 int n, max_count;
812
813 max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
814
815
816 n = cpuc->n_events;
817
818 if (is_x86_event(leader)) {
819 if (n >= max_count)
820 return -EINVAL;
821 cpuc->event_list[n] = leader;
822 n++;
823 }
824 if (!dogrp)
825 return n;
826
827 list_for_each_entry(event, &leader->sibling_list, group_entry) {
828 if (!is_x86_event(event) ||
829 event->state <= PERF_EVENT_STATE_OFF)
830 continue;
831
832 if (n >= max_count)
833 return -EINVAL;
834
835 cpuc->event_list[n] = event;
836 n++;
837 }
838 return n;
839}
840
841static inline void x86_assign_hw_event(struct perf_event *event,
842 struct cpu_hw_events *cpuc, int i)
843{
844 struct hw_perf_event *hwc = &event->hw;
845
846 hwc->idx = cpuc->assign[i];
847 hwc->last_cpu = smp_processor_id();
848 hwc->last_tag = ++cpuc->tags[i];
849
850 if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
851 hwc->config_base = 0;
852 hwc->event_base = 0;
853 } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
854 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
855 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
856 hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
857 } else {
858 hwc->config_base = x86_pmu_config_addr(hwc->idx);
859 hwc->event_base = x86_pmu_event_addr(hwc->idx);
860 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
861 }
862}
863
864static inline int match_prev_assignment(struct hw_perf_event *hwc,
865 struct cpu_hw_events *cpuc,
866 int i)
867{
868 return hwc->idx == cpuc->assign[i] &&
869 hwc->last_cpu == smp_processor_id() &&
870 hwc->last_tag == cpuc->tags[i];
871}
872
873static void x86_pmu_start(struct perf_event *event, int flags);
874
875static void x86_pmu_enable(struct pmu *pmu)
876{
877 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
878 struct perf_event *event;
879 struct hw_perf_event *hwc;
880 int i, added = cpuc->n_added;
881
882 if (!x86_pmu_initialized())
883 return;
884
885 if (cpuc->enabled)
886 return;
887
888 if (cpuc->n_added) {
889 int n_running = cpuc->n_events - cpuc->n_added;
890
891
892
893
894
895
896
897 for (i = 0; i < n_running; i++) {
898 event = cpuc->event_list[i];
899 hwc = &event->hw;
900
901
902
903
904
905
906
907 if (hwc->idx == -1 ||
908 match_prev_assignment(hwc, cpuc, i))
909 continue;
910
911
912
913
914
915 if (hwc->state & PERF_HES_STOPPED)
916 hwc->state |= PERF_HES_ARCH;
917
918 x86_pmu_stop(event, PERF_EF_UPDATE);
919 }
920
921 for (i = 0; i < cpuc->n_events; i++) {
922 event = cpuc->event_list[i];
923 hwc = &event->hw;
924
925 if (!match_prev_assignment(hwc, cpuc, i))
926 x86_assign_hw_event(event, cpuc, i);
927 else if (i < n_running)
928 continue;
929
930 if (hwc->state & PERF_HES_ARCH)
931 continue;
932
933 x86_pmu_start(event, PERF_EF_RELOAD);
934 }
935 cpuc->n_added = 0;
936 perf_events_lapic_init();
937 }
938
939 cpuc->enabled = 1;
940 barrier();
941
942 x86_pmu.enable_all(added);
943}
944
945static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
946
947
948
949
950
951int x86_perf_event_set_period(struct perf_event *event)
952{
953 struct hw_perf_event *hwc = &event->hw;
954 s64 left = local64_read(&hwc->period_left);
955 s64 period = hwc->sample_period;
956 int ret = 0, idx = hwc->idx;
957
958 if (idx == INTEL_PMC_IDX_FIXED_BTS)
959 return 0;
960
961
962
963
964 if (unlikely(left <= -period)) {
965 left = period;
966 local64_set(&hwc->period_left, left);
967 hwc->last_period = period;
968 ret = 1;
969 }
970
971 if (unlikely(left <= 0)) {
972 left += period;
973 local64_set(&hwc->period_left, left);
974 hwc->last_period = period;
975 ret = 1;
976 }
977
978
979
980 if (unlikely(left < 2))
981 left = 2;
982
983 if (left > x86_pmu.max_period)
984 left = x86_pmu.max_period;
985
986 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
987
988
989
990
991
992 local64_set(&hwc->prev_count, (u64)-left);
993
994 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
995
996
997
998
999
1000
1001 if (x86_pmu.perfctr_second_write) {
1002 wrmsrl(hwc->event_base,
1003 (u64)(-left) & x86_pmu.cntval_mask);
1004 }
1005
1006 perf_event_update_userpage(event);
1007
1008 return ret;
1009}
1010
1011void x86_pmu_enable_event(struct perf_event *event)
1012{
1013 if (__this_cpu_read(cpu_hw_events.enabled))
1014 __x86_pmu_enable_event(&event->hw,
1015 ARCH_PERFMON_EVENTSEL_ENABLE);
1016}
1017
1018
1019
1020
1021
1022
1023
1024static int x86_pmu_add(struct perf_event *event, int flags)
1025{
1026 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1027 struct hw_perf_event *hwc;
1028 int assign[X86_PMC_IDX_MAX];
1029 int n, n0, ret;
1030
1031 hwc = &event->hw;
1032
1033 perf_pmu_disable(event->pmu);
1034 n0 = cpuc->n_events;
1035 ret = n = collect_events(cpuc, event, false);
1036 if (ret < 0)
1037 goto out;
1038
1039 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1040 if (!(flags & PERF_EF_START))
1041 hwc->state |= PERF_HES_ARCH;
1042
1043
1044
1045
1046
1047
1048 if (cpuc->group_flag & PERF_EVENT_TXN)
1049 goto done_collect;
1050
1051 ret = x86_pmu.schedule_events(cpuc, n, assign);
1052 if (ret)
1053 goto out;
1054
1055
1056
1057
1058 memcpy(cpuc->assign, assign, n*sizeof(int));
1059
1060done_collect:
1061 cpuc->n_events = n;
1062 cpuc->n_added += n - n0;
1063 cpuc->n_txn += n - n0;
1064
1065 ret = 0;
1066out:
1067 perf_pmu_enable(event->pmu);
1068 return ret;
1069}
1070
1071static void x86_pmu_start(struct perf_event *event, int flags)
1072{
1073 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1074 int idx = event->hw.idx;
1075
1076 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1077 return;
1078
1079 if (WARN_ON_ONCE(idx == -1))
1080 return;
1081
1082 if (flags & PERF_EF_RELOAD) {
1083 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1084 x86_perf_event_set_period(event);
1085 }
1086
1087 event->hw.state = 0;
1088
1089 cpuc->events[idx] = event;
1090 __set_bit(idx, cpuc->active_mask);
1091 __set_bit(idx, cpuc->running);
1092 x86_pmu.enable(event);
1093 perf_event_update_userpage(event);
1094}
1095
1096void perf_event_print_debug(void)
1097{
1098 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1099 u64 pebs;
1100 struct cpu_hw_events *cpuc;
1101 unsigned long flags;
1102 int cpu, idx;
1103
1104 if (!x86_pmu.num_counters)
1105 return;
1106
1107 local_irq_save(flags);
1108
1109 cpu = smp_processor_id();
1110 cpuc = &per_cpu(cpu_hw_events, cpu);
1111
1112 if (x86_pmu.version >= 2) {
1113 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1114 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1115 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1116 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1117 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1118
1119 pr_info("\n");
1120 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1121 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1122 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1123 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1124 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1125 }
1126 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1127
1128 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1129 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1130 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1131
1132 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1133
1134 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1135 cpu, idx, pmc_ctrl);
1136 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1137 cpu, idx, pmc_count);
1138 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1139 cpu, idx, prev_left);
1140 }
1141 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1142 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1143
1144 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1145 cpu, idx, pmc_count);
1146 }
1147 local_irq_restore(flags);
1148}
1149
1150void x86_pmu_stop(struct perf_event *event, int flags)
1151{
1152 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1153 struct hw_perf_event *hwc = &event->hw;
1154
1155 if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1156 x86_pmu.disable(event);
1157 cpuc->events[hwc->idx] = NULL;
1158 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1159 hwc->state |= PERF_HES_STOPPED;
1160 }
1161
1162 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1163
1164
1165
1166
1167 x86_perf_event_update(event);
1168 hwc->state |= PERF_HES_UPTODATE;
1169 }
1170}
1171
1172static void x86_pmu_del(struct perf_event *event, int flags)
1173{
1174 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1175 int i;
1176
1177
1178
1179
1180 event->hw.flags &= ~PERF_X86_EVENT_COMMITTED;
1181
1182
1183
1184
1185
1186
1187 if (cpuc->group_flag & PERF_EVENT_TXN)
1188 return;
1189
1190 x86_pmu_stop(event, PERF_EF_UPDATE);
1191
1192 for (i = 0; i < cpuc->n_events; i++) {
1193 if (event == cpuc->event_list[i]) {
1194
1195 if (x86_pmu.put_event_constraints)
1196 x86_pmu.put_event_constraints(cpuc, event);
1197
1198 while (++i < cpuc->n_events)
1199 cpuc->event_list[i-1] = cpuc->event_list[i];
1200
1201 --cpuc->n_events;
1202 break;
1203 }
1204 }
1205 perf_event_update_userpage(event);
1206}
1207
1208int x86_pmu_handle_irq(struct pt_regs *regs)
1209{
1210 struct perf_sample_data data;
1211 struct cpu_hw_events *cpuc;
1212 struct perf_event *event;
1213 int idx, handled = 0;
1214 u64 val;
1215
1216 cpuc = &__get_cpu_var(cpu_hw_events);
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226 apic_write(APIC_LVTPC, APIC_DM_NMI);
1227
1228 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1229 if (!test_bit(idx, cpuc->active_mask)) {
1230
1231
1232
1233
1234
1235 if (__test_and_clear_bit(idx, cpuc->running))
1236 handled++;
1237 continue;
1238 }
1239
1240 event = cpuc->events[idx];
1241
1242 val = x86_perf_event_update(event);
1243 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1244 continue;
1245
1246
1247
1248
1249 handled++;
1250 perf_sample_data_init(&data, 0, event->hw.last_period);
1251
1252 if (!x86_perf_event_set_period(event))
1253 continue;
1254
1255 if (perf_event_overflow(event, &data, regs))
1256 x86_pmu_stop(event, 0);
1257 }
1258
1259 if (handled)
1260 inc_irq_stat(apic_perf_irqs);
1261
1262 return handled;
1263}
1264
1265void perf_events_lapic_init(void)
1266{
1267 if (!x86_pmu.apic || !x86_pmu_initialized())
1268 return;
1269
1270
1271
1272
1273 apic_write(APIC_LVTPC, APIC_DM_NMI);
1274}
1275
1276static int __kprobes
1277perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1278{
1279 int ret;
1280 u64 start_clock;
1281 u64 finish_clock;
1282
1283 if (!atomic_read(&active_events))
1284 return NMI_DONE;
1285
1286 start_clock = local_clock();
1287 ret = x86_pmu.handle_irq(regs);
1288 finish_clock = local_clock();
1289
1290 perf_sample_event_took(finish_clock - start_clock);
1291
1292 return ret;
1293}
1294
1295struct event_constraint emptyconstraint;
1296struct event_constraint unconstrained;
1297
1298static int
1299x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1300{
1301 unsigned int cpu = (long)hcpu;
1302 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1303 int ret = NOTIFY_OK;
1304
1305 switch (action & ~CPU_TASKS_FROZEN) {
1306 case CPU_UP_PREPARE:
1307 cpuc->kfree_on_online = NULL;
1308 if (x86_pmu.cpu_prepare)
1309 ret = x86_pmu.cpu_prepare(cpu);
1310 break;
1311
1312 case CPU_STARTING:
1313 if (x86_pmu.attr_rdpmc)
1314 set_in_cr4(X86_CR4_PCE);
1315 if (x86_pmu.cpu_starting)
1316 x86_pmu.cpu_starting(cpu);
1317 break;
1318
1319 case CPU_ONLINE:
1320 kfree(cpuc->kfree_on_online);
1321 break;
1322
1323 case CPU_DYING:
1324 if (x86_pmu.cpu_dying)
1325 x86_pmu.cpu_dying(cpu);
1326 break;
1327
1328 case CPU_UP_CANCELED:
1329 case CPU_DEAD:
1330 if (x86_pmu.cpu_dead)
1331 x86_pmu.cpu_dead(cpu);
1332 break;
1333
1334 default:
1335 break;
1336 }
1337
1338 return ret;
1339}
1340
1341static void __init pmu_check_apic(void)
1342{
1343 if (cpu_has_apic)
1344 return;
1345
1346 x86_pmu.apic = 0;
1347 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1348 pr_info("no hardware sampling interrupt available.\n");
1349}
1350
1351static struct attribute_group x86_pmu_format_group = {
1352 .name = "format",
1353 .attrs = NULL,
1354};
1355
1356
1357
1358
1359
1360static void __init filter_events(struct attribute **attrs)
1361{
1362 struct device_attribute *d;
1363 struct perf_pmu_events_attr *pmu_attr;
1364 int i, j;
1365
1366 for (i = 0; attrs[i]; i++) {
1367 d = (struct device_attribute *)attrs[i];
1368 pmu_attr = container_of(d, struct perf_pmu_events_attr, attr);
1369
1370 if (pmu_attr->event_str)
1371 continue;
1372 if (x86_pmu.event_map(i))
1373 continue;
1374
1375 for (j = i; attrs[j]; j++)
1376 attrs[j] = attrs[j + 1];
1377
1378
1379 i--;
1380 }
1381}
1382
1383
1384static __init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
1385{
1386 struct attribute **new;
1387 int j, i;
1388
1389 for (j = 0; a[j]; j++)
1390 ;
1391 for (i = 0; b[i]; i++)
1392 j++;
1393 j++;
1394
1395 new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
1396 if (!new)
1397 return NULL;
1398
1399 j = 0;
1400 for (i = 0; a[i]; i++)
1401 new[j++] = a[i];
1402 for (i = 0; b[i]; i++)
1403 new[j++] = b[i];
1404 new[j] = NULL;
1405
1406 return new;
1407}
1408
1409ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
1410 char *page)
1411{
1412 struct perf_pmu_events_attr *pmu_attr = \
1413 container_of(attr, struct perf_pmu_events_attr, attr);
1414 u64 config = x86_pmu.event_map(pmu_attr->id);
1415
1416
1417 if (pmu_attr->event_str)
1418 return sprintf(page, "%s", pmu_attr->event_str);
1419
1420 return x86_pmu.events_sysfs_show(page, config);
1421}
1422
1423EVENT_ATTR(cpu-cycles, CPU_CYCLES );
1424EVENT_ATTR(instructions, INSTRUCTIONS );
1425EVENT_ATTR(cache-references, CACHE_REFERENCES );
1426EVENT_ATTR(cache-misses, CACHE_MISSES );
1427EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS );
1428EVENT_ATTR(branch-misses, BRANCH_MISSES );
1429EVENT_ATTR(bus-cycles, BUS_CYCLES );
1430EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND );
1431EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND );
1432EVENT_ATTR(ref-cycles, REF_CPU_CYCLES );
1433
1434static struct attribute *empty_attrs;
1435
1436static struct attribute *events_attr[] = {
1437 EVENT_PTR(CPU_CYCLES),
1438 EVENT_PTR(INSTRUCTIONS),
1439 EVENT_PTR(CACHE_REFERENCES),
1440 EVENT_PTR(CACHE_MISSES),
1441 EVENT_PTR(BRANCH_INSTRUCTIONS),
1442 EVENT_PTR(BRANCH_MISSES),
1443 EVENT_PTR(BUS_CYCLES),
1444 EVENT_PTR(STALLED_CYCLES_FRONTEND),
1445 EVENT_PTR(STALLED_CYCLES_BACKEND),
1446 EVENT_PTR(REF_CPU_CYCLES),
1447 NULL,
1448};
1449
1450static struct attribute_group x86_pmu_events_group = {
1451 .name = "events",
1452 .attrs = events_attr,
1453};
1454
1455ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1456{
1457 u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1458 u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1459 bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1460 bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1461 bool any = (config & ARCH_PERFMON_EVENTSEL_ANY);
1462 bool inv = (config & ARCH_PERFMON_EVENTSEL_INV);
1463 ssize_t ret;
1464
1465
1466
1467
1468
1469 ret = sprintf(page, "event=0x%02llx", event);
1470
1471 if (umask)
1472 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1473
1474 if (edge)
1475 ret += sprintf(page + ret, ",edge");
1476
1477 if (pc)
1478 ret += sprintf(page + ret, ",pc");
1479
1480 if (any)
1481 ret += sprintf(page + ret, ",any");
1482
1483 if (inv)
1484 ret += sprintf(page + ret, ",inv");
1485
1486 if (cmask)
1487 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1488
1489 ret += sprintf(page + ret, "\n");
1490
1491 return ret;
1492}
1493
1494static int __init init_hw_perf_events(void)
1495{
1496 struct x86_pmu_quirk *quirk;
1497 int err;
1498
1499 pr_info("Performance Events: ");
1500
1501 switch (boot_cpu_data.x86_vendor) {
1502 case X86_VENDOR_INTEL:
1503 err = intel_pmu_init();
1504 break;
1505 case X86_VENDOR_AMD:
1506 err = amd_pmu_init();
1507 break;
1508 default:
1509 return 0;
1510 }
1511 if (err != 0) {
1512 pr_cont("no PMU driver, software events only.\n");
1513 return 0;
1514 }
1515
1516 pmu_check_apic();
1517
1518
1519 if (!check_hw_exists())
1520 return 0;
1521
1522 pr_cont("%s PMU driver.\n", x86_pmu.name);
1523
1524 for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1525 quirk->func();
1526
1527 if (!x86_pmu.intel_ctrl)
1528 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1529
1530 perf_events_lapic_init();
1531 register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1532
1533 unconstrained = (struct event_constraint)
1534 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1535 0, x86_pmu.num_counters, 0, 0);
1536
1537 x86_pmu.attr_rdpmc = 1;
1538 x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1539
1540 if (x86_pmu.event_attrs)
1541 x86_pmu_events_group.attrs = x86_pmu.event_attrs;
1542
1543 if (!x86_pmu.events_sysfs_show)
1544 x86_pmu_events_group.attrs = &empty_attrs;
1545 else
1546 filter_events(x86_pmu_events_group.attrs);
1547
1548 if (x86_pmu.cpu_events) {
1549 struct attribute **tmp;
1550
1551 tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
1552 if (!WARN_ON(!tmp))
1553 x86_pmu_events_group.attrs = tmp;
1554 }
1555
1556 pr_info("... version: %d\n", x86_pmu.version);
1557 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
1558 pr_info("... generic registers: %d\n", x86_pmu.num_counters);
1559 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
1560 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1561 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed);
1562 pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl);
1563
1564 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1565 perf_cpu_notifier(x86_pmu_notifier);
1566
1567 return 0;
1568}
1569early_initcall(init_hw_perf_events);
1570
1571static inline void x86_pmu_read(struct perf_event *event)
1572{
1573 x86_perf_event_update(event);
1574}
1575
1576
1577
1578
1579
1580
1581static void x86_pmu_start_txn(struct pmu *pmu)
1582{
1583 perf_pmu_disable(pmu);
1584 __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
1585 __this_cpu_write(cpu_hw_events.n_txn, 0);
1586}
1587
1588
1589
1590
1591
1592
1593static void x86_pmu_cancel_txn(struct pmu *pmu)
1594{
1595 __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1596
1597
1598
1599 __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1600 __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1601 perf_pmu_enable(pmu);
1602}
1603
1604
1605
1606
1607
1608
1609static int x86_pmu_commit_txn(struct pmu *pmu)
1610{
1611 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1612 int assign[X86_PMC_IDX_MAX];
1613 int n, ret;
1614
1615 n = cpuc->n_events;
1616
1617 if (!x86_pmu_initialized())
1618 return -EAGAIN;
1619
1620 ret = x86_pmu.schedule_events(cpuc, n, assign);
1621 if (ret)
1622 return ret;
1623
1624
1625
1626
1627
1628 memcpy(cpuc->assign, assign, n*sizeof(int));
1629
1630 cpuc->group_flag &= ~PERF_EVENT_TXN;
1631 perf_pmu_enable(pmu);
1632 return 0;
1633}
1634
1635
1636
1637
1638
1639
1640
1641
1642static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1643{
1644 kfree(cpuc->shared_regs);
1645 kfree(cpuc);
1646}
1647
1648static struct cpu_hw_events *allocate_fake_cpuc(void)
1649{
1650 struct cpu_hw_events *cpuc;
1651 int cpu = raw_smp_processor_id();
1652
1653 cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1654 if (!cpuc)
1655 return ERR_PTR(-ENOMEM);
1656
1657
1658 if (x86_pmu.extra_regs) {
1659 cpuc->shared_regs = allocate_shared_regs(cpu);
1660 if (!cpuc->shared_regs)
1661 goto error;
1662 }
1663 cpuc->is_fake = 1;
1664 return cpuc;
1665error:
1666 free_fake_cpuc(cpuc);
1667 return ERR_PTR(-ENOMEM);
1668}
1669
1670
1671
1672
1673static int validate_event(struct perf_event *event)
1674{
1675 struct cpu_hw_events *fake_cpuc;
1676 struct event_constraint *c;
1677 int ret = 0;
1678
1679 fake_cpuc = allocate_fake_cpuc();
1680 if (IS_ERR(fake_cpuc))
1681 return PTR_ERR(fake_cpuc);
1682
1683 c = x86_pmu.get_event_constraints(fake_cpuc, event);
1684
1685 if (!c || !c->weight)
1686 ret = -EINVAL;
1687
1688 if (x86_pmu.put_event_constraints)
1689 x86_pmu.put_event_constraints(fake_cpuc, event);
1690
1691 free_fake_cpuc(fake_cpuc);
1692
1693 return ret;
1694}
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707static int validate_group(struct perf_event *event)
1708{
1709 struct perf_event *leader = event->group_leader;
1710 struct cpu_hw_events *fake_cpuc;
1711 int ret = -EINVAL, n;
1712
1713 fake_cpuc = allocate_fake_cpuc();
1714 if (IS_ERR(fake_cpuc))
1715 return PTR_ERR(fake_cpuc);
1716
1717
1718
1719
1720
1721
1722 n = collect_events(fake_cpuc, leader, true);
1723 if (n < 0)
1724 goto out;
1725
1726 fake_cpuc->n_events = n;
1727 n = collect_events(fake_cpuc, event, false);
1728 if (n < 0)
1729 goto out;
1730
1731 fake_cpuc->n_events = n;
1732
1733 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1734
1735out:
1736 free_fake_cpuc(fake_cpuc);
1737 return ret;
1738}
1739
1740static int x86_pmu_event_init(struct perf_event *event)
1741{
1742 struct pmu *tmp;
1743 int err;
1744
1745 switch (event->attr.type) {
1746 case PERF_TYPE_RAW:
1747 case PERF_TYPE_HARDWARE:
1748 case PERF_TYPE_HW_CACHE:
1749 break;
1750
1751 default:
1752 return -ENOENT;
1753 }
1754
1755 err = __x86_pmu_event_init(event);
1756 if (!err) {
1757
1758
1759
1760
1761
1762 tmp = event->pmu;
1763 event->pmu = &pmu;
1764
1765 if (event->group_leader != event)
1766 err = validate_group(event);
1767 else
1768 err = validate_event(event);
1769
1770 event->pmu = tmp;
1771 }
1772 if (err) {
1773 if (event->destroy)
1774 event->destroy(event);
1775 }
1776
1777 return err;
1778}
1779
1780static int x86_pmu_event_idx(struct perf_event *event)
1781{
1782 int idx = event->hw.idx;
1783
1784 if (!x86_pmu.attr_rdpmc)
1785 return 0;
1786
1787 if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
1788 idx -= INTEL_PMC_IDX_FIXED;
1789 idx |= 1 << 30;
1790 }
1791
1792 return idx + 1;
1793}
1794
1795static ssize_t get_attr_rdpmc(struct device *cdev,
1796 struct device_attribute *attr,
1797 char *buf)
1798{
1799 return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
1800}
1801
1802static void change_rdpmc(void *info)
1803{
1804 bool enable = !!(unsigned long)info;
1805
1806 if (enable)
1807 set_in_cr4(X86_CR4_PCE);
1808 else
1809 clear_in_cr4(X86_CR4_PCE);
1810}
1811
1812static ssize_t set_attr_rdpmc(struct device *cdev,
1813 struct device_attribute *attr,
1814 const char *buf, size_t count)
1815{
1816 unsigned long val;
1817 ssize_t ret;
1818
1819 ret = kstrtoul(buf, 0, &val);
1820 if (ret)
1821 return ret;
1822
1823 if (!!val != !!x86_pmu.attr_rdpmc) {
1824 x86_pmu.attr_rdpmc = !!val;
1825 smp_call_function(change_rdpmc, (void *)val, 1);
1826 }
1827
1828 return count;
1829}
1830
1831static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
1832
1833static struct attribute *x86_pmu_attrs[] = {
1834 &dev_attr_rdpmc.attr,
1835 NULL,
1836};
1837
1838static struct attribute_group x86_pmu_attr_group = {
1839 .attrs = x86_pmu_attrs,
1840};
1841
1842static const struct attribute_group *x86_pmu_attr_groups[] = {
1843 &x86_pmu_attr_group,
1844 &x86_pmu_format_group,
1845 &x86_pmu_events_group,
1846 NULL,
1847};
1848
1849static void x86_pmu_flush_branch_stack(void)
1850{
1851 if (x86_pmu.flush_branch_stack)
1852 x86_pmu.flush_branch_stack();
1853}
1854
1855void perf_check_microcode(void)
1856{
1857 if (x86_pmu.check_microcode)
1858 x86_pmu.check_microcode();
1859}
1860EXPORT_SYMBOL_GPL(perf_check_microcode);
1861
1862static struct pmu pmu = {
1863 .pmu_enable = x86_pmu_enable,
1864 .pmu_disable = x86_pmu_disable,
1865
1866 .attr_groups = x86_pmu_attr_groups,
1867
1868 .event_init = x86_pmu_event_init,
1869
1870 .add = x86_pmu_add,
1871 .del = x86_pmu_del,
1872 .start = x86_pmu_start,
1873 .stop = x86_pmu_stop,
1874 .read = x86_pmu_read,
1875
1876 .start_txn = x86_pmu_start_txn,
1877 .cancel_txn = x86_pmu_cancel_txn,
1878 .commit_txn = x86_pmu_commit_txn,
1879
1880 .event_idx = x86_pmu_event_idx,
1881 .flush_branch_stack = x86_pmu_flush_branch_stack,
1882};
1883
1884void arch_perf_update_userpage(struct perf_event_mmap_page *userpg, u64 now)
1885{
1886 userpg->cap_usr_time = 0;
1887 userpg->cap_usr_rdpmc = x86_pmu.attr_rdpmc;
1888 userpg->pmc_width = x86_pmu.cntval_bits;
1889
1890 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
1891 return;
1892
1893 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
1894 return;
1895
1896 userpg->cap_usr_time = 1;
1897 userpg->time_mult = this_cpu_read(cyc2ns);
1898 userpg->time_shift = CYC2NS_SCALE_FACTOR;
1899 userpg->time_offset = this_cpu_read(cyc2ns_offset) - now;
1900}
1901
1902
1903
1904
1905
1906static int backtrace_stack(void *data, char *name)
1907{
1908 return 0;
1909}
1910
1911static void backtrace_address(void *data, unsigned long addr, int reliable)
1912{
1913 struct perf_callchain_entry *entry = data;
1914
1915 perf_callchain_store(entry, addr);
1916}
1917
1918static const struct stacktrace_ops backtrace_ops = {
1919 .stack = backtrace_stack,
1920 .address = backtrace_address,
1921 .walk_stack = print_context_stack_bp,
1922};
1923
1924void
1925perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1926{
1927 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1928
1929 return;
1930 }
1931
1932 perf_callchain_store(entry, regs->ip);
1933
1934 dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
1935}
1936
1937static inline int
1938valid_user_frame(const void __user *fp, unsigned long size)
1939{
1940 return (__range_not_ok(fp, size, TASK_SIZE) == 0);
1941}
1942
1943static unsigned long get_segment_base(unsigned int segment)
1944{
1945 struct desc_struct *desc;
1946 int idx = segment >> 3;
1947
1948 if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1949 if (idx > LDT_ENTRIES)
1950 return 0;
1951
1952 if (idx > current->active_mm->context.size)
1953 return 0;
1954
1955 desc = current->active_mm->context.ldt;
1956 } else {
1957 if (idx > GDT_ENTRIES)
1958 return 0;
1959
1960 desc = __this_cpu_ptr(&gdt_page.gdt[0]);
1961 }
1962
1963 return get_desc_base(desc + idx);
1964}
1965
1966#ifdef CONFIG_COMPAT
1967
1968#include <asm/compat.h>
1969
1970static inline int
1971perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1972{
1973
1974 unsigned long ss_base, cs_base;
1975 struct stack_frame_ia32 frame;
1976 const void __user *fp;
1977
1978 if (!test_thread_flag(TIF_IA32))
1979 return 0;
1980
1981 cs_base = get_segment_base(regs->cs);
1982 ss_base = get_segment_base(regs->ss);
1983
1984 fp = compat_ptr(ss_base + regs->bp);
1985 while (entry->nr < PERF_MAX_STACK_DEPTH) {
1986 unsigned long bytes;
1987 frame.next_frame = 0;
1988 frame.return_address = 0;
1989
1990 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1991 if (bytes != sizeof(frame))
1992 break;
1993
1994 if (!valid_user_frame(fp, sizeof(frame)))
1995 break;
1996
1997 perf_callchain_store(entry, cs_base + frame.return_address);
1998 fp = compat_ptr(ss_base + frame.next_frame);
1999 }
2000 return 1;
2001}
2002#else
2003static inline int
2004perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2005{
2006 return 0;
2007}
2008#endif
2009
2010void
2011perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
2012{
2013 struct stack_frame frame;
2014 const void __user *fp;
2015
2016 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2017
2018 return;
2019 }
2020
2021
2022
2023
2024 if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2025 return;
2026
2027 fp = (void __user *)regs->bp;
2028
2029 perf_callchain_store(entry, regs->ip);
2030
2031 if (!current->mm)
2032 return;
2033
2034 if (perf_callchain_user32(regs, entry))
2035 return;
2036
2037 while (entry->nr < PERF_MAX_STACK_DEPTH) {
2038 unsigned long bytes;
2039 frame.next_frame = NULL;
2040 frame.return_address = 0;
2041
2042 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2043 if (bytes != sizeof(frame))
2044 break;
2045
2046 if (!valid_user_frame(fp, sizeof(frame)))
2047 break;
2048
2049 perf_callchain_store(entry, frame.return_address);
2050 fp = frame.next_frame;
2051 }
2052}
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067static unsigned long code_segment_base(struct pt_regs *regs)
2068{
2069
2070
2071
2072
2073 if (regs->flags & X86_VM_MASK)
2074 return 0x10 * regs->cs;
2075
2076
2077
2078
2079
2080#ifdef CONFIG_X86_32
2081 if (user_mode(regs) && regs->cs != __USER_CS)
2082 return get_segment_base(regs->cs);
2083#else
2084 if (test_thread_flag(TIF_IA32)) {
2085 if (user_mode(regs) && regs->cs != __USER32_CS)
2086 return get_segment_base(regs->cs);
2087 }
2088#endif
2089 return 0;
2090}
2091
2092unsigned long perf_instruction_pointer(struct pt_regs *regs)
2093{
2094 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2095 return perf_guest_cbs->get_guest_ip();
2096
2097 return regs->ip + code_segment_base(regs);
2098}
2099
2100unsigned long perf_misc_flags(struct pt_regs *regs)
2101{
2102 int misc = 0;
2103
2104 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2105 if (perf_guest_cbs->is_user_mode())
2106 misc |= PERF_RECORD_MISC_GUEST_USER;
2107 else
2108 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2109 } else {
2110 if (user_mode(regs))
2111 misc |= PERF_RECORD_MISC_USER;
2112 else
2113 misc |= PERF_RECORD_MISC_KERNEL;
2114 }
2115
2116 if (regs->flags & PERF_EFLAGS_EXACT)
2117 misc |= PERF_RECORD_MISC_EXACT_IP;
2118
2119 return misc;
2120}
2121
2122void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2123{
2124 cap->version = x86_pmu.version;
2125 cap->num_counters_gp = x86_pmu.num_counters;
2126 cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2127 cap->bit_width_gp = x86_pmu.cntval_bits;
2128 cap->bit_width_fixed = x86_pmu.cntval_bits;
2129 cap->events_mask = (unsigned int)x86_pmu.events_maskl;
2130 cap->events_mask_len = x86_pmu.events_mask_len;
2131}
2132EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);
2133