1
2
3
4
5
6
7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/stddef.h>
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/slab.h>
14#include <linux/export.h>
15
16#include <asm/cpufeature.h>
17#include <asm/hardirq.h>
18#include <asm/apic.h>
19
20#include "perf_event.h"
21
22
23
24
25static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
26{
27 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
28 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
29 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
30 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
31 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
32 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
33 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
34 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300,
35};
36
37static struct event_constraint intel_core_event_constraints[] __read_mostly =
38{
39 INTEL_EVENT_CONSTRAINT(0x11, 0x2),
40 INTEL_EVENT_CONSTRAINT(0x12, 0x2),
41 INTEL_EVENT_CONSTRAINT(0x13, 0x2),
42 INTEL_EVENT_CONSTRAINT(0x14, 0x1),
43 INTEL_EVENT_CONSTRAINT(0x19, 0x2),
44 INTEL_EVENT_CONSTRAINT(0xc1, 0x1),
45 EVENT_CONSTRAINT_END
46};
47
48static struct event_constraint intel_core2_event_constraints[] __read_mostly =
49{
50 FIXED_EVENT_CONSTRAINT(0x00c0, 0),
51 FIXED_EVENT_CONSTRAINT(0x003c, 1),
52 FIXED_EVENT_CONSTRAINT(0x0300, 2),
53 INTEL_EVENT_CONSTRAINT(0x10, 0x1),
54 INTEL_EVENT_CONSTRAINT(0x11, 0x2),
55 INTEL_EVENT_CONSTRAINT(0x12, 0x2),
56 INTEL_EVENT_CONSTRAINT(0x13, 0x2),
57 INTEL_EVENT_CONSTRAINT(0x14, 0x1),
58 INTEL_EVENT_CONSTRAINT(0x18, 0x1),
59 INTEL_EVENT_CONSTRAINT(0x19, 0x2),
60 INTEL_EVENT_CONSTRAINT(0xa1, 0x1),
61 INTEL_EVENT_CONSTRAINT(0xc9, 0x1),
62 INTEL_EVENT_CONSTRAINT(0xcb, 0x1),
63 EVENT_CONSTRAINT_END
64};
65
66static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
67{
68 FIXED_EVENT_CONSTRAINT(0x00c0, 0),
69 FIXED_EVENT_CONSTRAINT(0x003c, 1),
70 FIXED_EVENT_CONSTRAINT(0x0300, 2),
71 INTEL_EVENT_CONSTRAINT(0x40, 0x3),
72 INTEL_EVENT_CONSTRAINT(0x41, 0x3),
73 INTEL_EVENT_CONSTRAINT(0x42, 0x3),
74 INTEL_EVENT_CONSTRAINT(0x43, 0x3),
75 INTEL_EVENT_CONSTRAINT(0x48, 0x3),
76 INTEL_EVENT_CONSTRAINT(0x4e, 0x3),
77 INTEL_EVENT_CONSTRAINT(0x51, 0x3),
78 INTEL_EVENT_CONSTRAINT(0x63, 0x3),
79 EVENT_CONSTRAINT_END
80};
81
82static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
83{
84 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
85 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
86 EVENT_EXTRA_END
87};
88
89static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
90{
91 FIXED_EVENT_CONSTRAINT(0x00c0, 0),
92 FIXED_EVENT_CONSTRAINT(0x003c, 1),
93 FIXED_EVENT_CONSTRAINT(0x0300, 2),
94 INTEL_EVENT_CONSTRAINT(0x51, 0x3),
95 INTEL_EVENT_CONSTRAINT(0x60, 0x1),
96 INTEL_EVENT_CONSTRAINT(0x63, 0x3),
97 INTEL_EVENT_CONSTRAINT(0xb3, 0x1),
98 EVENT_CONSTRAINT_END
99};
100
101static struct event_constraint intel_snb_event_constraints[] __read_mostly =
102{
103 FIXED_EVENT_CONSTRAINT(0x00c0, 0),
104 FIXED_EVENT_CONSTRAINT(0x003c, 1),
105 FIXED_EVENT_CONSTRAINT(0x0300, 2),
106 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
107 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf),
108 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4),
109 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4),
110 INTEL_EVENT_CONSTRAINT(0x48, 0x4),
111 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2),
112 INTEL_EVENT_CONSTRAINT(0xcd, 0x8),
113 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
114 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4),
115 EVENT_CONSTRAINT_END
116};
117
118static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
119{
120 FIXED_EVENT_CONSTRAINT(0x00c0, 0),
121 FIXED_EVENT_CONSTRAINT(0x003c, 1),
122 FIXED_EVENT_CONSTRAINT(0x0300, 2),
123 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4),
124 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf),
125 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf),
126 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
127 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf),
128 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf),
129 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
130 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
131 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2),
132
133
134
135
136
137 INTEL_EVENT_CONSTRAINT(0xd0, 0x0),
138 INTEL_EVENT_CONSTRAINT(0xd1, 0x0),
139 INTEL_EVENT_CONSTRAINT(0xd2, 0x0),
140 INTEL_EVENT_CONSTRAINT(0xd3, 0x0),
141 EVENT_CONSTRAINT_END
142};
143
144static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
145{
146 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
147 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
148 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
149 EVENT_EXTRA_END
150};
151
152static struct event_constraint intel_v1_event_constraints[] __read_mostly =
153{
154 EVENT_CONSTRAINT_END
155};
156
157static struct event_constraint intel_gen_event_constraints[] __read_mostly =
158{
159 FIXED_EVENT_CONSTRAINT(0x00c0, 0),
160 FIXED_EVENT_CONSTRAINT(0x003c, 1),
161 FIXED_EVENT_CONSTRAINT(0x0300, 2),
162 EVENT_CONSTRAINT_END
163};
164
165static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
166 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
167 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
168 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
169 EVENT_EXTRA_END
170};
171
172static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
173 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
174 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
175 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
176 EVENT_EXTRA_END
177};
178
179EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
180EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
181EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
182
183struct attribute *nhm_events_attrs[] = {
184 EVENT_PTR(mem_ld_nhm),
185 NULL,
186};
187
188struct attribute *snb_events_attrs[] = {
189 EVENT_PTR(mem_ld_snb),
190 EVENT_PTR(mem_st_snb),
191 NULL,
192};
193
194static struct event_constraint intel_hsw_event_constraints[] = {
195 FIXED_EVENT_CONSTRAINT(0x00c0, 0),
196 FIXED_EVENT_CONSTRAINT(0x003c, 1),
197 FIXED_EVENT_CONSTRAINT(0x0300, 2),
198 INTEL_EVENT_CONSTRAINT(0x48, 0x4),
199 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2),
200 INTEL_EVENT_CONSTRAINT(0xcd, 0x8),
201
202 INTEL_EVENT_CONSTRAINT(0x08a3, 0x4),
203
204 INTEL_EVENT_CONSTRAINT(0x0ca3, 0x4),
205
206 INTEL_EVENT_CONSTRAINT(0x04a3, 0xf),
207 EVENT_CONSTRAINT_END
208};
209
210static u64 intel_pmu_event_map(int hw_event)
211{
212 return intel_perfmon_event_map[hw_event];
213}
214
215#define SNB_DMND_DATA_RD (1ULL << 0)
216#define SNB_DMND_RFO (1ULL << 1)
217#define SNB_DMND_IFETCH (1ULL << 2)
218#define SNB_DMND_WB (1ULL << 3)
219#define SNB_PF_DATA_RD (1ULL << 4)
220#define SNB_PF_RFO (1ULL << 5)
221#define SNB_PF_IFETCH (1ULL << 6)
222#define SNB_LLC_DATA_RD (1ULL << 7)
223#define SNB_LLC_RFO (1ULL << 8)
224#define SNB_LLC_IFETCH (1ULL << 9)
225#define SNB_BUS_LOCKS (1ULL << 10)
226#define SNB_STRM_ST (1ULL << 11)
227#define SNB_OTHER (1ULL << 15)
228#define SNB_RESP_ANY (1ULL << 16)
229#define SNB_NO_SUPP (1ULL << 17)
230#define SNB_LLC_HITM (1ULL << 18)
231#define SNB_LLC_HITE (1ULL << 19)
232#define SNB_LLC_HITS (1ULL << 20)
233#define SNB_LLC_HITF (1ULL << 21)
234#define SNB_LOCAL (1ULL << 22)
235#define SNB_REMOTE (0xffULL << 23)
236#define SNB_SNP_NONE (1ULL << 31)
237#define SNB_SNP_NOT_NEEDED (1ULL << 32)
238#define SNB_SNP_MISS (1ULL << 33)
239#define SNB_NO_FWD (1ULL << 34)
240#define SNB_SNP_FWD (1ULL << 35)
241#define SNB_HITM (1ULL << 36)
242#define SNB_NON_DRAM (1ULL << 37)
243
244#define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
245#define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
246#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
247
248#define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
249 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
250 SNB_HITM)
251
252#define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
253#define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
254
255#define SNB_L3_ACCESS SNB_RESP_ANY
256#define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
257
258static __initconst const u64 snb_hw_cache_extra_regs
259 [PERF_COUNT_HW_CACHE_MAX]
260 [PERF_COUNT_HW_CACHE_OP_MAX]
261 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
262{
263 [ C(LL ) ] = {
264 [ C(OP_READ) ] = {
265 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
266 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
267 },
268 [ C(OP_WRITE) ] = {
269 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
270 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
271 },
272 [ C(OP_PREFETCH) ] = {
273 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
274 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
275 },
276 },
277 [ C(NODE) ] = {
278 [ C(OP_READ) ] = {
279 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
280 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
281 },
282 [ C(OP_WRITE) ] = {
283 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
284 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
285 },
286 [ C(OP_PREFETCH) ] = {
287 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
288 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
289 },
290 },
291};
292
293static __initconst const u64 snb_hw_cache_event_ids
294 [PERF_COUNT_HW_CACHE_MAX]
295 [PERF_COUNT_HW_CACHE_OP_MAX]
296 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
297{
298 [ C(L1D) ] = {
299 [ C(OP_READ) ] = {
300 [ C(RESULT_ACCESS) ] = 0xf1d0,
301 [ C(RESULT_MISS) ] = 0x0151,
302 },
303 [ C(OP_WRITE) ] = {
304 [ C(RESULT_ACCESS) ] = 0xf2d0,
305 [ C(RESULT_MISS) ] = 0x0851,
306 },
307 [ C(OP_PREFETCH) ] = {
308 [ C(RESULT_ACCESS) ] = 0x0,
309 [ C(RESULT_MISS) ] = 0x024e,
310 },
311 },
312 [ C(L1I ) ] = {
313 [ C(OP_READ) ] = {
314 [ C(RESULT_ACCESS) ] = 0x0,
315 [ C(RESULT_MISS) ] = 0x0280,
316 },
317 [ C(OP_WRITE) ] = {
318 [ C(RESULT_ACCESS) ] = -1,
319 [ C(RESULT_MISS) ] = -1,
320 },
321 [ C(OP_PREFETCH) ] = {
322 [ C(RESULT_ACCESS) ] = 0x0,
323 [ C(RESULT_MISS) ] = 0x0,
324 },
325 },
326 [ C(LL ) ] = {
327 [ C(OP_READ) ] = {
328
329 [ C(RESULT_ACCESS) ] = 0x01b7,
330
331 [ C(RESULT_MISS) ] = 0x01b7,
332 },
333 [ C(OP_WRITE) ] = {
334
335 [ C(RESULT_ACCESS) ] = 0x01b7,
336
337 [ C(RESULT_MISS) ] = 0x01b7,
338 },
339 [ C(OP_PREFETCH) ] = {
340
341 [ C(RESULT_ACCESS) ] = 0x01b7,
342
343 [ C(RESULT_MISS) ] = 0x01b7,
344 },
345 },
346 [ C(DTLB) ] = {
347 [ C(OP_READ) ] = {
348 [ C(RESULT_ACCESS) ] = 0x81d0,
349 [ C(RESULT_MISS) ] = 0x0108,
350 },
351 [ C(OP_WRITE) ] = {
352 [ C(RESULT_ACCESS) ] = 0x82d0,
353 [ C(RESULT_MISS) ] = 0x0149,
354 },
355 [ C(OP_PREFETCH) ] = {
356 [ C(RESULT_ACCESS) ] = 0x0,
357 [ C(RESULT_MISS) ] = 0x0,
358 },
359 },
360 [ C(ITLB) ] = {
361 [ C(OP_READ) ] = {
362 [ C(RESULT_ACCESS) ] = 0x1085,
363 [ C(RESULT_MISS) ] = 0x0185,
364 },
365 [ C(OP_WRITE) ] = {
366 [ C(RESULT_ACCESS) ] = -1,
367 [ C(RESULT_MISS) ] = -1,
368 },
369 [ C(OP_PREFETCH) ] = {
370 [ C(RESULT_ACCESS) ] = -1,
371 [ C(RESULT_MISS) ] = -1,
372 },
373 },
374 [ C(BPU ) ] = {
375 [ C(OP_READ) ] = {
376 [ C(RESULT_ACCESS) ] = 0x00c4,
377 [ C(RESULT_MISS) ] = 0x00c5,
378 },
379 [ C(OP_WRITE) ] = {
380 [ C(RESULT_ACCESS) ] = -1,
381 [ C(RESULT_MISS) ] = -1,
382 },
383 [ C(OP_PREFETCH) ] = {
384 [ C(RESULT_ACCESS) ] = -1,
385 [ C(RESULT_MISS) ] = -1,
386 },
387 },
388 [ C(NODE) ] = {
389 [ C(OP_READ) ] = {
390 [ C(RESULT_ACCESS) ] = 0x01b7,
391 [ C(RESULT_MISS) ] = 0x01b7,
392 },
393 [ C(OP_WRITE) ] = {
394 [ C(RESULT_ACCESS) ] = 0x01b7,
395 [ C(RESULT_MISS) ] = 0x01b7,
396 },
397 [ C(OP_PREFETCH) ] = {
398 [ C(RESULT_ACCESS) ] = 0x01b7,
399 [ C(RESULT_MISS) ] = 0x01b7,
400 },
401 },
402
403};
404
405static __initconst const u64 westmere_hw_cache_event_ids
406 [PERF_COUNT_HW_CACHE_MAX]
407 [PERF_COUNT_HW_CACHE_OP_MAX]
408 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
409{
410 [ C(L1D) ] = {
411 [ C(OP_READ) ] = {
412 [ C(RESULT_ACCESS) ] = 0x010b,
413 [ C(RESULT_MISS) ] = 0x0151,
414 },
415 [ C(OP_WRITE) ] = {
416 [ C(RESULT_ACCESS) ] = 0x020b,
417 [ C(RESULT_MISS) ] = 0x0251,
418 },
419 [ C(OP_PREFETCH) ] = {
420 [ C(RESULT_ACCESS) ] = 0x014e,
421 [ C(RESULT_MISS) ] = 0x024e,
422 },
423 },
424 [ C(L1I ) ] = {
425 [ C(OP_READ) ] = {
426 [ C(RESULT_ACCESS) ] = 0x0380,
427 [ C(RESULT_MISS) ] = 0x0280,
428 },
429 [ C(OP_WRITE) ] = {
430 [ C(RESULT_ACCESS) ] = -1,
431 [ C(RESULT_MISS) ] = -1,
432 },
433 [ C(OP_PREFETCH) ] = {
434 [ C(RESULT_ACCESS) ] = 0x0,
435 [ C(RESULT_MISS) ] = 0x0,
436 },
437 },
438 [ C(LL ) ] = {
439 [ C(OP_READ) ] = {
440
441 [ C(RESULT_ACCESS) ] = 0x01b7,
442
443 [ C(RESULT_MISS) ] = 0x01b7,
444 },
445
446
447
448
449 [ C(OP_WRITE) ] = {
450
451 [ C(RESULT_ACCESS) ] = 0x01b7,
452
453 [ C(RESULT_MISS) ] = 0x01b7,
454 },
455 [ C(OP_PREFETCH) ] = {
456
457 [ C(RESULT_ACCESS) ] = 0x01b7,
458
459 [ C(RESULT_MISS) ] = 0x01b7,
460 },
461 },
462 [ C(DTLB) ] = {
463 [ C(OP_READ) ] = {
464 [ C(RESULT_ACCESS) ] = 0x010b,
465 [ C(RESULT_MISS) ] = 0x0108,
466 },
467 [ C(OP_WRITE) ] = {
468 [ C(RESULT_ACCESS) ] = 0x020b,
469 [ C(RESULT_MISS) ] = 0x010c,
470 },
471 [ C(OP_PREFETCH) ] = {
472 [ C(RESULT_ACCESS) ] = 0x0,
473 [ C(RESULT_MISS) ] = 0x0,
474 },
475 },
476 [ C(ITLB) ] = {
477 [ C(OP_READ) ] = {
478 [ C(RESULT_ACCESS) ] = 0x01c0,
479 [ C(RESULT_MISS) ] = 0x0185,
480 },
481 [ C(OP_WRITE) ] = {
482 [ C(RESULT_ACCESS) ] = -1,
483 [ C(RESULT_MISS) ] = -1,
484 },
485 [ C(OP_PREFETCH) ] = {
486 [ C(RESULT_ACCESS) ] = -1,
487 [ C(RESULT_MISS) ] = -1,
488 },
489 },
490 [ C(BPU ) ] = {
491 [ C(OP_READ) ] = {
492 [ C(RESULT_ACCESS) ] = 0x00c4,
493 [ C(RESULT_MISS) ] = 0x03e8,
494 },
495 [ C(OP_WRITE) ] = {
496 [ C(RESULT_ACCESS) ] = -1,
497 [ C(RESULT_MISS) ] = -1,
498 },
499 [ C(OP_PREFETCH) ] = {
500 [ C(RESULT_ACCESS) ] = -1,
501 [ C(RESULT_MISS) ] = -1,
502 },
503 },
504 [ C(NODE) ] = {
505 [ C(OP_READ) ] = {
506 [ C(RESULT_ACCESS) ] = 0x01b7,
507 [ C(RESULT_MISS) ] = 0x01b7,
508 },
509 [ C(OP_WRITE) ] = {
510 [ C(RESULT_ACCESS) ] = 0x01b7,
511 [ C(RESULT_MISS) ] = 0x01b7,
512 },
513 [ C(OP_PREFETCH) ] = {
514 [ C(RESULT_ACCESS) ] = 0x01b7,
515 [ C(RESULT_MISS) ] = 0x01b7,
516 },
517 },
518};
519
520
521
522
523
524
525#define NHM_DMND_DATA_RD (1 << 0)
526#define NHM_DMND_RFO (1 << 1)
527#define NHM_DMND_IFETCH (1 << 2)
528#define NHM_DMND_WB (1 << 3)
529#define NHM_PF_DATA_RD (1 << 4)
530#define NHM_PF_DATA_RFO (1 << 5)
531#define NHM_PF_IFETCH (1 << 6)
532#define NHM_OFFCORE_OTHER (1 << 7)
533#define NHM_UNCORE_HIT (1 << 8)
534#define NHM_OTHER_CORE_HIT_SNP (1 << 9)
535#define NHM_OTHER_CORE_HITM (1 << 10)
536
537#define NHM_REMOTE_CACHE_FWD (1 << 12)
538#define NHM_REMOTE_DRAM (1 << 13)
539#define NHM_LOCAL_DRAM (1 << 14)
540#define NHM_NON_DRAM (1 << 15)
541
542#define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
543#define NHM_REMOTE (NHM_REMOTE_DRAM)
544
545#define NHM_DMND_READ (NHM_DMND_DATA_RD)
546#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
547#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
548
549#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
550#define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
551#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
552
553static __initconst const u64 nehalem_hw_cache_extra_regs
554 [PERF_COUNT_HW_CACHE_MAX]
555 [PERF_COUNT_HW_CACHE_OP_MAX]
556 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
557{
558 [ C(LL ) ] = {
559 [ C(OP_READ) ] = {
560 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
561 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
562 },
563 [ C(OP_WRITE) ] = {
564 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
565 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
566 },
567 [ C(OP_PREFETCH) ] = {
568 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
569 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
570 },
571 },
572 [ C(NODE) ] = {
573 [ C(OP_READ) ] = {
574 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
575 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
576 },
577 [ C(OP_WRITE) ] = {
578 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
579 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
580 },
581 [ C(OP_PREFETCH) ] = {
582 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
583 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
584 },
585 },
586};
587
588static __initconst const u64 nehalem_hw_cache_event_ids
589 [PERF_COUNT_HW_CACHE_MAX]
590 [PERF_COUNT_HW_CACHE_OP_MAX]
591 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
592{
593 [ C(L1D) ] = {
594 [ C(OP_READ) ] = {
595 [ C(RESULT_ACCESS) ] = 0x010b,
596 [ C(RESULT_MISS) ] = 0x0151,
597 },
598 [ C(OP_WRITE) ] = {
599 [ C(RESULT_ACCESS) ] = 0x020b,
600 [ C(RESULT_MISS) ] = 0x0251,
601 },
602 [ C(OP_PREFETCH) ] = {
603 [ C(RESULT_ACCESS) ] = 0x014e,
604 [ C(RESULT_MISS) ] = 0x024e,
605 },
606 },
607 [ C(L1I ) ] = {
608 [ C(OP_READ) ] = {
609 [ C(RESULT_ACCESS) ] = 0x0380,
610 [ C(RESULT_MISS) ] = 0x0280,
611 },
612 [ C(OP_WRITE) ] = {
613 [ C(RESULT_ACCESS) ] = -1,
614 [ C(RESULT_MISS) ] = -1,
615 },
616 [ C(OP_PREFETCH) ] = {
617 [ C(RESULT_ACCESS) ] = 0x0,
618 [ C(RESULT_MISS) ] = 0x0,
619 },
620 },
621 [ C(LL ) ] = {
622 [ C(OP_READ) ] = {
623
624 [ C(RESULT_ACCESS) ] = 0x01b7,
625
626 [ C(RESULT_MISS) ] = 0x01b7,
627 },
628
629
630
631
632 [ C(OP_WRITE) ] = {
633
634 [ C(RESULT_ACCESS) ] = 0x01b7,
635
636 [ C(RESULT_MISS) ] = 0x01b7,
637 },
638 [ C(OP_PREFETCH) ] = {
639
640 [ C(RESULT_ACCESS) ] = 0x01b7,
641
642 [ C(RESULT_MISS) ] = 0x01b7,
643 },
644 },
645 [ C(DTLB) ] = {
646 [ C(OP_READ) ] = {
647 [ C(RESULT_ACCESS) ] = 0x0f40,
648 [ C(RESULT_MISS) ] = 0x0108,
649 },
650 [ C(OP_WRITE) ] = {
651 [ C(RESULT_ACCESS) ] = 0x0f41,
652 [ C(RESULT_MISS) ] = 0x010c,
653 },
654 [ C(OP_PREFETCH) ] = {
655 [ C(RESULT_ACCESS) ] = 0x0,
656 [ C(RESULT_MISS) ] = 0x0,
657 },
658 },
659 [ C(ITLB) ] = {
660 [ C(OP_READ) ] = {
661 [ C(RESULT_ACCESS) ] = 0x01c0,
662 [ C(RESULT_MISS) ] = 0x20c8,
663 },
664 [ C(OP_WRITE) ] = {
665 [ C(RESULT_ACCESS) ] = -1,
666 [ C(RESULT_MISS) ] = -1,
667 },
668 [ C(OP_PREFETCH) ] = {
669 [ C(RESULT_ACCESS) ] = -1,
670 [ C(RESULT_MISS) ] = -1,
671 },
672 },
673 [ C(BPU ) ] = {
674 [ C(OP_READ) ] = {
675 [ C(RESULT_ACCESS) ] = 0x00c4,
676 [ C(RESULT_MISS) ] = 0x03e8,
677 },
678 [ C(OP_WRITE) ] = {
679 [ C(RESULT_ACCESS) ] = -1,
680 [ C(RESULT_MISS) ] = -1,
681 },
682 [ C(OP_PREFETCH) ] = {
683 [ C(RESULT_ACCESS) ] = -1,
684 [ C(RESULT_MISS) ] = -1,
685 },
686 },
687 [ C(NODE) ] = {
688 [ C(OP_READ) ] = {
689 [ C(RESULT_ACCESS) ] = 0x01b7,
690 [ C(RESULT_MISS) ] = 0x01b7,
691 },
692 [ C(OP_WRITE) ] = {
693 [ C(RESULT_ACCESS) ] = 0x01b7,
694 [ C(RESULT_MISS) ] = 0x01b7,
695 },
696 [ C(OP_PREFETCH) ] = {
697 [ C(RESULT_ACCESS) ] = 0x01b7,
698 [ C(RESULT_MISS) ] = 0x01b7,
699 },
700 },
701};
702
703static __initconst const u64 core2_hw_cache_event_ids
704 [PERF_COUNT_HW_CACHE_MAX]
705 [PERF_COUNT_HW_CACHE_OP_MAX]
706 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
707{
708 [ C(L1D) ] = {
709 [ C(OP_READ) ] = {
710 [ C(RESULT_ACCESS) ] = 0x0f40,
711 [ C(RESULT_MISS) ] = 0x0140,
712 },
713 [ C(OP_WRITE) ] = {
714 [ C(RESULT_ACCESS) ] = 0x0f41,
715 [ C(RESULT_MISS) ] = 0x0141,
716 },
717 [ C(OP_PREFETCH) ] = {
718 [ C(RESULT_ACCESS) ] = 0x104e,
719 [ C(RESULT_MISS) ] = 0,
720 },
721 },
722 [ C(L1I ) ] = {
723 [ C(OP_READ) ] = {
724 [ C(RESULT_ACCESS) ] = 0x0080,
725 [ C(RESULT_MISS) ] = 0x0081,
726 },
727 [ C(OP_WRITE) ] = {
728 [ C(RESULT_ACCESS) ] = -1,
729 [ C(RESULT_MISS) ] = -1,
730 },
731 [ C(OP_PREFETCH) ] = {
732 [ C(RESULT_ACCESS) ] = 0,
733 [ C(RESULT_MISS) ] = 0,
734 },
735 },
736 [ C(LL ) ] = {
737 [ C(OP_READ) ] = {
738 [ C(RESULT_ACCESS) ] = 0x4f29,
739 [ C(RESULT_MISS) ] = 0x4129,
740 },
741 [ C(OP_WRITE) ] = {
742 [ C(RESULT_ACCESS) ] = 0x4f2A,
743 [ C(RESULT_MISS) ] = 0x412A,
744 },
745 [ C(OP_PREFETCH) ] = {
746 [ C(RESULT_ACCESS) ] = 0,
747 [ C(RESULT_MISS) ] = 0,
748 },
749 },
750 [ C(DTLB) ] = {
751 [ C(OP_READ) ] = {
752 [ C(RESULT_ACCESS) ] = 0x0f40,
753 [ C(RESULT_MISS) ] = 0x0208,
754 },
755 [ C(OP_WRITE) ] = {
756 [ C(RESULT_ACCESS) ] = 0x0f41,
757 [ C(RESULT_MISS) ] = 0x0808,
758 },
759 [ C(OP_PREFETCH) ] = {
760 [ C(RESULT_ACCESS) ] = 0,
761 [ C(RESULT_MISS) ] = 0,
762 },
763 },
764 [ C(ITLB) ] = {
765 [ C(OP_READ) ] = {
766 [ C(RESULT_ACCESS) ] = 0x00c0,
767 [ C(RESULT_MISS) ] = 0x1282,
768 },
769 [ C(OP_WRITE) ] = {
770 [ C(RESULT_ACCESS) ] = -1,
771 [ C(RESULT_MISS) ] = -1,
772 },
773 [ C(OP_PREFETCH) ] = {
774 [ C(RESULT_ACCESS) ] = -1,
775 [ C(RESULT_MISS) ] = -1,
776 },
777 },
778 [ C(BPU ) ] = {
779 [ C(OP_READ) ] = {
780 [ C(RESULT_ACCESS) ] = 0x00c4,
781 [ C(RESULT_MISS) ] = 0x00c5,
782 },
783 [ C(OP_WRITE) ] = {
784 [ C(RESULT_ACCESS) ] = -1,
785 [ C(RESULT_MISS) ] = -1,
786 },
787 [ C(OP_PREFETCH) ] = {
788 [ C(RESULT_ACCESS) ] = -1,
789 [ C(RESULT_MISS) ] = -1,
790 },
791 },
792};
793
794static __initconst const u64 atom_hw_cache_event_ids
795 [PERF_COUNT_HW_CACHE_MAX]
796 [PERF_COUNT_HW_CACHE_OP_MAX]
797 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
798{
799 [ C(L1D) ] = {
800 [ C(OP_READ) ] = {
801 [ C(RESULT_ACCESS) ] = 0x2140,
802 [ C(RESULT_MISS) ] = 0,
803 },
804 [ C(OP_WRITE) ] = {
805 [ C(RESULT_ACCESS) ] = 0x2240,
806 [ C(RESULT_MISS) ] = 0,
807 },
808 [ C(OP_PREFETCH) ] = {
809 [ C(RESULT_ACCESS) ] = 0x0,
810 [ C(RESULT_MISS) ] = 0,
811 },
812 },
813 [ C(L1I ) ] = {
814 [ C(OP_READ) ] = {
815 [ C(RESULT_ACCESS) ] = 0x0380,
816 [ C(RESULT_MISS) ] = 0x0280,
817 },
818 [ C(OP_WRITE) ] = {
819 [ C(RESULT_ACCESS) ] = -1,
820 [ C(RESULT_MISS) ] = -1,
821 },
822 [ C(OP_PREFETCH) ] = {
823 [ C(RESULT_ACCESS) ] = 0,
824 [ C(RESULT_MISS) ] = 0,
825 },
826 },
827 [ C(LL ) ] = {
828 [ C(OP_READ) ] = {
829 [ C(RESULT_ACCESS) ] = 0x4f29,
830 [ C(RESULT_MISS) ] = 0x4129,
831 },
832 [ C(OP_WRITE) ] = {
833 [ C(RESULT_ACCESS) ] = 0x4f2A,
834 [ C(RESULT_MISS) ] = 0x412A,
835 },
836 [ C(OP_PREFETCH) ] = {
837 [ C(RESULT_ACCESS) ] = 0,
838 [ C(RESULT_MISS) ] = 0,
839 },
840 },
841 [ C(DTLB) ] = {
842 [ C(OP_READ) ] = {
843 [ C(RESULT_ACCESS) ] = 0x2140,
844 [ C(RESULT_MISS) ] = 0x0508,
845 },
846 [ C(OP_WRITE) ] = {
847 [ C(RESULT_ACCESS) ] = 0x2240,
848 [ C(RESULT_MISS) ] = 0x0608,
849 },
850 [ C(OP_PREFETCH) ] = {
851 [ C(RESULT_ACCESS) ] = 0,
852 [ C(RESULT_MISS) ] = 0,
853 },
854 },
855 [ C(ITLB) ] = {
856 [ C(OP_READ) ] = {
857 [ C(RESULT_ACCESS) ] = 0x00c0,
858 [ C(RESULT_MISS) ] = 0x0282,
859 },
860 [ C(OP_WRITE) ] = {
861 [ C(RESULT_ACCESS) ] = -1,
862 [ C(RESULT_MISS) ] = -1,
863 },
864 [ C(OP_PREFETCH) ] = {
865 [ C(RESULT_ACCESS) ] = -1,
866 [ C(RESULT_MISS) ] = -1,
867 },
868 },
869 [ C(BPU ) ] = {
870 [ C(OP_READ) ] = {
871 [ C(RESULT_ACCESS) ] = 0x00c4,
872 [ C(RESULT_MISS) ] = 0x00c5,
873 },
874 [ C(OP_WRITE) ] = {
875 [ C(RESULT_ACCESS) ] = -1,
876 [ C(RESULT_MISS) ] = -1,
877 },
878 [ C(OP_PREFETCH) ] = {
879 [ C(RESULT_ACCESS) ] = -1,
880 [ C(RESULT_MISS) ] = -1,
881 },
882 },
883};
884
885static inline bool intel_pmu_needs_lbr_smpl(struct perf_event *event)
886{
887
888 if (has_branch_stack(event))
889 return true;
890
891
892 if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1 &&
893 x86_pmu.intel_cap.pebs_format < 2)
894 return true;
895
896 return false;
897}
898
899static void intel_pmu_disable_all(void)
900{
901 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
902
903 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
904
905 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
906 intel_pmu_disable_bts();
907
908 intel_pmu_pebs_disable_all();
909 intel_pmu_lbr_disable_all();
910}
911
912static void intel_pmu_enable_all(int added)
913{
914 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
915
916 intel_pmu_pebs_enable_all();
917 intel_pmu_lbr_enable_all();
918 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
919 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
920
921 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
922 struct perf_event *event =
923 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
924
925 if (WARN_ON_ONCE(!event))
926 return;
927
928 intel_pmu_enable_bts(event->hw.config);
929 }
930}
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946static void intel_pmu_nhm_workaround(void)
947{
948 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
949 static const unsigned long nhm_magic[4] = {
950 0x4300B5,
951 0x4300D2,
952 0x4300B1,
953 0x4300B1
954 };
955 struct perf_event *event;
956 int i;
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980 for (i = 0; i < 4; i++) {
981 event = cpuc->events[i];
982 if (event)
983 x86_perf_event_update(event);
984 }
985
986 for (i = 0; i < 4; i++) {
987 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
988 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
989 }
990
991 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
992 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
993
994 for (i = 0; i < 4; i++) {
995 event = cpuc->events[i];
996
997 if (event) {
998 x86_perf_event_set_period(event);
999 __x86_pmu_enable_event(&event->hw,
1000 ARCH_PERFMON_EVENTSEL_ENABLE);
1001 } else
1002 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
1003 }
1004}
1005
1006static void intel_pmu_nhm_enable_all(int added)
1007{
1008 if (added)
1009 intel_pmu_nhm_workaround();
1010 intel_pmu_enable_all(added);
1011}
1012
1013static inline u64 intel_pmu_get_status(void)
1014{
1015 u64 status;
1016
1017 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1018
1019 return status;
1020}
1021
1022static inline void intel_pmu_ack_status(u64 ack)
1023{
1024 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1025}
1026
1027static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
1028{
1029 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1030 u64 ctrl_val, mask;
1031
1032 mask = 0xfULL << (idx * 4);
1033
1034 rdmsrl(hwc->config_base, ctrl_val);
1035 ctrl_val &= ~mask;
1036 wrmsrl(hwc->config_base, ctrl_val);
1037}
1038
1039static void intel_pmu_disable_event(struct perf_event *event)
1040{
1041 struct hw_perf_event *hwc = &event->hw;
1042 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1043
1044 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
1045 intel_pmu_disable_bts();
1046 intel_pmu_drain_bts_buffer();
1047 return;
1048 }
1049
1050 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
1051 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
1052
1053
1054
1055
1056
1057 if (intel_pmu_needs_lbr_smpl(event))
1058 intel_pmu_lbr_disable(event);
1059
1060 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1061 intel_pmu_disable_fixed(hwc);
1062 return;
1063 }
1064
1065 x86_pmu_disable_event(event);
1066
1067 if (unlikely(event->attr.precise_ip))
1068 intel_pmu_pebs_disable(event);
1069}
1070
1071static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
1072{
1073 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1074 u64 ctrl_val, bits, mask;
1075
1076
1077
1078
1079
1080
1081 bits = 0x8ULL;
1082 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1083 bits |= 0x2;
1084 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1085 bits |= 0x1;
1086
1087
1088
1089
1090 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1091 bits |= 0x4;
1092
1093 bits <<= (idx * 4);
1094 mask = 0xfULL << (idx * 4);
1095
1096 rdmsrl(hwc->config_base, ctrl_val);
1097 ctrl_val &= ~mask;
1098 ctrl_val |= bits;
1099 wrmsrl(hwc->config_base, ctrl_val);
1100}
1101
1102static void intel_pmu_enable_event(struct perf_event *event)
1103{
1104 struct hw_perf_event *hwc = &event->hw;
1105 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1106
1107 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
1108 if (!__this_cpu_read(cpu_hw_events.enabled))
1109 return;
1110
1111 intel_pmu_enable_bts(hwc->config);
1112 return;
1113 }
1114
1115
1116
1117
1118 if (intel_pmu_needs_lbr_smpl(event))
1119 intel_pmu_lbr_enable(event);
1120
1121 if (event->attr.exclude_host)
1122 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1123 if (event->attr.exclude_guest)
1124 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1125
1126 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1127 intel_pmu_enable_fixed(hwc);
1128 return;
1129 }
1130
1131 if (unlikely(event->attr.precise_ip))
1132 intel_pmu_pebs_enable(event);
1133
1134 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1135}
1136
1137
1138
1139
1140
1141int intel_pmu_save_and_restart(struct perf_event *event)
1142{
1143 x86_perf_event_update(event);
1144 return x86_perf_event_set_period(event);
1145}
1146
1147static void intel_pmu_reset(void)
1148{
1149 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1150 unsigned long flags;
1151 int idx;
1152
1153 if (!x86_pmu.num_counters)
1154 return;
1155
1156 local_irq_save(flags);
1157
1158 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
1159
1160 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1161 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
1162 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
1163 }
1164 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
1165 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
1166
1167 if (ds)
1168 ds->bts_index = ds->bts_buffer_base;
1169
1170 local_irq_restore(flags);
1171}
1172
1173
1174
1175
1176
1177static int intel_pmu_handle_irq(struct pt_regs *regs)
1178{
1179 struct perf_sample_data data;
1180 struct cpu_hw_events *cpuc;
1181 int bit, loops;
1182 u64 status;
1183 int handled;
1184
1185 cpuc = &__get_cpu_var(cpu_hw_events);
1186
1187
1188
1189
1190
1191 if (!x86_pmu.late_ack)
1192 apic_write(APIC_LVTPC, APIC_DM_NMI);
1193 intel_pmu_disable_all();
1194 handled = intel_pmu_drain_bts_buffer();
1195 status = intel_pmu_get_status();
1196 if (!status) {
1197 intel_pmu_enable_all(0);
1198 return handled;
1199 }
1200
1201 loops = 0;
1202again:
1203 intel_pmu_ack_status(status);
1204 if (++loops > 100) {
1205 static bool warned = false;
1206 if (!warned) {
1207 WARN(1, "perfevents: irq loop stuck!\n");
1208 perf_event_print_debug();
1209 warned = true;
1210 }
1211 intel_pmu_reset();
1212 goto done;
1213 }
1214
1215 inc_irq_stat(apic_perf_irqs);
1216
1217 intel_pmu_lbr_read();
1218
1219
1220
1221
1222 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1223 handled++;
1224 x86_pmu.drain_pebs(regs);
1225 }
1226
1227 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
1228 struct perf_event *event = cpuc->events[bit];
1229
1230 handled++;
1231
1232 if (!test_bit(bit, cpuc->active_mask))
1233 continue;
1234
1235 if (!intel_pmu_save_and_restart(event))
1236 continue;
1237
1238 perf_sample_data_init(&data, 0, event->hw.last_period);
1239
1240 if (has_branch_stack(event))
1241 data.br_stack = &cpuc->lbr_stack;
1242
1243 if (perf_event_overflow(event, &data, regs))
1244 x86_pmu_stop(event, 0);
1245 }
1246
1247
1248
1249
1250 status = intel_pmu_get_status();
1251 if (status)
1252 goto again;
1253
1254done:
1255 intel_pmu_enable_all(0);
1256
1257
1258
1259
1260
1261 if (x86_pmu.late_ack)
1262 apic_write(APIC_LVTPC, APIC_DM_NMI);
1263 return handled;
1264}
1265
1266static struct event_constraint *
1267intel_bts_constraints(struct perf_event *event)
1268{
1269 struct hw_perf_event *hwc = &event->hw;
1270 unsigned int hw_event, bts_event;
1271
1272 if (event->attr.freq)
1273 return NULL;
1274
1275 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1276 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
1277
1278 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
1279 return &bts_constraint;
1280
1281 return NULL;
1282}
1283
1284static int intel_alt_er(int idx)
1285{
1286 if (!(x86_pmu.er_flags & ERF_HAS_RSP_1))
1287 return idx;
1288
1289 if (idx == EXTRA_REG_RSP_0)
1290 return EXTRA_REG_RSP_1;
1291
1292 if (idx == EXTRA_REG_RSP_1)
1293 return EXTRA_REG_RSP_0;
1294
1295 return idx;
1296}
1297
1298static void intel_fixup_er(struct perf_event *event, int idx)
1299{
1300 event->hw.extra_reg.idx = idx;
1301
1302 if (idx == EXTRA_REG_RSP_0) {
1303 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1304 event->hw.config |= 0x01b7;
1305 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
1306 } else if (idx == EXTRA_REG_RSP_1) {
1307 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1308 event->hw.config |= 0x01bb;
1309 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
1310 }
1311}
1312
1313
1314
1315
1316
1317
1318
1319
1320static struct event_constraint *
1321__intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
1322 struct perf_event *event,
1323 struct hw_perf_event_extra *reg)
1324{
1325 struct event_constraint *c = &emptyconstraint;
1326 struct er_account *era;
1327 unsigned long flags;
1328 int idx = reg->idx;
1329
1330
1331
1332
1333
1334
1335 if (reg->alloc && !cpuc->is_fake)
1336 return NULL;
1337
1338again:
1339 era = &cpuc->shared_regs->regs[idx];
1340
1341
1342
1343
1344 raw_spin_lock_irqsave(&era->lock, flags);
1345
1346 if (!atomic_read(&era->ref) || era->config == reg->config) {
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358 if (!cpuc->is_fake) {
1359 if (idx != reg->idx)
1360 intel_fixup_er(event, idx);
1361
1362
1363
1364
1365
1366
1367
1368 reg->alloc = 1;
1369 }
1370
1371
1372 era->config = reg->config;
1373 era->reg = reg->reg;
1374
1375
1376 atomic_inc(&era->ref);
1377
1378
1379
1380
1381
1382 c = NULL;
1383 } else {
1384 idx = intel_alt_er(idx);
1385 if (idx != reg->idx) {
1386 raw_spin_unlock_irqrestore(&era->lock, flags);
1387 goto again;
1388 }
1389 }
1390 raw_spin_unlock_irqrestore(&era->lock, flags);
1391
1392 return c;
1393}
1394
1395static void
1396__intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
1397 struct hw_perf_event_extra *reg)
1398{
1399 struct er_account *era;
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409 if (!reg->alloc || cpuc->is_fake)
1410 return;
1411
1412 era = &cpuc->shared_regs->regs[reg->idx];
1413
1414
1415 atomic_dec(&era->ref);
1416
1417
1418 reg->alloc = 0;
1419}
1420
1421static struct event_constraint *
1422intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
1423 struct perf_event *event)
1424{
1425 struct event_constraint *c = NULL, *d;
1426 struct hw_perf_event_extra *xreg, *breg;
1427
1428 xreg = &event->hw.extra_reg;
1429 if (xreg->idx != EXTRA_REG_NONE) {
1430 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
1431 if (c == &emptyconstraint)
1432 return c;
1433 }
1434 breg = &event->hw.branch_reg;
1435 if (breg->idx != EXTRA_REG_NONE) {
1436 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
1437 if (d == &emptyconstraint) {
1438 __intel_shared_reg_put_constraints(cpuc, xreg);
1439 c = d;
1440 }
1441 }
1442 return c;
1443}
1444
1445struct event_constraint *
1446x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1447{
1448 struct event_constraint *c;
1449
1450 if (x86_pmu.event_constraints) {
1451 for_each_event_constraint(c, x86_pmu.event_constraints) {
1452 if ((event->hw.config & c->cmask) == c->code) {
1453 event->hw.flags |= c->flags;
1454 return c;
1455 }
1456 }
1457 }
1458
1459 return &unconstrained;
1460}
1461
1462static struct event_constraint *
1463intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1464{
1465 struct event_constraint *c;
1466
1467 c = intel_bts_constraints(event);
1468 if (c)
1469 return c;
1470
1471 c = intel_pebs_constraints(event);
1472 if (c)
1473 return c;
1474
1475 c = intel_shared_regs_constraints(cpuc, event);
1476 if (c)
1477 return c;
1478
1479 return x86_get_event_constraints(cpuc, event);
1480}
1481
1482static void
1483intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
1484 struct perf_event *event)
1485{
1486 struct hw_perf_event_extra *reg;
1487
1488 reg = &event->hw.extra_reg;
1489 if (reg->idx != EXTRA_REG_NONE)
1490 __intel_shared_reg_put_constraints(cpuc, reg);
1491
1492 reg = &event->hw.branch_reg;
1493 if (reg->idx != EXTRA_REG_NONE)
1494 __intel_shared_reg_put_constraints(cpuc, reg);
1495}
1496
1497static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
1498 struct perf_event *event)
1499{
1500 intel_put_shared_regs_event_constraints(cpuc, event);
1501}
1502
1503static void intel_pebs_aliases_core2(struct perf_event *event)
1504{
1505 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
1525
1526 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1527 event->hw.config = alt_config;
1528 }
1529}
1530
1531static void intel_pebs_aliases_snb(struct perf_event *event)
1532{
1533 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
1553
1554 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1555 event->hw.config = alt_config;
1556 }
1557}
1558
1559static int intel_pmu_hw_config(struct perf_event *event)
1560{
1561 int ret = x86_pmu_hw_config(event);
1562
1563 if (ret)
1564 return ret;
1565
1566 if (event->attr.precise_ip && x86_pmu.pebs_aliases)
1567 x86_pmu.pebs_aliases(event);
1568
1569 if (intel_pmu_needs_lbr_smpl(event)) {
1570 ret = intel_pmu_setup_lbr_filter(event);
1571 if (ret)
1572 return ret;
1573 }
1574
1575 if (event->attr.type != PERF_TYPE_RAW)
1576 return 0;
1577
1578 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
1579 return 0;
1580
1581 if (x86_pmu.version < 3)
1582 return -EINVAL;
1583
1584 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
1585 return -EACCES;
1586
1587 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
1588
1589 return 0;
1590}
1591
1592struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
1593{
1594 if (x86_pmu.guest_get_msrs)
1595 return x86_pmu.guest_get_msrs(nr);
1596 *nr = 0;
1597 return NULL;
1598}
1599EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
1600
1601static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
1602{
1603 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1604 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1605
1606 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
1607 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
1608 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
1609
1610
1611
1612
1613
1614 arr[1].msr = MSR_IA32_PEBS_ENABLE;
1615 arr[1].host = cpuc->pebs_enabled;
1616 arr[1].guest = 0;
1617
1618 *nr = 2;
1619 return arr;
1620}
1621
1622static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
1623{
1624 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1625 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1626 int idx;
1627
1628 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1629 struct perf_event *event = cpuc->events[idx];
1630
1631 arr[idx].msr = x86_pmu_config_addr(idx);
1632 arr[idx].host = arr[idx].guest = 0;
1633
1634 if (!test_bit(idx, cpuc->active_mask))
1635 continue;
1636
1637 arr[idx].host = arr[idx].guest =
1638 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
1639
1640 if (event->attr.exclude_host)
1641 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1642 else if (event->attr.exclude_guest)
1643 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1644 }
1645
1646 *nr = x86_pmu.num_counters;
1647 return arr;
1648}
1649
1650static void core_pmu_enable_event(struct perf_event *event)
1651{
1652 if (!event->attr.exclude_host)
1653 x86_pmu_enable_event(event);
1654}
1655
1656static void core_pmu_enable_all(int added)
1657{
1658 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1659 int idx;
1660
1661 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1662 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
1663
1664 if (!test_bit(idx, cpuc->active_mask) ||
1665 cpuc->events[idx]->attr.exclude_host)
1666 continue;
1667
1668 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1669 }
1670}
1671
1672static int hsw_hw_config(struct perf_event *event)
1673{
1674 int ret = intel_pmu_hw_config(event);
1675
1676 if (ret)
1677 return ret;
1678 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
1679 return 0;
1680 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
1681
1682
1683
1684
1685
1686
1687 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
1688 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
1689 event->attr.precise_ip > 0))
1690 return -EOPNOTSUPP;
1691
1692 return 0;
1693}
1694
1695static struct event_constraint counter2_constraint =
1696 EVENT_CONSTRAINT(0, 0x4, 0);
1697
1698static struct event_constraint *
1699hsw_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1700{
1701 struct event_constraint *c = intel_get_event_constraints(cpuc, event);
1702
1703
1704 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
1705 if (c->idxmsk64 & (1U << 2))
1706 return &counter2_constraint;
1707 return &emptyconstraint;
1708 }
1709
1710 return c;
1711}
1712
1713PMU_FORMAT_ATTR(event, "config:0-7" );
1714PMU_FORMAT_ATTR(umask, "config:8-15" );
1715PMU_FORMAT_ATTR(edge, "config:18" );
1716PMU_FORMAT_ATTR(pc, "config:19" );
1717PMU_FORMAT_ATTR(any, "config:21" );
1718PMU_FORMAT_ATTR(inv, "config:23" );
1719PMU_FORMAT_ATTR(cmask, "config:24-31" );
1720PMU_FORMAT_ATTR(in_tx, "config:32");
1721PMU_FORMAT_ATTR(in_tx_cp, "config:33");
1722
1723static struct attribute *intel_arch_formats_attr[] = {
1724 &format_attr_event.attr,
1725 &format_attr_umask.attr,
1726 &format_attr_edge.attr,
1727 &format_attr_pc.attr,
1728 &format_attr_inv.attr,
1729 &format_attr_cmask.attr,
1730 NULL,
1731};
1732
1733ssize_t intel_event_sysfs_show(char *page, u64 config)
1734{
1735 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
1736
1737 return x86_event_sysfs_show(page, config, event);
1738}
1739
1740static __initconst const struct x86_pmu core_pmu = {
1741 .name = "core",
1742 .handle_irq = x86_pmu_handle_irq,
1743 .disable_all = x86_pmu_disable_all,
1744 .enable_all = core_pmu_enable_all,
1745 .enable = core_pmu_enable_event,
1746 .disable = x86_pmu_disable_event,
1747 .hw_config = x86_pmu_hw_config,
1748 .schedule_events = x86_schedule_events,
1749 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1750 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1751 .event_map = intel_pmu_event_map,
1752 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1753 .apic = 1,
1754
1755
1756
1757
1758
1759 .max_period = (1ULL << 31) - 1,
1760 .get_event_constraints = intel_get_event_constraints,
1761 .put_event_constraints = intel_put_event_constraints,
1762 .event_constraints = intel_core_event_constraints,
1763 .guest_get_msrs = core_guest_get_msrs,
1764 .format_attrs = intel_arch_formats_attr,
1765 .events_sysfs_show = intel_event_sysfs_show,
1766};
1767
1768struct intel_shared_regs *allocate_shared_regs(int cpu)
1769{
1770 struct intel_shared_regs *regs;
1771 int i;
1772
1773 regs = kzalloc_node(sizeof(struct intel_shared_regs),
1774 GFP_KERNEL, cpu_to_node(cpu));
1775 if (regs) {
1776
1777
1778
1779 for (i = 0; i < EXTRA_REG_MAX; i++)
1780 raw_spin_lock_init(®s->regs[i].lock);
1781
1782 regs->core_id = -1;
1783 }
1784 return regs;
1785}
1786
1787static int intel_pmu_cpu_prepare(int cpu)
1788{
1789 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1790
1791 if (!(x86_pmu.extra_regs || x86_pmu.lbr_sel_map))
1792 return NOTIFY_OK;
1793
1794 cpuc->shared_regs = allocate_shared_regs(cpu);
1795 if (!cpuc->shared_regs)
1796 return NOTIFY_BAD;
1797
1798 return NOTIFY_OK;
1799}
1800
1801static void intel_pmu_cpu_starting(int cpu)
1802{
1803 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1804 int core_id = topology_core_id(cpu);
1805 int i;
1806
1807 init_debug_store_on_cpu(cpu);
1808
1809
1810
1811 intel_pmu_lbr_reset();
1812
1813 cpuc->lbr_sel = NULL;
1814
1815 if (!cpuc->shared_regs)
1816 return;
1817
1818 if (!(x86_pmu.er_flags & ERF_NO_HT_SHARING)) {
1819 for_each_cpu(i, topology_thread_cpumask(cpu)) {
1820 struct intel_shared_regs *pc;
1821
1822 pc = per_cpu(cpu_hw_events, i).shared_regs;
1823 if (pc && pc->core_id == core_id) {
1824 cpuc->kfree_on_online = cpuc->shared_regs;
1825 cpuc->shared_regs = pc;
1826 break;
1827 }
1828 }
1829 cpuc->shared_regs->core_id = core_id;
1830 cpuc->shared_regs->refcnt++;
1831 }
1832
1833 if (x86_pmu.lbr_sel_map)
1834 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
1835}
1836
1837static void intel_pmu_cpu_dying(int cpu)
1838{
1839 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1840 struct intel_shared_regs *pc;
1841
1842 pc = cpuc->shared_regs;
1843 if (pc) {
1844 if (pc->core_id == -1 || --pc->refcnt == 0)
1845 kfree(pc);
1846 cpuc->shared_regs = NULL;
1847 }
1848
1849 fini_debug_store_on_cpu(cpu);
1850}
1851
1852static void intel_pmu_flush_branch_stack(void)
1853{
1854
1855
1856
1857
1858
1859
1860 if (x86_pmu.lbr_nr)
1861 intel_pmu_lbr_reset();
1862}
1863
1864PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
1865
1866PMU_FORMAT_ATTR(ldlat, "config1:0-15");
1867
1868static struct attribute *intel_arch3_formats_attr[] = {
1869 &format_attr_event.attr,
1870 &format_attr_umask.attr,
1871 &format_attr_edge.attr,
1872 &format_attr_pc.attr,
1873 &format_attr_any.attr,
1874 &format_attr_inv.attr,
1875 &format_attr_cmask.attr,
1876 &format_attr_in_tx.attr,
1877 &format_attr_in_tx_cp.attr,
1878
1879 &format_attr_offcore_rsp.attr,
1880 &format_attr_ldlat.attr,
1881 NULL,
1882};
1883
1884static __initconst const struct x86_pmu intel_pmu = {
1885 .name = "Intel",
1886 .handle_irq = intel_pmu_handle_irq,
1887 .disable_all = intel_pmu_disable_all,
1888 .enable_all = intel_pmu_enable_all,
1889 .enable = intel_pmu_enable_event,
1890 .disable = intel_pmu_disable_event,
1891 .hw_config = intel_pmu_hw_config,
1892 .schedule_events = x86_schedule_events,
1893 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1894 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1895 .event_map = intel_pmu_event_map,
1896 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1897 .apic = 1,
1898
1899
1900
1901
1902
1903 .max_period = (1ULL << 31) - 1,
1904 .get_event_constraints = intel_get_event_constraints,
1905 .put_event_constraints = intel_put_event_constraints,
1906 .pebs_aliases = intel_pebs_aliases_core2,
1907
1908 .format_attrs = intel_arch3_formats_attr,
1909 .events_sysfs_show = intel_event_sysfs_show,
1910
1911 .cpu_prepare = intel_pmu_cpu_prepare,
1912 .cpu_starting = intel_pmu_cpu_starting,
1913 .cpu_dying = intel_pmu_cpu_dying,
1914 .guest_get_msrs = intel_guest_get_msrs,
1915 .flush_branch_stack = intel_pmu_flush_branch_stack,
1916};
1917
1918static __init void intel_clovertown_quirk(void)
1919{
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939 pr_warn("PEBS disabled due to CPU errata\n");
1940 x86_pmu.pebs = 0;
1941 x86_pmu.pebs_constraints = NULL;
1942}
1943
1944static int intel_snb_pebs_broken(int cpu)
1945{
1946 u32 rev = UINT_MAX;
1947
1948 switch (cpu_data(cpu).x86_model) {
1949 case 42:
1950 rev = 0x28;
1951 break;
1952
1953 case 45:
1954 switch (cpu_data(cpu).x86_mask) {
1955 case 6: rev = 0x618; break;
1956 case 7: rev = 0x70c; break;
1957 }
1958 }
1959
1960 return (cpu_data(cpu).microcode < rev);
1961}
1962
1963static void intel_snb_check_microcode(void)
1964{
1965 int pebs_broken = 0;
1966 int cpu;
1967
1968 get_online_cpus();
1969 for_each_online_cpu(cpu) {
1970 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
1971 break;
1972 }
1973 put_online_cpus();
1974
1975 if (pebs_broken == x86_pmu.pebs_broken)
1976 return;
1977
1978
1979
1980
1981 if (x86_pmu.pebs_broken) {
1982 pr_info("PEBS enabled due to microcode update\n");
1983 x86_pmu.pebs_broken = 0;
1984 } else {
1985 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
1986 x86_pmu.pebs_broken = 1;
1987 }
1988}
1989
1990static __init void intel_sandybridge_quirk(void)
1991{
1992 x86_pmu.check_microcode = intel_snb_check_microcode;
1993 intel_snb_check_microcode();
1994}
1995
1996static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
1997 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
1998 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
1999 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
2000 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
2001 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
2002 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
2003 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
2004};
2005
2006static __init void intel_arch_events_quirk(void)
2007{
2008 int bit;
2009
2010
2011 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
2012 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
2013 pr_warn("CPUID marked event: \'%s\' unavailable\n",
2014 intel_arch_events_map[bit].name);
2015 }
2016}
2017
2018static __init void intel_nehalem_quirk(void)
2019{
2020 union cpuid10_ebx ebx;
2021
2022 ebx.full = x86_pmu.events_maskl;
2023 if (ebx.split.no_branch_misses_retired) {
2024
2025
2026
2027
2028
2029
2030 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
2031 ebx.split.no_branch_misses_retired = 0;
2032 x86_pmu.events_maskl = ebx.full;
2033 pr_info("CPU erratum AAJ80 worked around\n");
2034 }
2035}
2036
2037EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
2038EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
2039
2040static struct attribute *hsw_events_attrs[] = {
2041 EVENT_PTR(mem_ld_hsw),
2042 EVENT_PTR(mem_st_hsw),
2043 NULL
2044};
2045
2046__init int intel_pmu_init(void)
2047{
2048 union cpuid10_edx edx;
2049 union cpuid10_eax eax;
2050 union cpuid10_ebx ebx;
2051 struct event_constraint *c;
2052 unsigned int unused;
2053 int version;
2054
2055 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
2056 switch (boot_cpu_data.x86) {
2057 case 0x6:
2058 return p6_pmu_init();
2059 case 0xb:
2060 return knc_pmu_init();
2061 case 0xf:
2062 return p4_pmu_init();
2063 }
2064 return -ENODEV;
2065 }
2066
2067
2068
2069
2070
2071 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
2072 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
2073 return -ENODEV;
2074
2075 version = eax.split.version_id;
2076 if (version < 2)
2077 x86_pmu = core_pmu;
2078 else
2079 x86_pmu = intel_pmu;
2080
2081 x86_pmu.version = version;
2082 x86_pmu.num_counters = eax.split.num_counters;
2083 x86_pmu.cntval_bits = eax.split.bit_width;
2084 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
2085
2086 x86_pmu.events_maskl = ebx.full;
2087 x86_pmu.events_mask_len = eax.split.mask_length;
2088
2089 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
2090
2091
2092
2093
2094
2095 if (version > 1)
2096 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
2097
2098
2099
2100
2101 if (version > 1) {
2102 u64 capabilities;
2103
2104 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
2105 x86_pmu.intel_cap.capabilities = capabilities;
2106 }
2107
2108 intel_ds_init();
2109
2110 x86_add_quirk(intel_arch_events_quirk);
2111
2112
2113
2114
2115 switch (boot_cpu_data.x86_model) {
2116 case 14:
2117 pr_cont("Core events, ");
2118 break;
2119
2120 case 15:
2121 x86_add_quirk(intel_clovertown_quirk);
2122 case 22:
2123 case 23:
2124 case 29:
2125 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
2126 sizeof(hw_cache_event_ids));
2127
2128 intel_pmu_lbr_init_core();
2129
2130 x86_pmu.event_constraints = intel_core2_event_constraints;
2131 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
2132 pr_cont("Core2 events, ");
2133 break;
2134
2135 case 26:
2136 case 30:
2137 case 46:
2138 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
2139 sizeof(hw_cache_event_ids));
2140 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2141 sizeof(hw_cache_extra_regs));
2142
2143 intel_pmu_lbr_init_nhm();
2144
2145 x86_pmu.event_constraints = intel_nehalem_event_constraints;
2146 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
2147 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
2148 x86_pmu.extra_regs = intel_nehalem_extra_regs;
2149
2150 x86_pmu.cpu_events = nhm_events_attrs;
2151
2152
2153 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2154 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2155
2156 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2157 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
2158
2159 x86_add_quirk(intel_nehalem_quirk);
2160
2161 pr_cont("Nehalem events, ");
2162 break;
2163
2164 case 28:
2165 case 38:
2166 case 39:
2167 case 53:
2168 case 54:
2169 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
2170 sizeof(hw_cache_event_ids));
2171
2172 intel_pmu_lbr_init_atom();
2173
2174 x86_pmu.event_constraints = intel_gen_event_constraints;
2175 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
2176 pr_cont("Atom events, ");
2177 break;
2178
2179 case 37:
2180 case 44:
2181 case 47:
2182 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
2183 sizeof(hw_cache_event_ids));
2184 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2185 sizeof(hw_cache_extra_regs));
2186
2187 intel_pmu_lbr_init_nhm();
2188
2189 x86_pmu.event_constraints = intel_westmere_event_constraints;
2190 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
2191 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
2192 x86_pmu.extra_regs = intel_westmere_extra_regs;
2193 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2194
2195 x86_pmu.cpu_events = nhm_events_attrs;
2196
2197
2198 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2199 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2200
2201 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2202 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
2203
2204 pr_cont("Westmere events, ");
2205 break;
2206
2207 case 42:
2208 case 45:
2209 x86_add_quirk(intel_sandybridge_quirk);
2210 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2211 sizeof(hw_cache_event_ids));
2212 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2213 sizeof(hw_cache_extra_regs));
2214
2215 intel_pmu_lbr_init_snb();
2216
2217 x86_pmu.event_constraints = intel_snb_event_constraints;
2218 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
2219 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
2220 if (boot_cpu_data.x86_model == 45)
2221 x86_pmu.extra_regs = intel_snbep_extra_regs;
2222 else
2223 x86_pmu.extra_regs = intel_snb_extra_regs;
2224
2225 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2226 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2227
2228 x86_pmu.cpu_events = snb_events_attrs;
2229
2230
2231 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2232 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2233
2234 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2235 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
2236
2237 pr_cont("SandyBridge events, ");
2238 break;
2239 case 58:
2240 case 62:
2241 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2242 sizeof(hw_cache_event_ids));
2243 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2244 sizeof(hw_cache_extra_regs));
2245
2246 intel_pmu_lbr_init_snb();
2247
2248 x86_pmu.event_constraints = intel_ivb_event_constraints;
2249 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
2250 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
2251 if (boot_cpu_data.x86_model == 62)
2252 x86_pmu.extra_regs = intel_snbep_extra_regs;
2253 else
2254 x86_pmu.extra_regs = intel_snb_extra_regs;
2255
2256 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2257 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2258
2259 x86_pmu.cpu_events = snb_events_attrs;
2260
2261
2262 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2263 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2264
2265 pr_cont("IvyBridge events, ");
2266 break;
2267
2268
2269 case 60:
2270 case 70:
2271 case 71:
2272 case 63:
2273 case 69:
2274 x86_pmu.late_ack = true;
2275 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids));
2276 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
2277
2278 intel_pmu_lbr_init_snb();
2279
2280 x86_pmu.event_constraints = intel_hsw_event_constraints;
2281 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
2282 x86_pmu.extra_regs = intel_snb_extra_regs;
2283 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
2284
2285 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2286 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2287
2288 x86_pmu.hw_config = hsw_hw_config;
2289 x86_pmu.get_event_constraints = hsw_get_event_constraints;
2290 x86_pmu.cpu_events = hsw_events_attrs;
2291 pr_cont("Haswell events, ");
2292 break;
2293
2294 default:
2295 switch (x86_pmu.version) {
2296 case 1:
2297 x86_pmu.event_constraints = intel_v1_event_constraints;
2298 pr_cont("generic architected perfmon v1, ");
2299 break;
2300 default:
2301
2302
2303
2304 x86_pmu.event_constraints = intel_gen_event_constraints;
2305 pr_cont("generic architected perfmon, ");
2306 break;
2307 }
2308 }
2309
2310 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
2311 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
2312 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
2313 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
2314 }
2315 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
2316
2317 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
2318 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
2319 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
2320 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
2321 }
2322
2323 x86_pmu.intel_ctrl |=
2324 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
2325
2326 if (x86_pmu.event_constraints) {
2327
2328
2329
2330
2331 for_each_event_constraint(c, x86_pmu.event_constraints) {
2332 if (c->cmask != FIXED_EVENT_FLAGS
2333 || c->idxmsk64 == INTEL_PMC_MSK_FIXED_REF_CYCLES) {
2334 continue;
2335 }
2336
2337 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
2338 c->weight += x86_pmu.num_counters;
2339 }
2340 }
2341
2342
2343 if (x86_pmu.intel_cap.full_width_write) {
2344 x86_pmu.max_period = x86_pmu.cntval_mask;
2345 x86_pmu.perfctr = MSR_IA32_PMC0;
2346 pr_cont("full-width counters, ");
2347 }
2348
2349 return 0;
2350}
2351