1#include <linux/linkage.h>
2#include <linux/errno.h>
3#include <linux/signal.h>
4#include <linux/sched.h>
5#include <linux/ioport.h>
6#include <linux/interrupt.h>
7#include <linux/timex.h>
8#include <linux/random.h>
9#include <linux/init.h>
10#include <linux/kernel_stat.h>
11#include <linux/syscore_ops.h>
12#include <linux/bitops.h>
13#include <linux/acpi.h>
14#include <linux/io.h>
15#include <linux/delay.h>
16
17#include <linux/atomic.h>
18#include <asm/timer.h>
19#include <asm/hw_irq.h>
20#include <asm/pgtable.h>
21#include <asm/desc.h>
22#include <asm/apic.h>
23#include <asm/i8259.h>
24
25
26
27
28
29
30
31static void init_8259A(int auto_eoi);
32
33static int i8259A_auto_eoi;
34DEFINE_RAW_SPINLOCK(i8259A_lock);
35
36
37
38
39
40
41
42
43unsigned int cached_irq_mask = 0xffff;
44
45
46
47
48
49
50
51
52
53
54unsigned long io_apic_irqs;
55
56static void mask_8259A_irq(unsigned int irq)
57{
58 unsigned int mask = 1 << irq;
59 unsigned long flags;
60
61 raw_spin_lock_irqsave(&i8259A_lock, flags);
62 cached_irq_mask |= mask;
63 if (irq & 8)
64 outb(cached_slave_mask, PIC_SLAVE_IMR);
65 else
66 outb(cached_master_mask, PIC_MASTER_IMR);
67 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
68}
69
70static void disable_8259A_irq(struct irq_data *data)
71{
72 mask_8259A_irq(data->irq);
73}
74
75static void unmask_8259A_irq(unsigned int irq)
76{
77 unsigned int mask = ~(1 << irq);
78 unsigned long flags;
79
80 raw_spin_lock_irqsave(&i8259A_lock, flags);
81 cached_irq_mask &= mask;
82 if (irq & 8)
83 outb(cached_slave_mask, PIC_SLAVE_IMR);
84 else
85 outb(cached_master_mask, PIC_MASTER_IMR);
86 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
87}
88
89static void enable_8259A_irq(struct irq_data *data)
90{
91 unmask_8259A_irq(data->irq);
92}
93
94static int i8259A_irq_pending(unsigned int irq)
95{
96 unsigned int mask = 1<<irq;
97 unsigned long flags;
98 int ret;
99
100 raw_spin_lock_irqsave(&i8259A_lock, flags);
101 if (irq < 8)
102 ret = inb(PIC_MASTER_CMD) & mask;
103 else
104 ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
105 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
106
107 return ret;
108}
109
110static void make_8259A_irq(unsigned int irq)
111{
112 disable_irq_nosync(irq);
113 io_apic_irqs &= ~(1<<irq);
114 irq_set_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq,
115 i8259A_chip.name);
116 enable_irq(irq);
117}
118
119
120
121
122
123
124
125static inline int i8259A_irq_real(unsigned int irq)
126{
127 int value;
128 int irqmask = 1<<irq;
129
130 if (irq < 8) {
131 outb(0x0B, PIC_MASTER_CMD);
132 value = inb(PIC_MASTER_CMD) & irqmask;
133 outb(0x0A, PIC_MASTER_CMD);
134 return value;
135 }
136 outb(0x0B, PIC_SLAVE_CMD);
137 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
138 outb(0x0A, PIC_SLAVE_CMD);
139 return value;
140}
141
142
143
144
145
146
147
148static void mask_and_ack_8259A(struct irq_data *data)
149{
150 unsigned int irq = data->irq;
151 unsigned int irqmask = 1 << irq;
152 unsigned long flags;
153
154 raw_spin_lock_irqsave(&i8259A_lock, flags);
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170 if (cached_irq_mask & irqmask)
171 goto spurious_8259A_irq;
172 cached_irq_mask |= irqmask;
173
174handle_real_irq:
175 if (irq & 8) {
176 inb(PIC_SLAVE_IMR);
177 outb(cached_slave_mask, PIC_SLAVE_IMR);
178
179 outb(0x60+(irq&7), PIC_SLAVE_CMD);
180
181 outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD);
182 } else {
183 inb(PIC_MASTER_IMR);
184 outb(cached_master_mask, PIC_MASTER_IMR);
185 outb(0x60+irq, PIC_MASTER_CMD);
186 }
187 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
188 return;
189
190spurious_8259A_irq:
191
192
193
194 if (i8259A_irq_real(irq))
195
196
197
198
199 goto handle_real_irq;
200
201 {
202 static int spurious_irq_mask;
203
204
205
206
207 if (!(spurious_irq_mask & irqmask)) {
208 printk(KERN_DEBUG
209 "spurious 8259A interrupt: IRQ%d.\n", irq);
210 spurious_irq_mask |= irqmask;
211 }
212 atomic_inc(&irq_err_count);
213
214
215
216
217
218 goto handle_real_irq;
219 }
220}
221
222struct irq_chip i8259A_chip = {
223 .name = "XT-PIC",
224 .irq_mask = disable_8259A_irq,
225 .irq_disable = disable_8259A_irq,
226 .irq_unmask = enable_8259A_irq,
227 .irq_mask_ack = mask_and_ack_8259A,
228};
229
230static char irq_trigger[2];
231
232
233
234static void restore_ELCR(char *trigger)
235{
236 outb(trigger[0], 0x4d0);
237 outb(trigger[1], 0x4d1);
238}
239
240static void save_ELCR(char *trigger)
241{
242
243 trigger[0] = inb(0x4d0) & 0xF8;
244 trigger[1] = inb(0x4d1) & 0xDE;
245}
246
247static void i8259A_resume(void)
248{
249 init_8259A(i8259A_auto_eoi);
250 restore_ELCR(irq_trigger);
251}
252
253static int i8259A_suspend(void)
254{
255 save_ELCR(irq_trigger);
256 return 0;
257}
258
259static void i8259A_shutdown(void)
260{
261
262
263
264
265 outb(0xff, PIC_MASTER_IMR);
266 outb(0xff, PIC_SLAVE_IMR);
267}
268
269static struct syscore_ops i8259_syscore_ops = {
270 .suspend = i8259A_suspend,
271 .resume = i8259A_resume,
272 .shutdown = i8259A_shutdown,
273};
274
275static void mask_8259A(void)
276{
277 unsigned long flags;
278
279 raw_spin_lock_irqsave(&i8259A_lock, flags);
280
281 outb(0xff, PIC_MASTER_IMR);
282 outb(0xff, PIC_SLAVE_IMR);
283
284 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
285}
286
287static void unmask_8259A(void)
288{
289 unsigned long flags;
290
291 raw_spin_lock_irqsave(&i8259A_lock, flags);
292
293 outb(cached_master_mask, PIC_MASTER_IMR);
294 outb(cached_slave_mask, PIC_SLAVE_IMR);
295
296 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
297}
298
299static void init_8259A(int auto_eoi)
300{
301 unsigned long flags;
302
303 i8259A_auto_eoi = auto_eoi;
304
305 raw_spin_lock_irqsave(&i8259A_lock, flags);
306
307 outb(0xff, PIC_MASTER_IMR);
308 outb(0xff, PIC_SLAVE_IMR);
309
310
311
312
313 outb_pic(0x11, PIC_MASTER_CMD);
314
315
316
317 outb_pic(IRQ0_VECTOR, PIC_MASTER_IMR);
318
319
320 outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);
321
322 if (auto_eoi)
323 outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
324 else
325 outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
326
327 outb_pic(0x11, PIC_SLAVE_CMD);
328
329
330 outb_pic(IRQ8_VECTOR, PIC_SLAVE_IMR);
331
332 outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);
333
334 outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);
335
336 if (auto_eoi)
337
338
339
340
341 i8259A_chip.irq_mask_ack = disable_8259A_irq;
342 else
343 i8259A_chip.irq_mask_ack = mask_and_ack_8259A;
344
345 udelay(100);
346
347 outb(cached_master_mask, PIC_MASTER_IMR);
348 outb(cached_slave_mask, PIC_SLAVE_IMR);
349
350 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
351}
352
353
354
355
356
357
358
359static void legacy_pic_noop(void) { };
360static void legacy_pic_uint_noop(unsigned int unused) { };
361static void legacy_pic_int_noop(int unused) { };
362static int legacy_pic_irq_pending_noop(unsigned int irq)
363{
364 return 0;
365}
366
367struct legacy_pic null_legacy_pic = {
368 .nr_legacy_irqs = 0,
369 .chip = &dummy_irq_chip,
370 .mask = legacy_pic_uint_noop,
371 .unmask = legacy_pic_uint_noop,
372 .mask_all = legacy_pic_noop,
373 .restore_mask = legacy_pic_noop,
374 .init = legacy_pic_int_noop,
375 .irq_pending = legacy_pic_irq_pending_noop,
376 .make_irq = legacy_pic_uint_noop,
377};
378
379struct legacy_pic default_legacy_pic = {
380 .nr_legacy_irqs = NR_IRQS_LEGACY,
381 .chip = &i8259A_chip,
382 .mask = mask_8259A_irq,
383 .unmask = unmask_8259A_irq,
384 .mask_all = mask_8259A,
385 .restore_mask = unmask_8259A,
386 .init = init_8259A,
387 .irq_pending = i8259A_irq_pending,
388 .make_irq = make_8259A_irq,
389};
390
391struct legacy_pic *legacy_pic = &default_legacy_pic;
392
393static int __init i8259A_init_ops(void)
394{
395 if (legacy_pic == &default_legacy_pic)
396 register_syscore_ops(&i8259_syscore_ops);
397
398 return 0;
399}
400
401device_initcall(i8259A_init_ops);
402